// Generator : SpinalHDL v1.3.3 git head : 8b8cd335eecbea3b5f1f970f218a982dbdb12d99 // Date : 26/04/2019, 01:10:32 // Component : VexRiscv `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 `define Src1CtrlEnum_defaultEncoding_type [1:0] `define Src1CtrlEnum_defaultEncoding_RS 2'b00 `define Src1CtrlEnum_defaultEncoding_IMU 2'b01 `define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 `define AluCtrlEnum_defaultEncoding_type [1:0] `define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 `define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 `define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 `define EnvCtrlEnum_defaultEncoding_type [1:0] `define EnvCtrlEnum_defaultEncoding_NONE 2'b00 `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 `define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 module InstructionCache ( input io_flush, input io_cpu_prefetch_isValid, output reg io_cpu_prefetch_haltIt, input [31:0] io_cpu_prefetch_pc, input io_cpu_fetch_isValid, input io_cpu_fetch_isStuck, input io_cpu_fetch_isRemoved, input [31:0] io_cpu_fetch_pc, output [31:0] io_cpu_fetch_data, input io_cpu_fetch_dataBypassValid, input [31:0] io_cpu_fetch_dataBypass, output io_cpu_fetch_mmuBus_cmd_isValid, output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, output io_cpu_fetch_mmuBus_cmd_bypassTranslation, input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, input io_cpu_fetch_mmuBus_rsp_isIoAccess, input io_cpu_fetch_mmuBus_rsp_allowRead, input io_cpu_fetch_mmuBus_rsp_allowWrite, input io_cpu_fetch_mmuBus_rsp_allowExecute, input io_cpu_fetch_mmuBus_rsp_exception, input io_cpu_fetch_mmuBus_rsp_refilling, output io_cpu_fetch_mmuBus_end, input io_cpu_fetch_mmuBus_busy, output [31:0] io_cpu_fetch_physicalAddress, output io_cpu_fetch_cacheMiss, output io_cpu_fetch_error, output io_cpu_fetch_mmuRefilling, output io_cpu_fetch_mmuException, input io_cpu_fetch_isUser, output io_cpu_fetch_haltIt, input io_cpu_decode_isValid, input io_cpu_decode_isStuck, input [31:0] io_cpu_decode_pc, output [31:0] io_cpu_decode_physicalAddress, output [31:0] io_cpu_decode_data, input io_cpu_fill_valid, input [31:0] io_cpu_fill_payload, output io_mem_cmd_valid, input io_mem_cmd_ready, output [31:0] io_mem_cmd_payload_address, output [2:0] io_mem_cmd_payload_size, input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, input clk, input reset); reg [22:0] _zz_10_; reg [31:0] _zz_11_; wire _zz_12_; wire _zz_13_; wire [0:0] _zz_14_; wire [0:0] _zz_15_; wire [22:0] _zz_16_; reg _zz_1_; reg _zz_2_; reg lineLoader_fire; reg lineLoader_valid; reg [31:0] lineLoader_address; reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; reg _zz_3_; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; wire lineLoader_wayToAllocate_willOverflow; reg [2:0] lineLoader_wordIndex; wire lineLoader_write_tag_0_valid; wire [5:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; wire [20:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; wire _zz_4_; wire [5:0] _zz_5_; wire _zz_6_; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; wire [22:0] _zz_7_; wire [8:0] _zz_8_; wire _zz_9_; wire [31:0] fetchStage_read_waysValues_0_data; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; reg [22:0] ways_0_tags [0:63]; reg [31:0] ways_0_datas [0:511]; assign _zz_12_ = (! lineLoader_flushCounter[6]); assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); assign _zz_14_ = _zz_7_[0 : 0]; assign _zz_15_ = _zz_7_[1 : 1]; assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; always @ (posedge clk) begin if(_zz_2_) begin ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; end end always @ (posedge clk) begin if(_zz_6_) begin _zz_10_ <= ways_0_tags[_zz_5_]; end end always @ (posedge clk) begin if(_zz_1_) begin ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end always @ (posedge clk) begin if(_zz_9_) begin _zz_11_ <= ways_0_datas[_zz_8_]; end end always @ (*) begin _zz_1_ = 1'b0; if(lineLoader_write_data_0_valid)begin _zz_1_ = 1'b1; end end always @ (*) begin _zz_2_ = 1'b0; if(lineLoader_write_tag_0_valid)begin _zz_2_ = 1'b1; end end assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; always @ (*) begin lineLoader_fire = 1'b0; if(io_mem_rsp_valid)begin if((lineLoader_wordIndex == (3'b111)))begin lineLoader_fire = 1'b1; end end end always @ (*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); if(_zz_12_)begin io_cpu_prefetch_haltIt = 1'b1; end if((! _zz_3_))begin io_cpu_prefetch_haltIt = 1'b1; end if(io_flush)begin io_cpu_prefetch_haltIt = 1'b1; end end assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; assign io_mem_cmd_payload_size = (3'b101); always @ (*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; if(lineLoader_fire)begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); assign _zz_4_ = 1'b1; assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; assign _zz_5_ = io_cpu_prefetch_pc[10 : 5]; assign _zz_6_ = (! io_cpu_fetch_isStuck); assign _zz_7_ = _zz_10_; assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2]; assign _zz_8_ = io_cpu_prefetch_pc[10 : 2]; assign _zz_9_ = (! io_cpu_fetch_isStuck); assign fetchStage_read_waysValues_0_data = _zz_11_; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); assign io_cpu_fetch_error = fetchStage_hit_error; assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); always @ (posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= (3'b000); end else begin if(lineLoader_fire)begin lineLoader_valid <= 1'b0; end if(lineLoader_fire)begin lineLoader_hadError <= 1'b0; end if(io_cpu_fill_valid)begin lineLoader_valid <= 1'b1; end if(io_flush)begin lineLoader_flushPending <= 1'b1; end if(_zz_13_)begin lineLoader_flushPending <= 1'b0; end if((io_mem_cmd_valid && io_mem_cmd_ready))begin lineLoader_cmdSent <= 1'b1; end if(lineLoader_fire)begin lineLoader_cmdSent <= 1'b0; end if(io_mem_rsp_valid)begin lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); if(io_mem_rsp_payload_error)begin lineLoader_hadError <= 1'b1; end end end end always @ (posedge clk) begin if(io_cpu_fill_valid)begin lineLoader_address <= io_cpu_fill_payload; end if(_zz_12_)begin lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); end _zz_3_ <= lineLoader_flushCounter[6]; if(_zz_13_)begin lineLoader_flushCounter <= (7'b0000000); end end endmodule module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, input [31:0] externalInterruptArray, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, output iBusWishbone_WE, output [29:0] iBusWishbone_ADR, input [31:0] iBusWishbone_DAT_MISO, output [31:0] iBusWishbone_DAT_MOSI, output [3:0] iBusWishbone_SEL, input iBusWishbone_ERR, output [1:0] iBusWishbone_BTE, output [2:0] iBusWishbone_CTI, output dBusWishbone_CYC, output dBusWishbone_STB, input dBusWishbone_ACK, output dBusWishbone_WE, output [29:0] dBusWishbone_ADR, input [31:0] dBusWishbone_DAT_MISO, output [31:0] dBusWishbone_DAT_MOSI, output reg [3:0] dBusWishbone_SEL, input dBusWishbone_ERR, output [1:0] dBusWishbone_BTE, output [2:0] dBusWishbone_CTI, input clk, input reset); wire _zz_131_; wire _zz_132_; wire _zz_133_; wire _zz_134_; wire _zz_135_; wire [31:0] _zz_136_; wire _zz_137_; wire _zz_138_; wire _zz_139_; wire _zz_140_; wire _zz_141_; wire _zz_142_; wire _zz_143_; wire _zz_144_; wire _zz_145_; wire _zz_146_; wire [31:0] _zz_147_; reg _zz_148_; reg [31:0] _zz_149_; reg [31:0] _zz_150_; reg [31:0] _zz_151_; reg [3:0] _zz_152_; reg [31:0] _zz_153_; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire IBusCachedPlugin_cache_io_cpu_fetch_error; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; wire _zz_154_; wire _zz_155_; wire _zz_156_; wire _zz_157_; wire _zz_158_; wire _zz_159_; wire [1:0] _zz_160_; wire _zz_161_; wire _zz_162_; wire _zz_163_; wire [1:0] _zz_164_; wire _zz_165_; wire [2:0] _zz_166_; wire [2:0] _zz_167_; wire [31:0] _zz_168_; wire [2:0] _zz_169_; wire [0:0] _zz_170_; wire [0:0] _zz_171_; wire [0:0] _zz_172_; wire [0:0] _zz_173_; wire [0:0] _zz_174_; wire [0:0] _zz_175_; wire [0:0] _zz_176_; wire [0:0] _zz_177_; wire [0:0] _zz_178_; wire [2:0] _zz_179_; wire [4:0] _zz_180_; wire [11:0] _zz_181_; wire [11:0] _zz_182_; wire [31:0] _zz_183_; wire [31:0] _zz_184_; wire [31:0] _zz_185_; wire [31:0] _zz_186_; wire [31:0] _zz_187_; wire [31:0] _zz_188_; wire [31:0] _zz_189_; wire [31:0] _zz_190_; wire [32:0] _zz_191_; wire [19:0] _zz_192_; wire [11:0] _zz_193_; wire [11:0] _zz_194_; wire [1:0] _zz_195_; wire [1:0] _zz_196_; wire [2:0] _zz_197_; wire [0:0] _zz_198_; wire [0:0] _zz_199_; wire [0:0] _zz_200_; wire [0:0] _zz_201_; wire [0:0] _zz_202_; wire [0:0] _zz_203_; wire [26:0] _zz_204_; wire [6:0] _zz_205_; wire [1:0] _zz_206_; wire [31:0] _zz_207_; wire [31:0] _zz_208_; wire _zz_209_; wire _zz_210_; wire [31:0] _zz_211_; wire [31:0] _zz_212_; wire [0:0] _zz_213_; wire [0:0] _zz_214_; wire [0:0] _zz_215_; wire [0:0] _zz_216_; wire _zz_217_; wire [0:0] _zz_218_; wire [20:0] _zz_219_; wire [31:0] _zz_220_; wire [31:0] _zz_221_; wire [31:0] _zz_222_; wire [31:0] _zz_223_; wire [0:0] _zz_224_; wire [2:0] _zz_225_; wire [0:0] _zz_226_; wire [0:0] _zz_227_; wire _zz_228_; wire [0:0] _zz_229_; wire [17:0] _zz_230_; wire [31:0] _zz_231_; wire [31:0] _zz_232_; wire [31:0] _zz_233_; wire _zz_234_; wire _zz_235_; wire [31:0] _zz_236_; wire _zz_237_; wire _zz_238_; wire [0:0] _zz_239_; wire [4:0] _zz_240_; wire [1:0] _zz_241_; wire [1:0] _zz_242_; wire _zz_243_; wire [0:0] _zz_244_; wire [14:0] _zz_245_; wire [31:0] _zz_246_; wire [31:0] _zz_247_; wire [31:0] _zz_248_; wire [31:0] _zz_249_; wire _zz_250_; wire [0:0] _zz_251_; wire [2:0] _zz_252_; wire _zz_253_; wire _zz_254_; wire _zz_255_; wire [0:0] _zz_256_; wire [0:0] _zz_257_; wire _zz_258_; wire [0:0] _zz_259_; wire [12:0] _zz_260_; wire [31:0] _zz_261_; wire [31:0] _zz_262_; wire [31:0] _zz_263_; wire [0:0] _zz_264_; wire [0:0] _zz_265_; wire [31:0] _zz_266_; wire [31:0] _zz_267_; wire [31:0] _zz_268_; wire [31:0] _zz_269_; wire [31:0] _zz_270_; wire [0:0] _zz_271_; wire [0:0] _zz_272_; wire [0:0] _zz_273_; wire [0:0] _zz_274_; wire _zz_275_; wire [0:0] _zz_276_; wire [10:0] _zz_277_; wire [31:0] _zz_278_; wire [31:0] _zz_279_; wire [31:0] _zz_280_; wire [31:0] _zz_281_; wire [31:0] _zz_282_; wire [31:0] _zz_283_; wire [31:0] _zz_284_; wire [0:0] _zz_285_; wire [0:0] _zz_286_; wire [0:0] _zz_287_; wire [0:0] _zz_288_; wire _zz_289_; wire [0:0] _zz_290_; wire [7:0] _zz_291_; wire [31:0] _zz_292_; wire [31:0] _zz_293_; wire [31:0] _zz_294_; wire _zz_295_; wire _zz_296_; wire [1:0] _zz_297_; wire [1:0] _zz_298_; wire _zz_299_; wire [0:0] _zz_300_; wire [4:0] _zz_301_; wire [31:0] _zz_302_; wire [31:0] _zz_303_; wire _zz_304_; wire [0:0] _zz_305_; wire [0:0] _zz_306_; wire [1:0] _zz_307_; wire [1:0] _zz_308_; wire _zz_309_; wire [0:0] _zz_310_; wire [1:0] _zz_311_; wire [31:0] _zz_312_; wire [31:0] _zz_313_; wire [31:0] _zz_314_; wire [31:0] _zz_315_; wire _zz_316_; wire _zz_317_; wire [1:0] _zz_318_; wire [1:0] _zz_319_; wire [0:0] _zz_320_; wire [0:0] _zz_321_; wire [31:0] _zz_322_; wire [31:0] _zz_323_; wire [31:0] _zz_324_; wire _zz_325_; wire [0:0] _zz_326_; wire [12:0] _zz_327_; wire [31:0] _zz_328_; wire [31:0] _zz_329_; wire [31:0] _zz_330_; wire _zz_331_; wire [0:0] _zz_332_; wire [6:0] _zz_333_; wire [31:0] _zz_334_; wire [31:0] _zz_335_; wire [31:0] _zz_336_; wire _zz_337_; wire [0:0] _zz_338_; wire [0:0] _zz_339_; wire decode_IS_CSR; wire execute_REGFILE_WRITE_VALID; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_1_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_2_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_3_; wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; wire `Src1CtrlEnum_defaultEncoding_type _zz_4_; wire `Src1CtrlEnum_defaultEncoding_type _zz_5_; wire `Src1CtrlEnum_defaultEncoding_type _zz_6_; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_7_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_9_; wire decode_CSR_WRITE_OPCODE; wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; wire `Src2CtrlEnum_defaultEncoding_type _zz_10_; wire `Src2CtrlEnum_defaultEncoding_type _zz_11_; wire `Src2CtrlEnum_defaultEncoding_type _zz_12_; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; wire `AluCtrlEnum_defaultEncoding_type _zz_13_; wire `AluCtrlEnum_defaultEncoding_type _zz_14_; wire `AluCtrlEnum_defaultEncoding_type _zz_15_; wire decode_MEMORY_STORE; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; wire `BranchCtrlEnum_defaultEncoding_type _zz_16_; wire `BranchCtrlEnum_defaultEncoding_type _zz_17_; wire `BranchCtrlEnum_defaultEncoding_type _zz_18_; wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_19_; wire `EnvCtrlEnum_defaultEncoding_type _zz_20_; wire `EnvCtrlEnum_defaultEncoding_type _zz_21_; wire decode_SRC2_FORCE_ZERO; wire decode_CSR_READ_OPCODE; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; wire _zz_22_; wire _zz_23_; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] _zz_25_; wire [31:0] execute_RS1; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; wire `BranchCtrlEnum_defaultEncoding_type _zz_26_; wire _zz_27_; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_28_; wire _zz_29_; wire [31:0] _zz_30_; wire [31:0] _zz_31_; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; wire `Src2CtrlEnum_defaultEncoding_type _zz_32_; wire [31:0] _zz_33_; wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; wire `Src1CtrlEnum_defaultEncoding_type _zz_34_; wire [31:0] _zz_35_; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire _zz_36_; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; wire `AluCtrlEnum_defaultEncoding_type _zz_37_; wire [31:0] _zz_38_; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39_; reg _zz_40_; wire [31:0] _zz_41_; wire [31:0] _zz_42_; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; wire decode_INSTRUCTION_READY; wire _zz_43_; wire `BranchCtrlEnum_defaultEncoding_type _zz_44_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_45_; wire _zz_46_; wire _zz_47_; wire _zz_48_; wire `EnvCtrlEnum_defaultEncoding_type _zz_49_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_50_; wire _zz_51_; wire _zz_52_; wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; wire _zz_54_; wire `Src2CtrlEnum_defaultEncoding_type _zz_55_; wire _zz_56_; wire `AluCtrlEnum_defaultEncoding_type _zz_57_; wire _zz_58_; wire [31:0] decode_INSTRUCTION; reg [31:0] _zz_59_; wire [1:0] execute_MEMORY_ADDRESS_LOW; wire [31:0] execute_MEMORY_READ_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [31:0] _zz_60_; wire [31:0] execute_SRC_ADD; wire [1:0] _zz_61_; wire [31:0] execute_RS2; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; wire _zz_62_; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected; reg _zz_63_; reg _zz_64_; reg _zz_65_; reg [31:0] _zz_66_; wire [31:0] decode_PC; wire [31:0] _zz_67_; wire [31:0] _zz_68_; wire [31:0] _zz_69_; wire [31:0] execute_PC; wire [31:0] execute_INSTRUCTION; wire decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; reg decode_arbitration_flushAll; wire decode_arbitration_isValid; wire decode_arbitration_isStuck; wire decode_arbitration_isStuckByOthers; wire decode_arbitration_isFlushed; wire decode_arbitration_isMoving; wire decode_arbitration_isFiring; reg execute_arbitration_haltItself; wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; wire execute_arbitration_flushAll; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; wire execute_arbitration_isStuckByOthers; wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; wire [31:0] lastStageInstruction /* verilator public */ ; wire [31:0] lastStagePc /* verilator public */ ; wire lastStageIsValid /* verilator public */ ; wire lastStageIsFiring /* verilator public */ ; reg IBusCachedPlugin_fetcherHalt; wire IBusCachedPlugin_fetcherflushIt; reg IBusCachedPlugin_incomingInstruction; wire IBusCachedPlugin_pcValids_0; wire IBusCachedPlugin_pcValids_1; wire IBusCachedPlugin_redoBranch_valid; wire [31:0] IBusCachedPlugin_redoBranch_payload; reg IBusCachedPlugin_decodeExceptionPort_valid; reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; reg CsrPlugin_jumpInterface_valid; reg [31:0] CsrPlugin_jumpInterface_payload; wire CsrPlugin_exceptionPendings_0; wire CsrPlugin_exceptionPendings_1; wire externalInterrupt; wire contextSwitching; reg [1:0] CsrPlugin_privilege; wire CsrPlugin_forceMachineWire; reg CsrPlugin_selfException_valid; reg [3:0] CsrPlugin_selfException_payload_code; wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; wire [2:0] _zz_70_; wire [2:0] _zz_71_; wire _zz_72_; wire _zz_73_; wire IBusCachedPlugin_fetchPc_preOutput_valid; wire IBusCachedPlugin_fetchPc_preOutput_ready; wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; wire _zz_74_; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_inc; reg IBusCachedPlugin_fetchPc_propagatePc; reg [31:0] IBusCachedPlugin_fetchPc_pc; reg IBusCachedPlugin_fetchPc_samplePcNext; reg _zz_75_; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; reg IBusCachedPlugin_iBusRsp_stages_0_halt; wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; wire _zz_76_; wire _zz_77_; wire _zz_78_; wire _zz_79_; reg _zz_80_; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_decodeInput_valid; wire IBusCachedPlugin_iBusRsp_decodeInput_ready; wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; reg IBusCachedPlugin_injector_decodeRemoved; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; wire [2:0] iBus_cmd_payload_size; wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; wire IBusCachedPlugin_rsp_iBusRspOutputHalt; reg IBusCachedPlugin_rsp_redoFetch; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [1:0] dBus_cmd_payload_size; wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; reg _zz_81_; reg execute_DBusSimplePlugin_skipCmd; reg [31:0] _zz_82_; reg [3:0] _zz_83_; wire [3:0] execute_DBusSimplePlugin_formalMask; reg [31:0] execute_DBusSimplePlugin_rspShifted; wire _zz_84_; reg [31:0] _zz_85_; wire _zz_86_; reg [31:0] _zz_87_; reg [31:0] execute_DBusSimplePlugin_rspFormated; wire [26:0] _zz_88_; wire _zz_89_; wire _zz_90_; wire _zz_91_; wire _zz_92_; wire `AluCtrlEnum_defaultEncoding_type _zz_93_; wire `Src2CtrlEnum_defaultEncoding_type _zz_94_; wire `Src1CtrlEnum_defaultEncoding_type _zz_95_; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_96_; wire `EnvCtrlEnum_defaultEncoding_type _zz_97_; wire `ShiftCtrlEnum_defaultEncoding_type _zz_98_; wire `BranchCtrlEnum_defaultEncoding_type _zz_99_; wire [4:0] execute_RegFilePlugin_regFileReadAddress1; wire [4:0] execute_RegFilePlugin_regFileReadAddress2; wire _zz_100_; wire [31:0] execute_RegFilePlugin_rs1Data; wire [31:0] execute_RegFilePlugin_rs2Data; wire lastStageRegFileWrite_valid /* verilator public */ ; wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; reg [31:0] execute_IntAluPlugin_bitwise; reg [31:0] _zz_101_; reg [31:0] _zz_102_; wire _zz_103_; reg [19:0] _zz_104_; wire _zz_105_; reg [19:0] _zz_106_; reg [31:0] _zz_107_; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; wire execute_LightShifterPlugin_isShift; reg [4:0] execute_LightShifterPlugin_amplitudeReg; wire [4:0] execute_LightShifterPlugin_amplitude; reg [31:0] execute_LightShifterPlugin_shiftReg; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; reg [31:0] _zz_108_; wire execute_BranchPlugin_eq; wire [2:0] _zz_109_; reg _zz_110_; reg _zz_111_; wire [31:0] execute_BranchPlugin_branch_src1; wire _zz_112_; reg [10:0] _zz_113_; wire _zz_114_; reg [19:0] _zz_115_; wire _zz_116_; reg [18:0] _zz_117_; reg [31:0] _zz_118_; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; reg [29:0] CsrPlugin_mtvec_base; reg [31:0] CsrPlugin_mepc; reg CsrPlugin_mstatus_MIE; reg CsrPlugin_mstatus_MPIE; reg [1:0] CsrPlugin_mstatus_MPP; reg CsrPlugin_mip_MEIP; reg CsrPlugin_mip_MTIP; reg CsrPlugin_mip_MSIP; reg CsrPlugin_mie_MEIE; reg CsrPlugin_mie_MTIE; reg CsrPlugin_mie_MSIE; reg [31:0] CsrPlugin_mscratch; reg CsrPlugin_mcause_interrupt; reg [3:0] CsrPlugin_mcause_exceptionCode; reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; wire [1:0] _zz_119_; wire _zz_120_; wire [2:0] _zz_121_; wire [2:0] _zz_122_; wire _zz_123_; wire _zz_124_; wire [1:0] _zz_125_; reg CsrPlugin_interrupt; reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; reg [1:0] CsrPlugin_interruptTargetPrivilege; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_done; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; wire execute_CsrPlugin_inWfi /* verilator public */ ; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; reg [31:0] execute_CsrPlugin_readData; wire execute_CsrPlugin_writeInstruction; wire execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; reg [31:0] _zz_126_; reg [31:0] externalInterruptArray_regNext; wire [31:0] _zz_127_; reg decode_to_execute_MEMORY_ENABLE; reg decode_to_execute_SRC_LESS_UNSIGNED; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_CSR_READ_OPCODE; reg decode_to_execute_SRC2_FORCE_ZERO; reg [31:0] decode_to_execute_INSTRUCTION; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_MEMORY_STORE; reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; reg decode_to_execute_CSR_WRITE_OPCODE; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; reg [31:0] decode_to_execute_PC; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; reg decode_to_execute_REGFILE_WRITE_VALID; reg decode_to_execute_IS_CSR; reg [2:0] _zz_128_; reg _zz_129_; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; wire dBus_cmd_halfPipe_payload_wr; wire [31:0] dBus_cmd_halfPipe_payload_address; wire [31:0] dBus_cmd_halfPipe_payload_data; wire [1:0] dBus_cmd_halfPipe_payload_size; reg dBus_cmd_halfPipe_regs_valid; reg dBus_cmd_halfPipe_regs_ready; reg dBus_cmd_halfPipe_regs_payload_wr; reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; reg [3:0] _zz_130_; `ifndef SYNTHESIS reg [71:0] decode_SHIFT_CTRL_string; reg [71:0] _zz_1__string; reg [71:0] _zz_2__string; reg [71:0] _zz_3__string; reg [95:0] decode_SRC1_CTRL_string; reg [95:0] _zz_4__string; reg [95:0] _zz_5__string; reg [95:0] _zz_6__string; reg [39:0] decode_ALU_BITWISE_CTRL_string; reg [39:0] _zz_7__string; reg [39:0] _zz_8__string; reg [39:0] _zz_9__string; reg [23:0] decode_SRC2_CTRL_string; reg [23:0] _zz_10__string; reg [23:0] _zz_11__string; reg [23:0] _zz_12__string; reg [63:0] decode_ALU_CTRL_string; reg [63:0] _zz_13__string; reg [63:0] _zz_14__string; reg [63:0] _zz_15__string; reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_16__string; reg [31:0] _zz_17__string; reg [31:0] _zz_18__string; reg [47:0] decode_ENV_CTRL_string; reg [47:0] _zz_19__string; reg [47:0] _zz_20__string; reg [47:0] _zz_21__string; reg [47:0] execute_ENV_CTRL_string; reg [47:0] _zz_24__string; reg [31:0] execute_BRANCH_CTRL_string; reg [31:0] _zz_26__string; reg [71:0] execute_SHIFT_CTRL_string; reg [71:0] _zz_28__string; reg [23:0] execute_SRC2_CTRL_string; reg [23:0] _zz_32__string; reg [95:0] execute_SRC1_CTRL_string; reg [95:0] _zz_34__string; reg [63:0] execute_ALU_CTRL_string; reg [63:0] _zz_37__string; reg [39:0] execute_ALU_BITWISE_CTRL_string; reg [39:0] _zz_39__string; reg [31:0] _zz_44__string; reg [71:0] _zz_45__string; reg [47:0] _zz_49__string; reg [39:0] _zz_50__string; reg [95:0] _zz_53__string; reg [23:0] _zz_55__string; reg [63:0] _zz_57__string; reg [63:0] _zz_93__string; reg [23:0] _zz_94__string; reg [95:0] _zz_95__string; reg [39:0] _zz_96__string; reg [47:0] _zz_97__string; reg [71:0] _zz_98__string; reg [31:0] _zz_99__string; reg [47:0] decode_to_execute_ENV_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; `endif reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; assign _zz_154_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); assign _zz_155_ = (! execute_arbitration_isStuckByOthers); assign _zz_156_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); assign _zz_157_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000)); assign _zz_158_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); assign _zz_159_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); assign _zz_160_ = execute_INSTRUCTION[29 : 28]; assign _zz_161_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); assign _zz_162_ = (iBus_cmd_valid || (_zz_128_ != (3'b000))); assign _zz_163_ = (! dBus_cmd_halfPipe_regs_valid); assign _zz_164_ = execute_INSTRUCTION[13 : 12]; assign _zz_165_ = execute_INSTRUCTION[13]; assign _zz_166_ = (_zz_70_ - (3'b001)); assign _zz_167_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; assign _zz_168_ = {29'd0, _zz_167_}; assign _zz_169_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100)); assign _zz_170_ = _zz_88_[2 : 2]; assign _zz_171_ = _zz_88_[5 : 5]; assign _zz_172_ = _zz_88_[10 : 10]; assign _zz_173_ = _zz_88_[11 : 11]; assign _zz_174_ = _zz_88_[16 : 16]; assign _zz_175_ = _zz_88_[17 : 17]; assign _zz_176_ = _zz_88_[18 : 18]; assign _zz_177_ = _zz_88_[26 : 26]; assign _zz_178_ = execute_SRC_LESS; assign _zz_179_ = (3'b100); assign _zz_180_ = execute_INSTRUCTION[19 : 15]; assign _zz_181_ = execute_INSTRUCTION[31 : 20]; assign _zz_182_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; assign _zz_183_ = ($signed(_zz_184_) + $signed(_zz_187_)); assign _zz_184_ = ($signed(_zz_185_) + $signed(_zz_186_)); assign _zz_185_ = execute_SRC1; assign _zz_186_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); assign _zz_187_ = (execute_SRC_USE_SUB_LESS ? _zz_188_ : _zz_189_); assign _zz_188_ = (32'b00000000000000000000000000000001); assign _zz_189_ = (32'b00000000000000000000000000000000); assign _zz_190_ = (_zz_191_ >>> 1); assign _zz_191_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; assign _zz_192_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; assign _zz_193_ = execute_INSTRUCTION[31 : 20]; assign _zz_194_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; assign _zz_195_ = (_zz_119_ & (~ _zz_196_)); assign _zz_196_ = (_zz_119_ - (2'b01)); assign _zz_197_ = (_zz_121_ - (3'b001)); assign _zz_198_ = execute_CsrPlugin_writeData[7 : 7]; assign _zz_199_ = execute_CsrPlugin_writeData[3 : 3]; assign _zz_200_ = execute_CsrPlugin_writeData[3 : 3]; assign _zz_201_ = execute_CsrPlugin_writeData[11 : 11]; assign _zz_202_ = execute_CsrPlugin_writeData[7 : 7]; assign _zz_203_ = execute_CsrPlugin_writeData[3 : 3]; assign _zz_204_ = (iBus_cmd_payload_address >>> 5); assign _zz_205_ = ({3'd0,_zz_130_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); assign _zz_206_ = {_zz_73_,_zz_72_}; assign _zz_207_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); assign _zz_208_ = (32'b00000000000000000000000001000000); assign _zz_209_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000)); assign _zz_210_ = ((decode_INSTRUCTION & (32'b01000000000000000100000000110100)) == (32'b01000000000000000000000000110000)); assign _zz_211_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010000)); assign _zz_212_ = (32'b00000000000000000000000000010000); assign _zz_213_ = _zz_92_; assign _zz_214_ = ((decode_INSTRUCTION & _zz_220_) == (32'b00000000000000000000000000000100)); assign _zz_215_ = ((decode_INSTRUCTION & _zz_221_) == (32'b00000000000000000000000001000000)); assign _zz_216_ = (1'b0); assign _zz_217_ = ((_zz_222_ == _zz_223_) != (1'b0)); assign _zz_218_ = ({_zz_224_,_zz_225_} != (4'b0000)); assign _zz_219_ = {(_zz_226_ != _zz_227_),{_zz_228_,{_zz_229_,_zz_230_}}}; assign _zz_220_ = (32'b00000000000000000000000000011100); assign _zz_221_ = (32'b00000000000000000000000001011000); assign _zz_222_ = (decode_INSTRUCTION & (32'b00000000000000000000000000000000)); assign _zz_223_ = (32'b00000000000000000000000000000000); assign _zz_224_ = ((decode_INSTRUCTION & _zz_231_) == (32'b00000000000000000000000000000000)); assign _zz_225_ = {(_zz_232_ == _zz_233_),{_zz_234_,_zz_235_}}; assign _zz_226_ = ((decode_INSTRUCTION & _zz_236_) == (32'b00000000000000000101000000010000)); assign _zz_227_ = (1'b0); assign _zz_228_ = ({_zz_237_,_zz_238_} != (2'b00)); assign _zz_229_ = ({_zz_239_,_zz_240_} != (6'b000000)); assign _zz_230_ = {(_zz_241_ != _zz_242_),{_zz_243_,{_zz_244_,_zz_245_}}}; assign _zz_231_ = (32'b00000000000000000000000001000100); assign _zz_232_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); assign _zz_233_ = (32'b00000000000000000000000000000000); assign _zz_234_ = ((decode_INSTRUCTION & _zz_246_) == (32'b00000000000000000010000000000000)); assign _zz_235_ = ((decode_INSTRUCTION & _zz_247_) == (32'b00000000000000000001000000000000)); assign _zz_236_ = (32'b00000000000000000111000001010100); assign _zz_237_ = ((decode_INSTRUCTION & _zz_248_) == (32'b01000000000000000001000000010000)); assign _zz_238_ = ((decode_INSTRUCTION & _zz_249_) == (32'b00000000000000000001000000010000)); assign _zz_239_ = _zz_92_; assign _zz_240_ = {_zz_250_,{_zz_251_,_zz_252_}}; assign _zz_241_ = {_zz_253_,_zz_254_}; assign _zz_242_ = (2'b00); assign _zz_243_ = (_zz_255_ != (1'b0)); assign _zz_244_ = (_zz_256_ != _zz_257_); assign _zz_245_ = {_zz_258_,{_zz_259_,_zz_260_}}; assign _zz_246_ = (32'b00000000000000000110000000000100); assign _zz_247_ = (32'b00000000000000000101000000000100); assign _zz_248_ = (32'b01000000000000000011000001010100); assign _zz_249_ = (32'b00000000000000000111000001010100); assign _zz_250_ = ((decode_INSTRUCTION & _zz_261_) == (32'b00000000000000000001000000010000)); assign _zz_251_ = (_zz_262_ == _zz_263_); assign _zz_252_ = {_zz_91_,{_zz_264_,_zz_265_}}; assign _zz_253_ = ((decode_INSTRUCTION & _zz_266_) == (32'b00000000000000000001000001010000)); assign _zz_254_ = ((decode_INSTRUCTION & _zz_267_) == (32'b00000000000000000010000001010000)); assign _zz_255_ = ((decode_INSTRUCTION & _zz_268_) == (32'b00000000000000000001000000001000)); assign _zz_256_ = (_zz_269_ == _zz_270_); assign _zz_257_ = (1'b0); assign _zz_258_ = ({_zz_271_,_zz_272_} != (2'b00)); assign _zz_259_ = (_zz_273_ != _zz_274_); assign _zz_260_ = {_zz_275_,{_zz_276_,_zz_277_}}; assign _zz_261_ = (32'b00000000000000000001000000010000); assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); assign _zz_263_ = (32'b00000000000000000010000000010000); assign _zz_264_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000000000000000100)); assign _zz_265_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000000000000000000)); assign _zz_266_ = (32'b00000000000000000001000001010000); assign _zz_267_ = (32'b00000000000000000010000001010000); assign _zz_268_ = (32'b00000000000000000001000001001000); assign _zz_269_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); assign _zz_270_ = (32'b00000000000000000000000001010000); assign _zz_271_ = ((decode_INSTRUCTION & _zz_280_) == (32'b00000000000100000000000001010000)); assign _zz_272_ = ((decode_INSTRUCTION & _zz_281_) == (32'b00010000000000000000000001010000)); assign _zz_273_ = ((decode_INSTRUCTION & _zz_282_) == (32'b00000000000000000001000000000000)); assign _zz_274_ = (1'b0); assign _zz_275_ = ((_zz_283_ == _zz_284_) != (1'b0)); assign _zz_276_ = ({_zz_285_,_zz_286_} != (2'b00)); assign _zz_277_ = {(_zz_287_ != _zz_288_),{_zz_289_,{_zz_290_,_zz_291_}}}; assign _zz_278_ = (32'b00000000000000000000000000001100); assign _zz_279_ = (32'b00000000000000000000000000101000); assign _zz_280_ = (32'b00010000000100000011000001010000); assign _zz_281_ = (32'b00010000010000000011000001010000); assign _zz_282_ = (32'b00000000000000000001000000000000); assign _zz_283_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); assign _zz_284_ = (32'b00000000000000000010000000000000); assign _zz_285_ = ((decode_INSTRUCTION & _zz_292_) == (32'b00000000000000000010000000000000)); assign _zz_286_ = ((decode_INSTRUCTION & _zz_293_) == (32'b00000000000000000001000000000000)); assign _zz_287_ = ((decode_INSTRUCTION & _zz_294_) == (32'b00000000000000000000000000000000)); assign _zz_288_ = (1'b0); assign _zz_289_ = ({_zz_295_,_zz_296_} != (2'b00)); assign _zz_290_ = (_zz_91_ != (1'b0)); assign _zz_291_ = {(_zz_297_ != _zz_298_),{_zz_299_,{_zz_300_,_zz_301_}}}; assign _zz_292_ = (32'b00000000000000000010000000010000); assign _zz_293_ = (32'b00000000000000000101000000000000); assign _zz_294_ = (32'b00000000000000000000000001011000); assign _zz_295_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)); assign _zz_296_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000)); assign _zz_297_ = {(_zz_302_ == _zz_303_),_zz_90_}; assign _zz_298_ = (2'b00); assign _zz_299_ = ({_zz_304_,_zz_90_} != (2'b00)); assign _zz_300_ = ({_zz_305_,_zz_306_} != (2'b00)); assign _zz_301_ = {(_zz_307_ != _zz_308_),{_zz_309_,{_zz_310_,_zz_311_}}}; assign _zz_302_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); assign _zz_303_ = (32'b00000000000000000000000000000100); assign _zz_304_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); assign _zz_305_ = ((decode_INSTRUCTION & _zz_312_) == (32'b00000000000000000000000000100100)); assign _zz_306_ = ((decode_INSTRUCTION & _zz_313_) == (32'b00000000000000000001000000010000)); assign _zz_307_ = {_zz_89_,(_zz_314_ == _zz_315_)}; assign _zz_308_ = (2'b00); assign _zz_309_ = ({_zz_89_,_zz_316_} != (2'b00)); assign _zz_310_ = (_zz_317_ != (1'b0)); assign _zz_311_ = {(_zz_318_ != _zz_319_),(_zz_320_ != _zz_321_)}; assign _zz_312_ = (32'b00000000000000000000000001100100); assign _zz_313_ = (32'b00000000000000000011000001010100); assign _zz_314_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); assign _zz_315_ = (32'b00000000000000000000000000100000); assign _zz_316_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); assign _zz_317_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); assign _zz_318_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000110000000010000)),((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000100000000010000))}; assign _zz_319_ = (2'b00); assign _zz_320_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); assign _zz_321_ = (1'b0); assign _zz_322_ = (32'b00000000000000000001000001111111); assign _zz_323_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); assign _zz_324_ = (32'b00000000000000000010000001110011); assign _zz_325_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); assign _zz_326_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); assign _zz_327_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_328_) == (32'b00000000000000000000000000000011)),{(_zz_329_ == _zz_330_),{_zz_331_,{_zz_332_,_zz_333_}}}}}}; assign _zz_328_ = (32'b00000000000000000101000001011111); assign _zz_329_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); assign _zz_330_ = (32'b00000000000000000000000001100011); assign _zz_331_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); assign _zz_332_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); assign _zz_333_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_334_) == (32'b00000000000000000101000000110011)),{(_zz_335_ == _zz_336_),{_zz_337_,{_zz_338_,_zz_339_}}}}}}; assign _zz_334_ = (32'b10111110000000000111000001111111); assign _zz_335_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); assign _zz_336_ = (32'b00000000000000000000000000110011); assign _zz_337_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); assign _zz_338_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); assign _zz_339_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); initial begin $readmemb("2-stage-2048-cache.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile); end always @ (posedge clk) begin if(_zz_40_) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end always @ (posedge clk) begin if(_zz_100_) begin _zz_149_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin if(_zz_100_) begin _zz_150_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; end end InstructionCache IBusCachedPlugin_cache ( .io_flush(_zz_131_), .io_cpu_prefetch_isValid(_zz_132_), .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), .io_cpu_fetch_isValid(_zz_133_), .io_cpu_fetch_isStuck(_zz_134_), .io_cpu_fetch_isRemoved(_zz_135_), .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), .io_cpu_fetch_dataBypass(_zz_136_), .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_137_), .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_138_), .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_139_), .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_140_), .io_cpu_fetch_mmuBus_rsp_exception(_zz_141_), .io_cpu_fetch_mmuBus_rsp_refilling(_zz_142_), .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), .io_cpu_fetch_mmuBus_busy(_zz_143_), .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), .io_cpu_fetch_isUser(_zz_144_), .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), .io_cpu_decode_isValid(_zz_145_), .io_cpu_decode_isStuck(_zz_146_), .io_cpu_decode_pc(_zz_147_), .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), .io_cpu_fill_valid(_zz_148_), .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), .io_mem_cmd_ready(iBus_cmd_ready), .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), .io_mem_rsp_valid(iBus_rsp_valid), .io_mem_rsp_payload_data(iBus_rsp_payload_data), .io_mem_rsp_payload_error(iBus_rsp_payload_error), .clk(clk), .reset(reset) ); always @(*) begin case(_zz_206_) 2'b00 : begin _zz_151_ = BranchPlugin_jumpInterface_payload; end 2'b01 : begin _zz_151_ = CsrPlugin_jumpInterface_payload; end default : begin _zz_151_ = IBusCachedPlugin_redoBranch_payload; end endcase end always @(*) begin case(_zz_125_) 2'b00 : begin _zz_152_ = DBusSimplePlugin_memoryExceptionPort_payload_code; _zz_153_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; end 2'b01 : begin _zz_152_ = BranchPlugin_branchExceptionPort_payload_code; _zz_153_ = BranchPlugin_branchExceptionPort_payload_badAddr; end default : begin _zz_152_ = CsrPlugin_selfException_payload_code; _zz_153_ = CsrPlugin_selfException_payload_badAddr; end endcase end `ifndef SYNTHESIS always @(*) begin case(decode_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_1_) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_1__string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_1__string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_1__string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_1__string = "SRA_1 "; default : _zz_1__string = "?????????"; endcase end always @(*) begin case(_zz_2_) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_2__string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_2__string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_2__string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_2__string = "SRA_1 "; default : _zz_2__string = "?????????"; endcase end always @(*) begin case(_zz_3_) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_3__string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_3__string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_3__string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_3__string = "SRA_1 "; default : _zz_3__string = "?????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(_zz_4_) `Src1CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : _zz_4__string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_4__string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : _zz_4__string = "URS1 "; default : _zz_4__string = "????????????"; endcase end always @(*) begin case(_zz_5_) `Src1CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : _zz_5__string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_5__string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : _zz_5__string = "URS1 "; default : _zz_5__string = "????????????"; endcase end always @(*) begin case(_zz_6_) `Src1CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : _zz_6__string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_6__string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : _zz_6__string = "URS1 "; default : _zz_6__string = "????????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_7_) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_7__string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_7__string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_7__string = "AND_1"; default : _zz_7__string = "?????"; endcase end always @(*) begin case(_zz_8_) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8__string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8__string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8__string = "AND_1"; default : _zz_8__string = "?????"; endcase end always @(*) begin case(_zz_9_) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_9__string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_9__string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_9__string = "AND_1"; default : _zz_9__string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(_zz_10_) `Src2CtrlEnum_defaultEncoding_RS : _zz_10__string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : _zz_10__string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : _zz_10__string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : _zz_10__string = "PC "; default : _zz_10__string = "???"; endcase end always @(*) begin case(_zz_11_) `Src2CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : _zz_11__string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : _zz_11__string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : _zz_11__string = "PC "; default : _zz_11__string = "???"; endcase end always @(*) begin case(_zz_12_) `Src2CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : _zz_12__string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : _zz_12__string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : _zz_12__string = "PC "; default : _zz_12__string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_13_) `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_13__string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_13__string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : _zz_13__string = "BITWISE "; default : _zz_13__string = "????????"; endcase end always @(*) begin case(_zz_14_) `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_14__string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_14__string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : _zz_14__string = "BITWISE "; default : _zz_14__string = "????????"; endcase end always @(*) begin case(_zz_15_) `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_15__string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_15__string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : _zz_15__string = "BITWISE "; default : _zz_15__string = "????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_16_) `BranchCtrlEnum_defaultEncoding_INC : _zz_16__string = "INC "; `BranchCtrlEnum_defaultEncoding_B : _zz_16__string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : _zz_16__string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : _zz_16__string = "JALR"; default : _zz_16__string = "????"; endcase end always @(*) begin case(_zz_17_) `BranchCtrlEnum_defaultEncoding_INC : _zz_17__string = "INC "; `BranchCtrlEnum_defaultEncoding_B : _zz_17__string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : _zz_17__string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : _zz_17__string = "JALR"; default : _zz_17__string = "????"; endcase end always @(*) begin case(_zz_18_) `BranchCtrlEnum_defaultEncoding_INC : _zz_18__string = "INC "; `BranchCtrlEnum_defaultEncoding_B : _zz_18__string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : _zz_18__string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : _zz_18__string = "JALR"; default : _zz_18__string = "????"; endcase end always @(*) begin case(decode_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; default : decode_ENV_CTRL_string = "??????"; endcase end always @(*) begin case(_zz_19_) `EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : _zz_19__string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_19__string = "EBREAK"; default : _zz_19__string = "??????"; endcase end always @(*) begin case(_zz_20_) `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : _zz_20__string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_20__string = "EBREAK"; default : _zz_20__string = "??????"; endcase end always @(*) begin case(_zz_21_) `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : _zz_21__string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_21__string = "EBREAK"; default : _zz_21__string = "??????"; endcase end always @(*) begin case(execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; default : execute_ENV_CTRL_string = "??????"; endcase end always @(*) begin case(_zz_24_) `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_24__string = "EBREAK"; default : _zz_24__string = "??????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_26_) `BranchCtrlEnum_defaultEncoding_INC : _zz_26__string = "INC "; `BranchCtrlEnum_defaultEncoding_B : _zz_26__string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : _zz_26__string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : _zz_26__string = "JALR"; default : _zz_26__string = "????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_28_) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_28__string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_28__string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_28__string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_28__string = "SRA_1 "; default : _zz_28__string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(_zz_32_) `Src2CtrlEnum_defaultEncoding_RS : _zz_32__string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : _zz_32__string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : _zz_32__string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : _zz_32__string = "PC "; default : _zz_32__string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(_zz_34_) `Src1CtrlEnum_defaultEncoding_RS : _zz_34__string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : _zz_34__string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34__string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34__string = "URS1 "; default : _zz_34__string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_37_) `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_37__string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_37__string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : _zz_37__string = "BITWISE "; default : _zz_37__string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_39_) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39__string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39__string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39__string = "AND_1"; default : _zz_39__string = "?????"; endcase end always @(*) begin case(_zz_44_) `BranchCtrlEnum_defaultEncoding_INC : _zz_44__string = "INC "; `BranchCtrlEnum_defaultEncoding_B : _zz_44__string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : _zz_44__string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : _zz_44__string = "JALR"; default : _zz_44__string = "????"; endcase end always @(*) begin case(_zz_45_) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45__string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45__string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45__string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45__string = "SRA_1 "; default : _zz_45__string = "?????????"; endcase end always @(*) begin case(_zz_49_) `EnvCtrlEnum_defaultEncoding_NONE : _zz_49__string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : _zz_49__string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : _zz_49__string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_49__string = "EBREAK"; default : _zz_49__string = "??????"; endcase end always @(*) begin case(_zz_50_) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_50__string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_50__string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_50__string = "AND_1"; default : _zz_50__string = "?????"; endcase end always @(*) begin case(_zz_53_) `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; default : _zz_53__string = "????????????"; endcase end always @(*) begin case(_zz_55_) `Src2CtrlEnum_defaultEncoding_RS : _zz_55__string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : _zz_55__string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : _zz_55__string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : _zz_55__string = "PC "; default : _zz_55__string = "???"; endcase end always @(*) begin case(_zz_57_) `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_57__string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_57__string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : _zz_57__string = "BITWISE "; default : _zz_57__string = "????????"; endcase end always @(*) begin case(_zz_93_) `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_93__string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_93__string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : _zz_93__string = "BITWISE "; default : _zz_93__string = "????????"; endcase end always @(*) begin case(_zz_94_) `Src2CtrlEnum_defaultEncoding_RS : _zz_94__string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : _zz_94__string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : _zz_94__string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : _zz_94__string = "PC "; default : _zz_94__string = "???"; endcase end always @(*) begin case(_zz_95_) `Src1CtrlEnum_defaultEncoding_RS : _zz_95__string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : _zz_95__string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_95__string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : _zz_95__string = "URS1 "; default : _zz_95__string = "????????????"; endcase end always @(*) begin case(_zz_96_) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_96__string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_96__string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_96__string = "AND_1"; default : _zz_96__string = "?????"; endcase end always @(*) begin case(_zz_97_) `EnvCtrlEnum_defaultEncoding_NONE : _zz_97__string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : _zz_97__string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97__string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_97__string = "EBREAK"; default : _zz_97__string = "??????"; endcase end always @(*) begin case(_zz_98_) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_98__string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_98__string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_98__string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_98__string = "SRA_1 "; default : _zz_98__string = "?????????"; endcase end always @(*) begin case(_zz_99_) `BranchCtrlEnum_defaultEncoding_INC : _zz_99__string = "INC "; `BranchCtrlEnum_defaultEncoding_B : _zz_99__string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : _zz_99__string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : _zz_99__string = "JALR"; default : _zz_99__string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; default : decode_to_execute_ENV_CTRL_string = "??????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end `endif assign decode_IS_CSR = _zz_47_; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = _zz_67_; assign decode_SHIFT_CTRL = _zz_1_; assign _zz_2_ = _zz_3_; assign decode_SRC1_CTRL = _zz_4_; assign _zz_5_ = _zz_6_; assign decode_ALU_BITWISE_CTRL = _zz_7_; assign _zz_8_ = _zz_9_; assign decode_CSR_WRITE_OPCODE = _zz_23_; assign decode_SRC2_CTRL = _zz_10_; assign _zz_11_ = _zz_12_; assign decode_ALU_CTRL = _zz_13_; assign _zz_14_ = _zz_15_; assign decode_MEMORY_STORE = _zz_56_; assign decode_BRANCH_CTRL = _zz_16_; assign _zz_17_ = _zz_18_; assign decode_ENV_CTRL = _zz_19_; assign _zz_20_ = _zz_21_; assign decode_SRC2_FORCE_ZERO = _zz_36_; assign decode_CSR_READ_OPCODE = _zz_22_; assign decode_SRC_LESS_UNSIGNED = _zz_51_; assign decode_MEMORY_ENABLE = _zz_52_; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; assign execute_ENV_CTRL = _zz_24_; assign execute_BRANCH_CALC = _zz_25_; assign execute_BRANCH_DO = _zz_27_; assign execute_RS1 = _zz_42_; assign execute_BRANCH_CTRL = _zz_26_; assign execute_SHIFT_CTRL = _zz_28_; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; assign execute_SRC2_CTRL = _zz_32_; assign execute_SRC1_CTRL = _zz_34_; assign decode_SRC_USE_SUB_LESS = _zz_43_; assign decode_SRC_ADD_ZERO = _zz_54_; assign execute_SRC_ADD_SUB = _zz_31_; assign execute_SRC_LESS = _zz_29_; assign execute_ALU_CTRL = _zz_37_; assign execute_SRC2 = _zz_33_; assign execute_SRC1 = _zz_35_; assign execute_ALU_BITWISE_CTRL = _zz_39_; always @ (*) begin _zz_40_ = 1'b0; if(lastStageRegFileWrite_valid)begin _zz_40_ = 1'b1; end end always @ (*) begin decode_REGFILE_WRITE_VALID = _zz_46_; if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin decode_REGFILE_WRITE_VALID = 1'b0; end end assign decode_LEGAL_INSTRUCTION = _zz_58_; assign decode_INSTRUCTION_READY = 1'b1; assign decode_INSTRUCTION = _zz_68_; always @ (*) begin _zz_59_ = execute_REGFILE_WRITE_DATA; execute_arbitration_haltItself = 1'b0; if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_81_)))begin execute_arbitration_haltItself = 1'b1; end if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && ((! dBus_rsp_ready) || (! _zz_81_))))begin execute_arbitration_haltItself = 1'b1; end if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin _zz_59_ = execute_DBusSimplePlugin_rspFormated; end if(_zz_154_)begin _zz_59_ = _zz_108_; if(_zz_155_)begin if(! execute_LightShifterPlugin_done) begin execute_arbitration_haltItself = 1'b1; end end end if((execute_arbitration_isValid && execute_IS_CSR))begin _zz_59_ = execute_CsrPlugin_readData; if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end end assign execute_MEMORY_ADDRESS_LOW = _zz_61_; assign execute_MEMORY_READ_DATA = _zz_60_; assign execute_REGFILE_WRITE_DATA = _zz_38_; assign execute_SRC_ADD = _zz_30_; assign execute_RS2 = _zz_41_; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = _zz_62_; assign decode_FLUSH_ALL = _zz_48_; always @ (*) begin IBusCachedPlugin_rsp_issueDetected = _zz_63_; _zz_64_ = _zz_65_; IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); if(((_zz_133_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_65_)))begin _zz_64_ = 1'b1; IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); end if(((_zz_133_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_63_)))begin IBusCachedPlugin_rsp_issueDetected = 1'b1; IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); end if(IBusCachedPlugin_fetcherHalt)begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; end end always @ (*) begin _zz_63_ = _zz_64_; _zz_65_ = 1'b0; IBusCachedPlugin_rsp_redoFetch = 1'b0; _zz_148_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); if(((_zz_133_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)))begin _zz_65_ = 1'b1; IBusCachedPlugin_rsp_redoFetch = 1'b1; end if(((_zz_133_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_64_)))begin _zz_63_ = 1'b1; _zz_148_ = 1'b1; IBusCachedPlugin_rsp_redoFetch = 1'b1; end if((! IBusCachedPlugin_iBusRsp_readyForError))begin IBusCachedPlugin_rsp_redoFetch = 1'b0; end if((! IBusCachedPlugin_iBusRsp_readyForError))begin _zz_148_ = 1'b0; end end always @ (*) begin _zz_66_ = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_redoBranch_valid)begin _zz_66_ = IBusCachedPlugin_redoBranch_payload; end end assign decode_PC = _zz_69_; assign execute_PC = decode_to_execute_PC; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign decode_arbitration_haltItself = 1'b0; always @ (*) begin decode_arbitration_haltByOther = 1'b0; if(CsrPlugin_interrupt)begin decode_arbitration_haltByOther = decode_arbitration_isValid; end if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; if(_zz_156_)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin decode_arbitration_removeIt = 1'b1; end end always @ (*) begin decode_arbitration_flushAll = 1'b0; execute_arbitration_removeIt = 1'b0; IBusCachedPlugin_fetcherHalt = 1'b0; CsrPlugin_jumpInterface_valid = 1'b0; CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); if(BranchPlugin_jumpInterface_valid)begin decode_arbitration_flushAll = 1'b1; end CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; if(_zz_157_)begin decode_arbitration_flushAll = 1'b1; execute_arbitration_removeIt = 1'b1; CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin IBusCachedPlugin_fetcherHalt = 1'b1; end if(_zz_158_)begin IBusCachedPlugin_fetcherHalt = 1'b1; CsrPlugin_jumpInterface_valid = 1'b1; CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; decode_arbitration_flushAll = 1'b1; end if(_zz_159_)begin IBusCachedPlugin_fetcherHalt = 1'b1; CsrPlugin_jumpInterface_valid = 1'b1; decode_arbitration_flushAll = 1'b1; case(_zz_160_) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end default : begin end endcase end if(execute_arbitration_isFlushed)begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_haltByOther = 1'b0; assign execute_arbitration_flushAll = 1'b0; assign lastStageInstruction = execute_INSTRUCTION; assign lastStagePc = execute_PC; assign lastStageIsValid = execute_arbitration_isValid; assign lastStageIsFiring = execute_arbitration_isFiring; assign IBusCachedPlugin_fetcherflushIt = 1'b0; always @ (*) begin IBusCachedPlugin_incomingInstruction = 1'b0; if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin IBusCachedPlugin_incomingInstruction = 1'b1; end end assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_redoBranch_valid}} != (3'b000)); assign _zz_70_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid}}; assign _zz_71_ = (_zz_70_ & (~ _zz_166_)); assign _zz_72_ = _zz_71_[1]; assign _zz_73_ = _zz_71_[2]; assign IBusCachedPlugin_jump_pcLoad_payload = _zz_151_; assign _zz_74_ = (! IBusCachedPlugin_fetcherHalt); assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_74_); assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_74_); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; always @ (*) begin IBusCachedPlugin_fetchPc_propagatePc = 1'b0; if((IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))begin IBusCachedPlugin_fetchPc_propagatePc = 1'b1; end end always @ (*) begin IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_168_); IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; if(IBusCachedPlugin_fetchPc_propagatePc)begin IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end if(_zz_161_)begin IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_75_; assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end assign _zz_76_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_76_); assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_76_); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; end if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; end end assign _zz_77_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_77_); assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_77_); assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_78_; assign _zz_78_ = ((1'b0 && (! _zz_79_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); assign _zz_79_ = _zz_80_; assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_79_; assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); assign _zz_69_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; assign _zz_68_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; assign _zz_67_ = (decode_PC + (32'b00000000000000000000000000000100)); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; assign _zz_132_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); assign _zz_135_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); assign _zz_136_ = (32'b00000000000000000000000000000000); assign _zz_133_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); assign _zz_134_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); assign _zz_144_ = (CsrPlugin_privilege == (2'b00)); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; assign _zz_140_ = 1'b1; assign _zz_138_ = 1'b1; assign _zz_139_ = 1'b1; assign _zz_137_ = 1'b0; assign _zz_141_ = 1'b0; assign _zz_142_ = 1'b0; assign _zz_143_ = 1'b0; assign _zz_131_ = (decode_arbitration_isValid && decode_FLUSH_ALL); assign _zz_62_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_81_)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin _zz_82_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin _zz_82_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin _zz_82_ = execute_RS2[31 : 0]; end endcase end assign dBus_cmd_payload_data = _zz_82_; assign _zz_61_ = dBus_cmd_payload_address[1 : 0]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin _zz_83_ = (4'b0001); end 2'b01 : begin _zz_83_ = (4'b0011); end default : begin _zz_83_ = (4'b1111); end endcase end assign execute_DBusSimplePlugin_formalMask = (_zz_83_ <<< dBus_cmd_payload_address[1 : 0]); assign dBus_cmd_payload_address = execute_SRC_ADD; assign _zz_60_ = dBus_rsp_data; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); if(execute_ALIGNEMENT_FAULT)begin DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_169_}; DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))))begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; always @ (*) begin execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; case(execute_MEMORY_ADDRESS_LOW) 2'b01 : begin execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; end 2'b10 : begin execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; end 2'b11 : begin execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; end default : begin end endcase end assign _zz_84_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); always @ (*) begin _zz_85_[31] = _zz_84_; _zz_85_[30] = _zz_84_; _zz_85_[29] = _zz_84_; _zz_85_[28] = _zz_84_; _zz_85_[27] = _zz_84_; _zz_85_[26] = _zz_84_; _zz_85_[25] = _zz_84_; _zz_85_[24] = _zz_84_; _zz_85_[23] = _zz_84_; _zz_85_[22] = _zz_84_; _zz_85_[21] = _zz_84_; _zz_85_[20] = _zz_84_; _zz_85_[19] = _zz_84_; _zz_85_[18] = _zz_84_; _zz_85_[17] = _zz_84_; _zz_85_[16] = _zz_84_; _zz_85_[15] = _zz_84_; _zz_85_[14] = _zz_84_; _zz_85_[13] = _zz_84_; _zz_85_[12] = _zz_84_; _zz_85_[11] = _zz_84_; _zz_85_[10] = _zz_84_; _zz_85_[9] = _zz_84_; _zz_85_[8] = _zz_84_; _zz_85_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; end assign _zz_86_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); always @ (*) begin _zz_87_[31] = _zz_86_; _zz_87_[30] = _zz_86_; _zz_87_[29] = _zz_86_; _zz_87_[28] = _zz_86_; _zz_87_[27] = _zz_86_; _zz_87_[26] = _zz_86_; _zz_87_[25] = _zz_86_; _zz_87_[24] = _zz_86_; _zz_87_[23] = _zz_86_; _zz_87_[22] = _zz_86_; _zz_87_[21] = _zz_86_; _zz_87_[20] = _zz_86_; _zz_87_[19] = _zz_86_; _zz_87_[18] = _zz_86_; _zz_87_[17] = _zz_86_; _zz_87_[16] = _zz_86_; _zz_87_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; end always @ (*) begin case(_zz_164_) 2'b00 : begin execute_DBusSimplePlugin_rspFormated = _zz_85_; end 2'b01 : begin execute_DBusSimplePlugin_rspFormated = _zz_87_; end default : begin execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; end endcase end assign _zz_89_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); assign _zz_90_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); assign _zz_91_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); assign _zz_92_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); assign _zz_88_ = {({(_zz_207_ == _zz_208_),{_zz_209_,_zz_210_}} != (3'b000)),{((_zz_211_ == _zz_212_) != (1'b0)),{({_zz_213_,_zz_214_} != (2'b00)),{(_zz_215_ != _zz_216_),{_zz_217_,{_zz_218_,_zz_219_}}}}}}; assign _zz_58_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_322_) == (32'b00000000000000000001000001110011)),{(_zz_323_ == _zz_324_),{_zz_325_,{_zz_326_,_zz_327_}}}}}}} != (20'b00000000000000000000)); assign _zz_93_ = _zz_88_[1 : 0]; assign _zz_57_ = _zz_93_; assign _zz_56_ = _zz_170_[0]; assign _zz_94_ = _zz_88_[4 : 3]; assign _zz_55_ = _zz_94_; assign _zz_54_ = _zz_171_[0]; assign _zz_95_ = _zz_88_[7 : 6]; assign _zz_53_ = _zz_95_; assign _zz_52_ = _zz_172_[0]; assign _zz_51_ = _zz_173_[0]; assign _zz_96_ = _zz_88_[13 : 12]; assign _zz_50_ = _zz_96_; assign _zz_97_ = _zz_88_[15 : 14]; assign _zz_49_ = _zz_97_; assign _zz_48_ = _zz_174_[0]; assign _zz_47_ = _zz_175_[0]; assign _zz_46_ = _zz_176_[0]; assign _zz_98_ = _zz_88_[20 : 19]; assign _zz_45_ = _zz_98_; assign _zz_99_ = _zz_88_[24 : 23]; assign _zz_44_ = _zz_99_; assign _zz_43_ = _zz_177_[0]; assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = (4'b0010); assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; assign _zz_100_ = (! execute_arbitration_isStuck); assign execute_RegFilePlugin_rs1Data = _zz_149_; assign execute_RegFilePlugin_rs2Data = _zz_150_; assign _zz_42_ = execute_RegFilePlugin_rs1Data; assign _zz_41_ = execute_RegFilePlugin_rs2Data; assign lastStageRegFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); assign lastStageRegFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; assign lastStageRegFileWrite_payload_data = _zz_59_; always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); end endcase end always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin _zz_101_ = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin _zz_101_ = {31'd0, _zz_178_}; end default : begin _zz_101_ = execute_SRC_ADD_SUB; end endcase end assign _zz_38_ = _zz_101_; assign _zz_36_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin _zz_102_ = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin _zz_102_ = {29'd0, _zz_179_}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_102_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; end default : begin _zz_102_ = {27'd0, _zz_180_}; end endcase end assign _zz_35_ = _zz_102_; assign _zz_103_ = _zz_181_[11]; always @ (*) begin _zz_104_[19] = _zz_103_; _zz_104_[18] = _zz_103_; _zz_104_[17] = _zz_103_; _zz_104_[16] = _zz_103_; _zz_104_[15] = _zz_103_; _zz_104_[14] = _zz_103_; _zz_104_[13] = _zz_103_; _zz_104_[12] = _zz_103_; _zz_104_[11] = _zz_103_; _zz_104_[10] = _zz_103_; _zz_104_[9] = _zz_103_; _zz_104_[8] = _zz_103_; _zz_104_[7] = _zz_103_; _zz_104_[6] = _zz_103_; _zz_104_[5] = _zz_103_; _zz_104_[4] = _zz_103_; _zz_104_[3] = _zz_103_; _zz_104_[2] = _zz_103_; _zz_104_[1] = _zz_103_; _zz_104_[0] = _zz_103_; end assign _zz_105_ = _zz_182_[11]; always @ (*) begin _zz_106_[19] = _zz_105_; _zz_106_[18] = _zz_105_; _zz_106_[17] = _zz_105_; _zz_106_[16] = _zz_105_; _zz_106_[15] = _zz_105_; _zz_106_[14] = _zz_105_; _zz_106_[13] = _zz_105_; _zz_106_[12] = _zz_105_; _zz_106_[11] = _zz_105_; _zz_106_[10] = _zz_105_; _zz_106_[9] = _zz_105_; _zz_106_[8] = _zz_105_; _zz_106_[7] = _zz_105_; _zz_106_[6] = _zz_105_; _zz_106_[5] = _zz_105_; _zz_106_[4] = _zz_105_; _zz_106_[3] = _zz_105_; _zz_106_[2] = _zz_105_; _zz_106_[1] = _zz_105_; _zz_106_[0] = _zz_105_; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin _zz_107_ = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin _zz_107_ = {_zz_104_,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin _zz_107_ = {_zz_106_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin _zz_107_ = execute_PC; end endcase end assign _zz_33_ = _zz_107_; always @ (*) begin execute_SrcPlugin_addSub = _zz_183_; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign _zz_31_ = execute_SrcPlugin_addSub; assign _zz_30_ = execute_SrcPlugin_addSub; assign _zz_29_ = execute_SrcPlugin_less; assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin _zz_108_ = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin _zz_108_ = _zz_190_; end endcase end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); assign _zz_109_ = execute_INSTRUCTION[14 : 12]; always @ (*) begin if((_zz_109_ == (3'b000))) begin _zz_110_ = execute_BranchPlugin_eq; end else if((_zz_109_ == (3'b001))) begin _zz_110_ = (! execute_BranchPlugin_eq); end else if((((_zz_109_ & (3'b101)) == (3'b101)))) begin _zz_110_ = (! execute_SRC_LESS); end else begin _zz_110_ = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin _zz_111_ = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin _zz_111_ = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin _zz_111_ = 1'b1; end default : begin _zz_111_ = _zz_110_; end endcase end assign _zz_27_ = _zz_111_; assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); assign _zz_112_ = _zz_192_[19]; always @ (*) begin _zz_113_[10] = _zz_112_; _zz_113_[9] = _zz_112_; _zz_113_[8] = _zz_112_; _zz_113_[7] = _zz_112_; _zz_113_[6] = _zz_112_; _zz_113_[5] = _zz_112_; _zz_113_[4] = _zz_112_; _zz_113_[3] = _zz_112_; _zz_113_[2] = _zz_112_; _zz_113_[1] = _zz_112_; _zz_113_[0] = _zz_112_; end assign _zz_114_ = _zz_193_[11]; always @ (*) begin _zz_115_[19] = _zz_114_; _zz_115_[18] = _zz_114_; _zz_115_[17] = _zz_114_; _zz_115_[16] = _zz_114_; _zz_115_[15] = _zz_114_; _zz_115_[14] = _zz_114_; _zz_115_[13] = _zz_114_; _zz_115_[12] = _zz_114_; _zz_115_[11] = _zz_114_; _zz_115_[10] = _zz_114_; _zz_115_[9] = _zz_114_; _zz_115_[8] = _zz_114_; _zz_115_[7] = _zz_114_; _zz_115_[6] = _zz_114_; _zz_115_[5] = _zz_114_; _zz_115_[4] = _zz_114_; _zz_115_[3] = _zz_114_; _zz_115_[2] = _zz_114_; _zz_115_[1] = _zz_114_; _zz_115_[0] = _zz_114_; end assign _zz_116_ = _zz_194_[11]; always @ (*) begin _zz_117_[18] = _zz_116_; _zz_117_[17] = _zz_116_; _zz_117_[16] = _zz_116_; _zz_117_[15] = _zz_116_; _zz_117_[14] = _zz_116_; _zz_117_[13] = _zz_116_; _zz_117_[12] = _zz_116_; _zz_117_[11] = _zz_116_; _zz_117_[10] = _zz_116_; _zz_117_[9] = _zz_116_; _zz_117_[8] = _zz_116_; _zz_117_[7] = _zz_116_; _zz_117_[6] = _zz_116_; _zz_117_[5] = _zz_116_; _zz_117_[4] = _zz_116_; _zz_117_[3] = _zz_116_; _zz_117_[2] = _zz_116_; _zz_117_[1] = _zz_116_; _zz_117_[0] = _zz_116_; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin _zz_118_ = {{_zz_113_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin _zz_118_ = {_zz_115_,execute_INSTRUCTION[31 : 20]}; end default : begin _zz_118_ = {{_zz_117_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end assign execute_BranchPlugin_branch_src2 = _zz_118_; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign _zz_25_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; always @ (*) begin BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); if(1'b0)begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; always @ (*) begin CsrPlugin_privilege = (2'b11); if(CsrPlugin_forceMachineWire)begin CsrPlugin_privilege = (2'b11); end end assign CsrPlugin_misa_base = (2'b01); assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_119_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; assign _zz_120_ = _zz_195_[0]; assign _zz_121_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; assign _zz_122_ = (_zz_121_ & (~ _zz_197_)); assign _zz_123_ = _zz_122_[1]; assign _zz_124_ = _zz_122_[2]; assign _zz_125_ = {_zz_124_,_zz_123_}; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; if(_zz_156_)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; always @ (*) begin CsrPlugin_interrupt = 1'b0; CsrPlugin_interruptCode = (4'bxxxx); CsrPlugin_interruptTargetPrivilege = (2'bxx); if((CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))))begin if((((CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE) && 1'b1) && (! 1'b0)))begin CsrPlugin_interrupt = 1'b1; CsrPlugin_interruptCode = (4'b0111); CsrPlugin_interruptTargetPrivilege = (2'b11); end if((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) && 1'b1) && (! 1'b0)))begin CsrPlugin_interrupt = 1'b1; CsrPlugin_interruptCode = (4'b0011); CsrPlugin_interruptTargetPrivilege = (2'b11); end if((((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) && 1'b1) && (! 1'b0)))begin CsrPlugin_interrupt = 1'b1; CsrPlugin_interruptCode = (4'b1011); CsrPlugin_interruptTargetPrivilege = (2'b11); end end if((! CsrPlugin_allowInterrupts))begin CsrPlugin_interrupt = 1'b0; end end assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; always @ (*) begin CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1); if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin CsrPlugin_pipelineLiberator_done = 1'b0; end end assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); always @ (*) begin CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; if(CsrPlugin_hadException)begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end always @ (*) begin CsrPlugin_trapCause = CsrPlugin_interruptCode; if(CsrPlugin_hadException)begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end always @ (*) begin CsrPlugin_xtvec_mode = (2'bxx); CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; end default : begin end endcase end assign contextSwitching = CsrPlugin_jumpInterface_valid; assign _zz_23_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); assign _zz_22_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); assign execute_CsrPlugin_inWfi = 1'b0; assign execute_CsrPlugin_blockedBySideEffects = 1'b0; always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); case(execute_CsrPlugin_csrAddress) 12'b101111000000 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[31 : 0] = _zz_126_; end 12'b001100000000 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; end 12'b001101000001 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; end 12'b001100000101 : begin if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end end 12'b001101000100 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; end 12'b001101000011 : begin if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; end 12'b111111000000 : begin if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end execute_CsrPlugin_readData[31 : 0] = _zz_127_; end 12'b001101000000 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; end 12'b001100000100 : begin execute_CsrPlugin_illegalAccess = 1'b0; execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; end 12'b001101000010 : begin if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; end default : begin end endcase if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin execute_CsrPlugin_illegalAccess = 1'b0; end end always @ (*) begin execute_CsrPlugin_illegalInstruction = 1'b0; if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end always @ (*) begin CsrPlugin_selfException_valid = 1'b0; CsrPlugin_selfException_payload_code = (4'bxxxx); if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin CsrPlugin_selfException_valid = 1'b1; case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = (4'b1000); end default : begin CsrPlugin_selfException_payload_code = (4'b1011); end endcase end if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin CsrPlugin_selfException_valid = 1'b1; CsrPlugin_selfException_payload_code = (4'b0011); end end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin case(_zz_165_) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end default : begin execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign _zz_127_ = (_zz_126_ & externalInterruptArray_regNext); assign externalInterrupt = (_zz_127_ != (32'b00000000000000000000000000000000)); assign _zz_21_ = decode_ENV_CTRL; assign _zz_19_ = _zz_49_; assign _zz_24_ = decode_to_execute_ENV_CTRL; assign _zz_18_ = decode_BRANCH_CTRL; assign _zz_16_ = _zz_44_; assign _zz_26_ = decode_to_execute_BRANCH_CTRL; assign _zz_15_ = decode_ALU_CTRL; assign _zz_13_ = _zz_57_; assign _zz_37_ = decode_to_execute_ALU_CTRL; assign _zz_12_ = decode_SRC2_CTRL; assign _zz_10_ = _zz_55_; assign _zz_32_ = decode_to_execute_SRC2_CTRL; assign _zz_9_ = decode_ALU_BITWISE_CTRL; assign _zz_7_ = _zz_50_; assign _zz_39_ = decode_to_execute_ALU_BITWISE_CTRL; assign _zz_6_ = decode_SRC1_CTRL; assign _zz_4_ = _zz_53_; assign _zz_34_ = decode_to_execute_SRC1_CTRL; assign _zz_3_ = decode_SHIFT_CTRL; assign _zz_1_ = _zz_45_; assign _zz_28_ = decode_to_execute_SHIFT_CTRL; assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00)); assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); assign iBusWishbone_ADR = {_zz_204_,_zz_128_}; assign iBusWishbone_CTI = ((_zz_128_ == (3'b111)) ? (3'b111) : (3'b010)); assign iBusWishbone_BTE = (2'b00); assign iBusWishbone_SEL = (4'b1111); assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); always @ (*) begin iBusWishbone_CYC = 1'b0; iBusWishbone_STB = 1'b0; if(_zz_162_)begin iBusWishbone_CYC = 1'b1; iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); assign iBus_rsp_valid = _zz_129_; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); assign dBusWishbone_CTI = (3'b000); assign dBusWishbone_BTE = (2'b00); always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin _zz_130_ = (4'b0001); end 2'b01 : begin _zz_130_ = (4'b0011); end default : begin _zz_130_ = (4'b1111); end endcase end always @ (*) begin dBusWishbone_SEL = _zz_205_[3:0]; if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = (4'b1111); end end assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_inc <= 1'b0; _zz_75_ <= 1'b0; _zz_80_ <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_decodeRemoved <= 1'b0; _zz_81_ <= 1'b0; execute_LightShifterPlugin_isActive <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= (2'b11); CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; CsrPlugin_hadException <= 1'b0; _zz_126_ <= (32'b00000000000000000000000000000000); execute_arbitration_isValid <= 1'b0; _zz_128_ <= (3'b000); _zz_129_ <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin if(IBusCachedPlugin_fetchPc_propagatePc)begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if(_zz_161_)begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end if(IBusCachedPlugin_fetchPc_samplePcNext)begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end _zz_75_ <= 1'b1; if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin _zz_80_ <= 1'b0; end if(_zz_78_)begin _zz_80_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; end if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if(decode_arbitration_removeIt)begin IBusCachedPlugin_injector_decodeRemoved <= 1'b1; end if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin IBusCachedPlugin_injector_decodeRemoved <= 1'b0; end if((dBus_cmd_valid && dBus_cmd_ready))begin _zz_81_ <= 1'b1; end if((! execute_arbitration_isStuck))begin _zz_81_ <= 1'b0; end if(_zz_154_)begin if(_zz_155_)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; end end end if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end if((! execute_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; if(_zz_158_)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; end default : begin end endcase end if(_zz_159_)begin case(_zz_160_) 2'b11 : begin CsrPlugin_mstatus_MPP <= (2'b00); CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end default : begin end endcase end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin execute_arbitration_isValid <= decode_arbitration_isValid; end case(execute_CsrPlugin_csrAddress) 12'b101111000000 : begin if(execute_CsrPlugin_writeEnable)begin _zz_126_ <= execute_CsrPlugin_writeData[31 : 0]; end end 12'b001100000000 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; CsrPlugin_mstatus_MPIE <= _zz_198_[0]; CsrPlugin_mstatus_MIE <= _zz_199_[0]; end end 12'b001101000001 : begin end 12'b001100000101 : begin end 12'b001101000100 : begin end 12'b001101000011 : begin end 12'b111111000000 : begin end 12'b001101000000 : begin end 12'b001100000100 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mie_MEIE <= _zz_201_[0]; CsrPlugin_mie_MTIE <= _zz_202_[0]; CsrPlugin_mie_MSIE <= _zz_203_[0]; end end 12'b001101000010 : begin end default : begin end endcase if(_zz_162_)begin if(iBusWishbone_ACK)begin _zz_128_ <= (_zz_128_ + (3'b001)); end end _zz_129_ <= (iBusWishbone_CYC && iBusWishbone_ACK); if(_zz_163_)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; end end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end if((! execute_arbitration_isStuckByOthers))begin execute_LightShifterPlugin_shiftReg <= _zz_59_; end if(_zz_154_)begin if(_zz_155_)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); end end CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); if(execute_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); end if(_zz_156_)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_120_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_120_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(_zz_157_)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_152_; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_153_; end if(_zz_158_)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= execute_PC; if(CsrPlugin_hadException)begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end default : begin end endcase end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end if((! execute_arbitration_isStuck))begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end if((! execute_arbitration_isStuck))begin decode_to_execute_ENV_CTRL <= _zz_20_; end if((! execute_arbitration_isStuck))begin decode_to_execute_BRANCH_CTRL <= _zz_17_; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end if((! execute_arbitration_isStuck))begin decode_to_execute_ALU_CTRL <= _zz_14_; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC2_CTRL <= _zz_11_; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end if((! execute_arbitration_isStuck))begin decode_to_execute_ALU_BITWISE_CTRL <= _zz_8_; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC1_CTRL <= _zz_5_; end if((! execute_arbitration_isStuck))begin decode_to_execute_SHIFT_CTRL <= _zz_2_; end if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin decode_to_execute_PC <= decode_PC; end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= _zz_66_; end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_CSR <= decode_IS_CSR; end case(execute_CsrPlugin_csrAddress) 12'b101111000000 : begin end 12'b001100000000 : begin end 12'b001101000001 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end end 12'b001100000101 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end end 12'b001101000100 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mip_MSIP <= _zz_200_[0]; end end 12'b001101000011 : begin end 12'b111111000000 : begin end 12'b001101000000 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; end end 12'b001100000100 : begin end 12'b001101000010 : begin end default : begin end endcase iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; if(_zz_163_)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; end end endmodule