diff --git a/sw/include/fomu/csr.h b/sw/include/fomu/csr.h index d6be9e4..1e777fc 100644 --- a/sw/include/fomu/csr.h +++ b/sw/include/fomu/csr.h @@ -1,902 +1,784 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (bc90344) & LiteX (3a72688b) on 2019-05-22 22:55:33 +//-------------------------------------------------------------------------------- #ifndef __GENERATED_CSR_H #define __GENERATED_CSR_H #include #ifdef CSR_ACCESSORS_DEFINED -extern void csr_writeb(uint8_t value, uint32_t addr); -extern uint8_t csr_readb(uint32_t addr); -extern void csr_writew(uint16_t value, uint32_t addr); -extern uint16_t csr_readw(uint32_t addr); -extern void csr_writel(uint32_t value, uint32_t addr); -extern uint32_t csr_readl(uint32_t addr); +extern void csr_writeb(uint8_t value, unsigned long addr); +extern uint8_t csr_readb(unsigned long addr); +extern void csr_writew(uint16_t value, unsigned long addr); +extern uint16_t csr_readw(unsigned long addr); +extern void csr_writel(uint32_t value, unsigned long addr); +extern uint32_t csr_readl(unsigned long addr); #else /* ! CSR_ACCESSORS_DEFINED */ -static inline void csr_writeb(uint8_t value, uint32_t addr) -{ - *((volatile uint8_t *)addr) = value; -} - -static inline uint8_t csr_readb(uint32_t addr) -{ - return *(volatile uint8_t *)addr; -} - -static inline void csr_writew(uint16_t value, uint32_t addr) -{ - *((volatile uint16_t *)addr) = value; -} - -static inline uint16_t csr_readw(uint32_t addr) -{ - return *(volatile uint16_t *)addr; -} - -static inline void csr_writel(uint32_t value, uint32_t addr) -{ - *((volatile uint32_t *)addr) = value; -} - -static inline uint32_t csr_readl(uint32_t addr) -{ - return *(volatile uint32_t *)addr; -} +#include #endif /* ! CSR_ACCESSORS_DEFINED */ /* ctrl */ -#define CSR_CTRL_BASE 0xe0000000 -#define CSR_CTRL_RESET_ADDR 0xe0000000 +#define CSR_CTRL_BASE 0xe0000000L +#define CSR_CTRL_RESET_ADDR 0xe0000000L #define CSR_CTRL_RESET_SIZE 1 - static inline unsigned char - ctrl_reset_read(void) -{ - unsigned char r = csr_readl(0xe0000000); +static inline unsigned char ctrl_reset_read(void) { + unsigned char r = csr_readl(0xe0000000L); return r; } -static inline void ctrl_reset_write(unsigned char value) -{ - csr_writel(value, 0xe0000000); +static inline void ctrl_reset_write(unsigned char value) { + csr_writel(value, 0xe0000000L); } -#define CSR_CTRL_SCRATCH_ADDR 0xe0000004 +#define CSR_CTRL_SCRATCH_ADDR 0xe0000004L #define CSR_CTRL_SCRATCH_SIZE 4 -static inline unsigned int ctrl_scratch_read(void) -{ - unsigned int r = csr_readl(0xe0000004); +static inline unsigned int ctrl_scratch_read(void) { + unsigned int r = csr_readl(0xe0000004L); r <<= 8; - r |= csr_readl(0xe0000008); + r |= csr_readl(0xe0000008L); r <<= 8; - r |= csr_readl(0xe000000c); + r |= csr_readl(0xe000000cL); r <<= 8; - r |= csr_readl(0xe0000010); + r |= csr_readl(0xe0000010L); return r; } -static inline void ctrl_scratch_write(unsigned int value) -{ - csr_writel(value >> 24, 0xe0000004); - csr_writel(value >> 16, 0xe0000008); - csr_writel(value >> 8, 0xe000000c); - csr_writel(value, 0xe0000010); +static inline void ctrl_scratch_write(unsigned int value) { + csr_writel(value >> 24, 0xe0000004L); + csr_writel(value >> 16, 0xe0000008L); + csr_writel(value >> 8, 0xe000000cL); + csr_writel(value, 0xe0000010L); } -#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014 +#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014L #define CSR_CTRL_BUS_ERRORS_SIZE 4 -static inline unsigned int ctrl_bus_errors_read(void) -{ - unsigned int r = csr_readl(0xe0000014); +static inline unsigned int ctrl_bus_errors_read(void) { + unsigned int r = csr_readl(0xe0000014L); r <<= 8; - r |= csr_readl(0xe0000018); + r |= csr_readl(0xe0000018L); r <<= 8; - r |= csr_readl(0xe000001c); + r |= csr_readl(0xe000001cL); r <<= 8; - r |= csr_readl(0xe0000020); + r |= csr_readl(0xe0000020L); return r; } /* picorvspi */ -#define CSR_PICORVSPI_BASE 0xe0005000 -#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000 +#define CSR_PICORVSPI_BASE 0xe0005000L +#define CSR_PICORVSPI_CFG1_ADDR 0xe0005000L #define CSR_PICORVSPI_CFG1_SIZE 1 -static inline unsigned char picorvspi_cfg1_read(void) -{ - unsigned char r = csr_readl(0xe0005000); +static inline unsigned char picorvspi_cfg1_read(void) { + unsigned char r = csr_readl(0xe0005000L); return r; } -static inline void picorvspi_cfg1_write(unsigned char value) -{ - csr_writel(value, 0xe0005000); +static inline void picorvspi_cfg1_write(unsigned char value) { + csr_writel(value, 0xe0005000L); } -#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004 +#define CSR_PICORVSPI_CFG2_ADDR 0xe0005004L #define CSR_PICORVSPI_CFG2_SIZE 1 -static inline unsigned char picorvspi_cfg2_read(void) -{ - unsigned char r = csr_readl(0xe0005004); +static inline unsigned char picorvspi_cfg2_read(void) { + unsigned char r = csr_readl(0xe0005004L); return r; } -static inline void picorvspi_cfg2_write(unsigned char value) -{ - csr_writel(value, 0xe0005004); +static inline void picorvspi_cfg2_write(unsigned char value) { + csr_writel(value, 0xe0005004L); } -#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008 +#define CSR_PICORVSPI_CFG3_ADDR 0xe0005008L #define CSR_PICORVSPI_CFG3_SIZE 1 -static inline unsigned char picorvspi_cfg3_read(void) -{ - unsigned char r = csr_readl(0xe0005008); +static inline unsigned char picorvspi_cfg3_read(void) { + unsigned char r = csr_readl(0xe0005008L); return r; } -static inline void picorvspi_cfg3_write(unsigned char value) -{ - csr_writel(value, 0xe0005008); +static inline void picorvspi_cfg3_write(unsigned char value) { + csr_writel(value, 0xe0005008L); } -#define CSR_PICORVSPI_CFG4_ADDR 0xe000500c +#define CSR_PICORVSPI_CFG4_ADDR 0xe000500cL #define CSR_PICORVSPI_CFG4_SIZE 1 -static inline unsigned char picorvspi_cfg4_read(void) -{ - unsigned char r = csr_readl(0xe000500c); +static inline unsigned char picorvspi_cfg4_read(void) { + unsigned char r = csr_readl(0xe000500cL); return r; } -static inline void picorvspi_cfg4_write(unsigned char value) -{ - csr_writel(value, 0xe000500c); +static inline void picorvspi_cfg4_write(unsigned char value) { + csr_writel(value, 0xe000500cL); } -#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010 +#define CSR_PICORVSPI_STAT1_ADDR 0xe0005010L #define CSR_PICORVSPI_STAT1_SIZE 1 -static inline unsigned char picorvspi_stat1_read(void) -{ - unsigned char r = csr_readl(0xe0005010); +static inline unsigned char picorvspi_stat1_read(void) { + unsigned char r = csr_readl(0xe0005010L); return r; } -#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014 +#define CSR_PICORVSPI_STAT2_ADDR 0xe0005014L #define CSR_PICORVSPI_STAT2_SIZE 1 -static inline unsigned char picorvspi_stat2_read(void) -{ - unsigned char r = csr_readl(0xe0005014); +static inline unsigned char picorvspi_stat2_read(void) { + unsigned char r = csr_readl(0xe0005014L); return r; } -#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018 +#define CSR_PICORVSPI_STAT3_ADDR 0xe0005018L #define CSR_PICORVSPI_STAT3_SIZE 1 -static inline unsigned char picorvspi_stat3_read(void) -{ - unsigned char r = csr_readl(0xe0005018); +static inline unsigned char picorvspi_stat3_read(void) { + unsigned char r = csr_readl(0xe0005018L); return r; } -#define CSR_PICORVSPI_STAT4_ADDR 0xe000501c +#define CSR_PICORVSPI_STAT4_ADDR 0xe000501cL #define CSR_PICORVSPI_STAT4_SIZE 1 -static inline unsigned char picorvspi_stat4_read(void) -{ - unsigned char r = csr_readl(0xe000501c); +static inline unsigned char picorvspi_stat4_read(void) { + unsigned char r = csr_readl(0xe000501cL); return r; } /* reboot */ -#define CSR_REBOOT_BASE 0xe0006000 -#define CSR_REBOOT_CTRL_ADDR 0xe0006000 +#define CSR_REBOOT_BASE 0xe0006000L +#define CSR_REBOOT_CTRL_ADDR 0xe0006000L #define CSR_REBOOT_CTRL_SIZE 1 -static inline unsigned char reboot_ctrl_read(void) -{ - unsigned char r = csr_readl(0xe0006000); +static inline unsigned char reboot_ctrl_read(void) { + unsigned char r = csr_readl(0xe0006000L); return r; } -static inline void reboot_ctrl_write(unsigned char value) -{ - csr_writel(value, 0xe0006000); +static inline void reboot_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0006000L); } -#define CSR_REBOOT_ADDR_ADDR 0xe0006004 +#define CSR_REBOOT_ADDR_ADDR 0xe0006004L #define CSR_REBOOT_ADDR_SIZE 4 -static inline unsigned int reboot_addr_read(void) -{ - unsigned int r = csr_readl(0xe0006004); +static inline unsigned int reboot_addr_read(void) { + unsigned int r = csr_readl(0xe0006004L); r <<= 8; - r |= csr_readl(0xe0006008); + r |= csr_readl(0xe0006008L); r <<= 8; - r |= csr_readl(0xe000600c); + r |= csr_readl(0xe000600cL); r <<= 8; - r |= csr_readl(0xe0006010); + r |= csr_readl(0xe0006010L); return r; } -static inline void reboot_addr_write(unsigned int value) -{ - csr_writel(value >> 24, 0xe0006004); - csr_writel(value >> 16, 0xe0006008); - csr_writel(value >> 8, 0xe000600c); - csr_writel(value, 0xe0006010); +static inline void reboot_addr_write(unsigned int value) { + csr_writel(value >> 24, 0xe0006004L); + csr_writel(value >> 16, 0xe0006008L); + csr_writel(value >> 8, 0xe000600cL); + csr_writel(value, 0xe0006010L); } /* rgb */ -#define CSR_RGB_BASE 0xe0006800 -#define CSR_RGB_DAT_ADDR 0xe0006800 +#define CSR_RGB_BASE 0xe0006800L +#define CSR_RGB_DAT_ADDR 0xe0006800L #define CSR_RGB_DAT_SIZE 1 -static inline unsigned char rgb_dat_read(void) -{ - unsigned char r = csr_readl(0xe0006800); +static inline unsigned char rgb_dat_read(void) { + unsigned char r = csr_readl(0xe0006800L); return r; } -static inline void rgb_dat_write(unsigned char value) -{ - csr_writel(value, 0xe0006800); +static inline void rgb_dat_write(unsigned char value) { + csr_writel(value, 0xe0006800L); } -#define CSR_RGB_ADDR_ADDR 0xe0006804 +#define CSR_RGB_ADDR_ADDR 0xe0006804L #define CSR_RGB_ADDR_SIZE 1 -static inline unsigned char rgb_addr_read(void) -{ - unsigned char r = csr_readl(0xe0006804); +static inline unsigned char rgb_addr_read(void) { + unsigned char r = csr_readl(0xe0006804L); return r; } -static inline void rgb_addr_write(unsigned char value) -{ - csr_writel(value, 0xe0006804); +static inline void rgb_addr_write(unsigned char value) { + csr_writel(value, 0xe0006804L); } -#define CSR_RGB_CTRL_ADDR 0xe0006808 +#define CSR_RGB_CTRL_ADDR 0xe0006808L #define CSR_RGB_CTRL_SIZE 1 -static inline unsigned char rgb_ctrl_read(void) -{ - unsigned char r = csr_readl(0xe0006808); +static inline unsigned char rgb_ctrl_read(void) { + unsigned char r = csr_readl(0xe0006808L); return r; } -static inline void rgb_ctrl_write(unsigned char value) -{ - csr_writel(value, 0xe0006808); +static inline void rgb_ctrl_write(unsigned char value) { + csr_writel(value, 0xe0006808L); +} +#define CSR_RGB_BYPASS_ADDR 0xe000680cL +#define CSR_RGB_BYPASS_SIZE 1 +static inline unsigned char rgb_bypass_read(void) { + unsigned char r = csr_readl(0xe000680cL); + return r; +} +static inline void rgb_bypass_write(unsigned char value) { + csr_writel(value, 0xe000680cL); +} +#define CSR_RGB_PWM_COUNT_ADDR 0xe0006810L +#define CSR_RGB_PWM_COUNT_SIZE 3 +static inline unsigned int rgb_pwm_count_read(void) { + unsigned int r = csr_readl(0xe0006810L); + r <<= 8; + r |= csr_readl(0xe0006814L); + r <<= 8; + r |= csr_readl(0xe0006818L); + return r; +} +static inline void rgb_pwm_count_write(unsigned int value) { + csr_writel(value >> 16, 0xe0006810L); + csr_writel(value >> 8, 0xe0006814L); + csr_writel(value, 0xe0006818L); +} +#define CSR_RGB_SENT_PULSES_ADDR 0xe000681cL +#define CSR_RGB_SENT_PULSES_SIZE 4 +static inline unsigned int rgb_sent_pulses_read(void) { + unsigned int r = csr_readl(0xe000681cL); + r <<= 8; + r |= csr_readl(0xe0006820L); + r <<= 8; + r |= csr_readl(0xe0006824L); + r <<= 8; + r |= csr_readl(0xe0006828L); + return r; +} +#define CSR_RGB_DETECTED_PULSES_ADDR 0xe000682cL +#define CSR_RGB_DETECTED_PULSES_SIZE 4 +static inline unsigned int rgb_detected_pulses_read(void) { + unsigned int r = csr_readl(0xe000682cL); + r <<= 8; + r |= csr_readl(0xe0006830L); + r <<= 8; + r |= csr_readl(0xe0006834L); + r <<= 8; + r |= csr_readl(0xe0006838L); + return r; } /* timer0 */ -#define CSR_TIMER0_BASE 0xe0002800 -#define CSR_TIMER0_LOAD_ADDR 0xe0002800 +#define CSR_TIMER0_BASE 0xe0002800L +#define CSR_TIMER0_LOAD_ADDR 0xe0002800L #define CSR_TIMER0_LOAD_SIZE 4 -static inline unsigned int timer0_load_read(void) -{ - unsigned int r = csr_readl(0xe0002800); +static inline unsigned int timer0_load_read(void) { + unsigned int r = csr_readl(0xe0002800L); r <<= 8; - r |= csr_readl(0xe0002804); + r |= csr_readl(0xe0002804L); r <<= 8; - r |= csr_readl(0xe0002808); + r |= csr_readl(0xe0002808L); r <<= 8; - r |= csr_readl(0xe000280c); + r |= csr_readl(0xe000280cL); return r; } -static inline void timer0_load_write(unsigned int value) -{ - csr_writel(value >> 24, 0xe0002800); - csr_writel(value >> 16, 0xe0002804); - csr_writel(value >> 8, 0xe0002808); - csr_writel(value, 0xe000280c); +static inline void timer0_load_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002800L); + csr_writel(value >> 16, 0xe0002804L); + csr_writel(value >> 8, 0xe0002808L); + csr_writel(value, 0xe000280cL); } -#define CSR_TIMER0_RELOAD_ADDR 0xe0002810 +#define CSR_TIMER0_RELOAD_ADDR 0xe0002810L #define CSR_TIMER0_RELOAD_SIZE 4 -static inline unsigned int timer0_reload_read(void) -{ - unsigned int r = csr_readl(0xe0002810); +static inline unsigned int timer0_reload_read(void) { + unsigned int r = csr_readl(0xe0002810L); r <<= 8; - r |= csr_readl(0xe0002814); + r |= csr_readl(0xe0002814L); r <<= 8; - r |= csr_readl(0xe0002818); + r |= csr_readl(0xe0002818L); r <<= 8; - r |= csr_readl(0xe000281c); + r |= csr_readl(0xe000281cL); return r; } -static inline void timer0_reload_write(unsigned int value) -{ - csr_writel(value >> 24, 0xe0002810); - csr_writel(value >> 16, 0xe0002814); - csr_writel(value >> 8, 0xe0002818); - csr_writel(value, 0xe000281c); +static inline void timer0_reload_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002810L); + csr_writel(value >> 16, 0xe0002814L); + csr_writel(value >> 8, 0xe0002818L); + csr_writel(value, 0xe000281cL); } -#define CSR_TIMER0_EN_ADDR 0xe0002820 +#define CSR_TIMER0_EN_ADDR 0xe0002820L #define CSR_TIMER0_EN_SIZE 1 -static inline unsigned char timer0_en_read(void) -{ - unsigned char r = csr_readl(0xe0002820); +static inline unsigned char timer0_en_read(void) { + unsigned char r = csr_readl(0xe0002820L); return r; } -static inline void timer0_en_write(unsigned char value) -{ - csr_writel(value, 0xe0002820); +static inline void timer0_en_write(unsigned char value) { + csr_writel(value, 0xe0002820L); } -#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824 +#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824L #define CSR_TIMER0_UPDATE_VALUE_SIZE 1 -static inline unsigned char timer0_update_value_read(void) -{ - unsigned char r = csr_readl(0xe0002824); +static inline unsigned char timer0_update_value_read(void) { + unsigned char r = csr_readl(0xe0002824L); return r; } -static inline void timer0_update_value_write(unsigned char value) -{ - csr_writel(value, 0xe0002824); +static inline void timer0_update_value_write(unsigned char value) { + csr_writel(value, 0xe0002824L); } -#define CSR_TIMER0_VALUE_ADDR 0xe0002828 +#define CSR_TIMER0_VALUE_ADDR 0xe0002828L #define CSR_TIMER0_VALUE_SIZE 4 -static inline unsigned int timer0_value_read(void) -{ - unsigned int r = csr_readl(0xe0002828); +static inline unsigned int timer0_value_read(void) { + unsigned int r = csr_readl(0xe0002828L); r <<= 8; - r |= csr_readl(0xe000282c); + r |= csr_readl(0xe000282cL); r <<= 8; - r |= csr_readl(0xe0002830); + r |= csr_readl(0xe0002830L); r <<= 8; - r |= csr_readl(0xe0002834); + r |= csr_readl(0xe0002834L); return r; } -#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838 +#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838L #define CSR_TIMER0_EV_STATUS_SIZE 1 -static inline unsigned char timer0_ev_status_read(void) -{ - unsigned char r = csr_readl(0xe0002838); +static inline unsigned char timer0_ev_status_read(void) { + unsigned char r = csr_readl(0xe0002838L); return r; } -static inline void timer0_ev_status_write(unsigned char value) -{ - csr_writel(value, 0xe0002838); +static inline void timer0_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0002838L); } -#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283c +#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283cL #define CSR_TIMER0_EV_PENDING_SIZE 1 -static inline unsigned char timer0_ev_pending_read(void) -{ - unsigned char r = csr_readl(0xe000283c); +static inline unsigned char timer0_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000283cL); return r; } -static inline void timer0_ev_pending_write(unsigned char value) -{ - csr_writel(value, 0xe000283c); +static inline void timer0_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000283cL); } -#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840 +#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840L #define CSR_TIMER0_EV_ENABLE_SIZE 1 -static inline unsigned char timer0_ev_enable_read(void) -{ - unsigned char r = csr_readl(0xe0002840); +static inline unsigned char timer0_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0002840L); return r; } -static inline void timer0_ev_enable_write(unsigned char value) -{ - csr_writel(value, 0xe0002840); +static inline void timer0_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0002840L); } /* touch */ -#define CSR_TOUCH_BASE 0xe0005800 -#define CSR_TOUCH_O_ADDR 0xe0005800 +#define CSR_TOUCH_BASE 0xe0005800L +#define CSR_TOUCH_O_ADDR 0xe0005800L #define CSR_TOUCH_O_SIZE 1 -static inline unsigned char touch_o_read(void) -{ - unsigned char r = csr_readl(0xe0005800); +static inline unsigned char touch_o_read(void) { + unsigned char r = csr_readl(0xe0005800L); return r; } -static inline void touch_o_write(unsigned char value) -{ - csr_writel(value, 0xe0005800); +static inline void touch_o_write(unsigned char value) { + csr_writel(value, 0xe0005800L); } -#define CSR_TOUCH_OE_ADDR 0xe0005804 +#define CSR_TOUCH_OE_ADDR 0xe0005804L #define CSR_TOUCH_OE_SIZE 1 -static inline unsigned char touch_oe_read(void) -{ - unsigned char r = csr_readl(0xe0005804); +static inline unsigned char touch_oe_read(void) { + unsigned char r = csr_readl(0xe0005804L); return r; } -static inline void touch_oe_write(unsigned char value) -{ - csr_writel(value, 0xe0005804); +static inline void touch_oe_write(unsigned char value) { + csr_writel(value, 0xe0005804L); } -#define CSR_TOUCH_I_ADDR 0xe0005808 +#define CSR_TOUCH_I_ADDR 0xe0005808L #define CSR_TOUCH_I_SIZE 1 -static inline unsigned char touch_i_read(void) -{ - unsigned char r = csr_readl(0xe0005808); +static inline unsigned char touch_i_read(void) { + unsigned char r = csr_readl(0xe0005808L); return r; } /* usb */ -#define CSR_USB_BASE 0xe0004800 -#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800 +#define CSR_USB_BASE 0xe0004800L +#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800L #define CSR_USB_PULLUP_OUT_SIZE 1 -static inline unsigned char usb_pullup_out_read(void) -{ - unsigned char r = csr_readl(0xe0004800); +static inline unsigned char usb_pullup_out_read(void) { + unsigned char r = csr_readl(0xe0004800L); return r; } -static inline void usb_pullup_out_write(unsigned char value) -{ - csr_writel(value, 0xe0004800); +static inline void usb_pullup_out_write(unsigned char value) { + csr_writel(value, 0xe0004800L); } -#define CSR_USB_EP_0_OUT_EV_STATUS_ADDR 0xe0004804 +#define CSR_USB_EP_0_OUT_EV_STATUS_ADDR 0xe0004804L #define CSR_USB_EP_0_OUT_EV_STATUS_SIZE 1 -static inline unsigned char usb_ep_0_out_ev_status_read(void) -{ - unsigned char r = csr_readl(0xe0004804); +static inline unsigned char usb_ep_0_out_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004804L); return r; } -static inline void usb_ep_0_out_ev_status_write(unsigned char value) -{ - csr_writel(value, 0xe0004804); +static inline void usb_ep_0_out_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004804L); } -#define CSR_USB_EP_0_OUT_EV_PENDING_ADDR 0xe0004808 +#define CSR_USB_EP_0_OUT_EV_PENDING_ADDR 0xe0004808L #define CSR_USB_EP_0_OUT_EV_PENDING_SIZE 1 -static inline unsigned char usb_ep_0_out_ev_pending_read(void) -{ - unsigned char r = csr_readl(0xe0004808); +static inline unsigned char usb_ep_0_out_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004808L); return r; } -static inline void usb_ep_0_out_ev_pending_write(unsigned char value) -{ - csr_writel(value, 0xe0004808); +static inline void usb_ep_0_out_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004808L); } -#define CSR_USB_EP_0_OUT_EV_ENABLE_ADDR 0xe000480c +#define CSR_USB_EP_0_OUT_EV_ENABLE_ADDR 0xe000480cL #define CSR_USB_EP_0_OUT_EV_ENABLE_SIZE 1 -static inline unsigned char usb_ep_0_out_ev_enable_read(void) -{ - unsigned char r = csr_readl(0xe000480c); +static inline unsigned char usb_ep_0_out_ev_enable_read(void) { + unsigned char r = csr_readl(0xe000480cL); return r; } -static inline void usb_ep_0_out_ev_enable_write(unsigned char value) -{ - csr_writel(value, 0xe000480c); +static inline void usb_ep_0_out_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe000480cL); } -#define CSR_USB_EP_0_OUT_LAST_TOK_ADDR 0xe0004810 +#define CSR_USB_EP_0_OUT_LAST_TOK_ADDR 0xe0004810L #define CSR_USB_EP_0_OUT_LAST_TOK_SIZE 1 -static inline unsigned char usb_ep_0_out_last_tok_read(void) -{ - unsigned char r = csr_readl(0xe0004810); +static inline unsigned char usb_ep_0_out_last_tok_read(void) { + unsigned char r = csr_readl(0xe0004810L); return r; } -#define CSR_USB_EP_0_OUT_RESPOND_ADDR 0xe0004814 +#define CSR_USB_EP_0_OUT_RESPOND_ADDR 0xe0004814L #define CSR_USB_EP_0_OUT_RESPOND_SIZE 1 -static inline unsigned char usb_ep_0_out_respond_read(void) -{ - unsigned char r = csr_readl(0xe0004814); +static inline unsigned char usb_ep_0_out_respond_read(void) { + unsigned char r = csr_readl(0xe0004814L); return r; } -static inline void usb_ep_0_out_respond_write(unsigned char value) -{ - csr_writel(value, 0xe0004814); +static inline void usb_ep_0_out_respond_write(unsigned char value) { + csr_writel(value, 0xe0004814L); } -#define CSR_USB_EP_0_OUT_DTB_ADDR 0xe0004818 +#define CSR_USB_EP_0_OUT_DTB_ADDR 0xe0004818L #define CSR_USB_EP_0_OUT_DTB_SIZE 1 -static inline unsigned char usb_ep_0_out_dtb_read(void) -{ - unsigned char r = csr_readl(0xe0004818); +static inline unsigned char usb_ep_0_out_dtb_read(void) { + unsigned char r = csr_readl(0xe0004818L); return r; } -static inline void usb_ep_0_out_dtb_write(unsigned char value) -{ - csr_writel(value, 0xe0004818); +static inline void usb_ep_0_out_dtb_write(unsigned char value) { + csr_writel(value, 0xe0004818L); } -#define CSR_USB_EP_0_OUT_OBUF_HEAD_ADDR 0xe000481c +#define CSR_USB_EP_0_OUT_OBUF_HEAD_ADDR 0xe000481cL #define CSR_USB_EP_0_OUT_OBUF_HEAD_SIZE 1 -static inline unsigned char usb_ep_0_out_obuf_head_read(void) -{ - unsigned char r = csr_readl(0xe000481c); +static inline unsigned char usb_ep_0_out_obuf_head_read(void) { + unsigned char r = csr_readl(0xe000481cL); return r; } -static inline void usb_ep_0_out_obuf_head_write(unsigned char value) -{ - csr_writel(value, 0xe000481c); +static inline void usb_ep_0_out_obuf_head_write(unsigned char value) { + csr_writel(value, 0xe000481cL); } -#define CSR_USB_EP_0_OUT_OBUF_EMPTY_ADDR 0xe0004820 +#define CSR_USB_EP_0_OUT_OBUF_EMPTY_ADDR 0xe0004820L #define CSR_USB_EP_0_OUT_OBUF_EMPTY_SIZE 1 -static inline unsigned char usb_ep_0_out_obuf_empty_read(void) -{ - unsigned char r = csr_readl(0xe0004820); +static inline unsigned char usb_ep_0_out_obuf_empty_read(void) { + unsigned char r = csr_readl(0xe0004820L); return r; } -#define CSR_USB_EP_0_IN_EV_STATUS_ADDR 0xe0004824 +#define CSR_USB_EP_0_IN_EV_STATUS_ADDR 0xe0004824L #define CSR_USB_EP_0_IN_EV_STATUS_SIZE 1 -static inline unsigned char usb_ep_0_in_ev_status_read(void) -{ - unsigned char r = csr_readl(0xe0004824); +static inline unsigned char usb_ep_0_in_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004824L); return r; } -static inline void usb_ep_0_in_ev_status_write(unsigned char value) -{ - csr_writel(value, 0xe0004824); +static inline void usb_ep_0_in_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004824L); } -#define CSR_USB_EP_0_IN_EV_PENDING_ADDR 0xe0004828 +#define CSR_USB_EP_0_IN_EV_PENDING_ADDR 0xe0004828L #define CSR_USB_EP_0_IN_EV_PENDING_SIZE 1 -static inline unsigned char usb_ep_0_in_ev_pending_read(void) -{ - unsigned char r = csr_readl(0xe0004828); +static inline unsigned char usb_ep_0_in_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004828L); return r; } -static inline void usb_ep_0_in_ev_pending_write(unsigned char value) -{ - csr_writel(value, 0xe0004828); +static inline void usb_ep_0_in_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004828L); } -#define CSR_USB_EP_0_IN_EV_ENABLE_ADDR 0xe000482c +#define CSR_USB_EP_0_IN_EV_ENABLE_ADDR 0xe000482cL #define CSR_USB_EP_0_IN_EV_ENABLE_SIZE 1 -static inline unsigned char usb_ep_0_in_ev_enable_read(void) -{ - unsigned char r = csr_readl(0xe000482c); +static inline unsigned char usb_ep_0_in_ev_enable_read(void) { + unsigned char r = csr_readl(0xe000482cL); return r; } -static inline void usb_ep_0_in_ev_enable_write(unsigned char value) -{ - csr_writel(value, 0xe000482c); +static inline void usb_ep_0_in_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe000482cL); } -#define CSR_USB_EP_0_IN_LAST_TOK_ADDR 0xe0004830 +#define CSR_USB_EP_0_IN_LAST_TOK_ADDR 0xe0004830L #define CSR_USB_EP_0_IN_LAST_TOK_SIZE 1 -static inline unsigned char usb_ep_0_in_last_tok_read(void) -{ - unsigned char r = csr_readl(0xe0004830); +static inline unsigned char usb_ep_0_in_last_tok_read(void) { + unsigned char r = csr_readl(0xe0004830L); return r; } -#define CSR_USB_EP_0_IN_RESPOND_ADDR 0xe0004834 +#define CSR_USB_EP_0_IN_RESPOND_ADDR 0xe0004834L #define CSR_USB_EP_0_IN_RESPOND_SIZE 1 -static inline unsigned char usb_ep_0_in_respond_read(void) -{ - unsigned char r = csr_readl(0xe0004834); +static inline unsigned char usb_ep_0_in_respond_read(void) { + unsigned char r = csr_readl(0xe0004834L); return r; } -static inline void usb_ep_0_in_respond_write(unsigned char value) -{ - csr_writel(value, 0xe0004834); +static inline void usb_ep_0_in_respond_write(unsigned char value) { + csr_writel(value, 0xe0004834L); } -#define CSR_USB_EP_0_IN_DTB_ADDR 0xe0004838 +#define CSR_USB_EP_0_IN_DTB_ADDR 0xe0004838L #define CSR_USB_EP_0_IN_DTB_SIZE 1 -static inline unsigned char usb_ep_0_in_dtb_read(void) -{ - unsigned char r = csr_readl(0xe0004838); +static inline unsigned char usb_ep_0_in_dtb_read(void) { + unsigned char r = csr_readl(0xe0004838L); return r; } -static inline void usb_ep_0_in_dtb_write(unsigned char value) -{ - csr_writel(value, 0xe0004838); +static inline void usb_ep_0_in_dtb_write(unsigned char value) { + csr_writel(value, 0xe0004838L); } -#define CSR_USB_EP_0_IN_IBUF_HEAD_ADDR 0xe000483c +#define CSR_USB_EP_0_IN_IBUF_HEAD_ADDR 0xe000483cL #define CSR_USB_EP_0_IN_IBUF_HEAD_SIZE 1 -static inline unsigned char usb_ep_0_in_ibuf_head_read(void) -{ - unsigned char r = csr_readl(0xe000483c); +static inline unsigned char usb_ep_0_in_ibuf_head_read(void) { + unsigned char r = csr_readl(0xe000483cL); return r; } -static inline void usb_ep_0_in_ibuf_head_write(unsigned char value) -{ - csr_writel(value, 0xe000483c); +static inline void usb_ep_0_in_ibuf_head_write(unsigned char value) { + csr_writel(value, 0xe000483cL); } -#define CSR_USB_EP_0_IN_IBUF_EMPTY_ADDR 0xe0004840 +#define CSR_USB_EP_0_IN_IBUF_EMPTY_ADDR 0xe0004840L #define CSR_USB_EP_0_IN_IBUF_EMPTY_SIZE 1 -static inline unsigned char usb_ep_0_in_ibuf_empty_read(void) -{ - unsigned char r = csr_readl(0xe0004840); +static inline unsigned char usb_ep_0_in_ibuf_empty_read(void) { + unsigned char r = csr_readl(0xe0004840L); return r; } -#define CSR_USB_EP_1_IN_EV_STATUS_ADDR 0xe0004844 +#define CSR_USB_EP_1_IN_EV_STATUS_ADDR 0xe0004844L #define CSR_USB_EP_1_IN_EV_STATUS_SIZE 1 -static inline unsigned char usb_ep_1_in_ev_status_read(void) -{ - unsigned char r = csr_readl(0xe0004844); +static inline unsigned char usb_ep_1_in_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004844L); return r; } -static inline void usb_ep_1_in_ev_status_write(unsigned char value) -{ - csr_writel(value, 0xe0004844); +static inline void usb_ep_1_in_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004844L); } -#define CSR_USB_EP_1_IN_EV_PENDING_ADDR 0xe0004848 +#define CSR_USB_EP_1_IN_EV_PENDING_ADDR 0xe0004848L #define CSR_USB_EP_1_IN_EV_PENDING_SIZE 1 -static inline unsigned char usb_ep_1_in_ev_pending_read(void) -{ - unsigned char r = csr_readl(0xe0004848); +static inline unsigned char usb_ep_1_in_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004848L); return r; } -static inline void usb_ep_1_in_ev_pending_write(unsigned char value) -{ - csr_writel(value, 0xe0004848); +static inline void usb_ep_1_in_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004848L); } -#define CSR_USB_EP_1_IN_EV_ENABLE_ADDR 0xe000484c +#define CSR_USB_EP_1_IN_EV_ENABLE_ADDR 0xe000484cL #define CSR_USB_EP_1_IN_EV_ENABLE_SIZE 1 -static inline unsigned char usb_ep_1_in_ev_enable_read(void) -{ - unsigned char r = csr_readl(0xe000484c); +static inline unsigned char usb_ep_1_in_ev_enable_read(void) { + unsigned char r = csr_readl(0xe000484cL); return r; } -static inline void usb_ep_1_in_ev_enable_write(unsigned char value) -{ - csr_writel(value, 0xe000484c); +static inline void usb_ep_1_in_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe000484cL); } -#define CSR_USB_EP_1_IN_LAST_TOK_ADDR 0xe0004850 +#define CSR_USB_EP_1_IN_LAST_TOK_ADDR 0xe0004850L #define CSR_USB_EP_1_IN_LAST_TOK_SIZE 1 -static inline unsigned char usb_ep_1_in_last_tok_read(void) -{ - unsigned char r = csr_readl(0xe0004850); +static inline unsigned char usb_ep_1_in_last_tok_read(void) { + unsigned char r = csr_readl(0xe0004850L); return r; } -#define CSR_USB_EP_1_IN_RESPOND_ADDR 0xe0004854 +#define CSR_USB_EP_1_IN_RESPOND_ADDR 0xe0004854L #define CSR_USB_EP_1_IN_RESPOND_SIZE 1 -static inline unsigned char usb_ep_1_in_respond_read(void) -{ - unsigned char r = csr_readl(0xe0004854); +static inline unsigned char usb_ep_1_in_respond_read(void) { + unsigned char r = csr_readl(0xe0004854L); return r; } -static inline void usb_ep_1_in_respond_write(unsigned char value) -{ - csr_writel(value, 0xe0004854); +static inline void usb_ep_1_in_respond_write(unsigned char value) { + csr_writel(value, 0xe0004854L); } -#define CSR_USB_EP_1_IN_DTB_ADDR 0xe0004858 +#define CSR_USB_EP_1_IN_DTB_ADDR 0xe0004858L #define CSR_USB_EP_1_IN_DTB_SIZE 1 -static inline unsigned char usb_ep_1_in_dtb_read(void) -{ - unsigned char r = csr_readl(0xe0004858); +static inline unsigned char usb_ep_1_in_dtb_read(void) { + unsigned char r = csr_readl(0xe0004858L); return r; } -static inline void usb_ep_1_in_dtb_write(unsigned char value) -{ - csr_writel(value, 0xe0004858); +static inline void usb_ep_1_in_dtb_write(unsigned char value) { + csr_writel(value, 0xe0004858L); } -#define CSR_USB_EP_1_IN_IBUF_HEAD_ADDR 0xe000485c +#define CSR_USB_EP_1_IN_IBUF_HEAD_ADDR 0xe000485cL #define CSR_USB_EP_1_IN_IBUF_HEAD_SIZE 1 -static inline unsigned char usb_ep_1_in_ibuf_head_read(void) -{ - unsigned char r = csr_readl(0xe000485c); +static inline unsigned char usb_ep_1_in_ibuf_head_read(void) { + unsigned char r = csr_readl(0xe000485cL); return r; } -static inline void usb_ep_1_in_ibuf_head_write(unsigned char value) -{ - csr_writel(value, 0xe000485c); +static inline void usb_ep_1_in_ibuf_head_write(unsigned char value) { + csr_writel(value, 0xe000485cL); } -#define CSR_USB_EP_1_IN_IBUF_EMPTY_ADDR 0xe0004860 +#define CSR_USB_EP_1_IN_IBUF_EMPTY_ADDR 0xe0004860L #define CSR_USB_EP_1_IN_IBUF_EMPTY_SIZE 1 -static inline unsigned char usb_ep_1_in_ibuf_empty_read(void) -{ - unsigned char r = csr_readl(0xe0004860); +static inline unsigned char usb_ep_1_in_ibuf_empty_read(void) { + unsigned char r = csr_readl(0xe0004860L); return r; } -#define CSR_USB_EP_2_OUT_EV_STATUS_ADDR 0xe0004864 +#define CSR_USB_EP_2_OUT_EV_STATUS_ADDR 0xe0004864L #define CSR_USB_EP_2_OUT_EV_STATUS_SIZE 1 -static inline unsigned char usb_ep_2_out_ev_status_read(void) -{ - unsigned char r = csr_readl(0xe0004864); +static inline unsigned char usb_ep_2_out_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004864L); return r; } -static inline void usb_ep_2_out_ev_status_write(unsigned char value) -{ - csr_writel(value, 0xe0004864); +static inline void usb_ep_2_out_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004864L); } -#define CSR_USB_EP_2_OUT_EV_PENDING_ADDR 0xe0004868 +#define CSR_USB_EP_2_OUT_EV_PENDING_ADDR 0xe0004868L #define CSR_USB_EP_2_OUT_EV_PENDING_SIZE 1 -static inline unsigned char usb_ep_2_out_ev_pending_read(void) -{ - unsigned char r = csr_readl(0xe0004868); +static inline unsigned char usb_ep_2_out_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004868L); return r; } -static inline void usb_ep_2_out_ev_pending_write(unsigned char value) -{ - csr_writel(value, 0xe0004868); +static inline void usb_ep_2_out_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004868L); } -#define CSR_USB_EP_2_OUT_EV_ENABLE_ADDR 0xe000486c +#define CSR_USB_EP_2_OUT_EV_ENABLE_ADDR 0xe000486cL #define CSR_USB_EP_2_OUT_EV_ENABLE_SIZE 1 -static inline unsigned char usb_ep_2_out_ev_enable_read(void) -{ - unsigned char r = csr_readl(0xe000486c); +static inline unsigned char usb_ep_2_out_ev_enable_read(void) { + unsigned char r = csr_readl(0xe000486cL); return r; } -static inline void usb_ep_2_out_ev_enable_write(unsigned char value) -{ - csr_writel(value, 0xe000486c); +static inline void usb_ep_2_out_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe000486cL); } -#define CSR_USB_EP_2_OUT_LAST_TOK_ADDR 0xe0004870 +#define CSR_USB_EP_2_OUT_LAST_TOK_ADDR 0xe0004870L #define CSR_USB_EP_2_OUT_LAST_TOK_SIZE 1 -static inline unsigned char usb_ep_2_out_last_tok_read(void) -{ - unsigned char r = csr_readl(0xe0004870); +static inline unsigned char usb_ep_2_out_last_tok_read(void) { + unsigned char r = csr_readl(0xe0004870L); return r; } -#define CSR_USB_EP_2_OUT_RESPOND_ADDR 0xe0004874 +#define CSR_USB_EP_2_OUT_RESPOND_ADDR 0xe0004874L #define CSR_USB_EP_2_OUT_RESPOND_SIZE 1 -static inline unsigned char usb_ep_2_out_respond_read(void) -{ - unsigned char r = csr_readl(0xe0004874); +static inline unsigned char usb_ep_2_out_respond_read(void) { + unsigned char r = csr_readl(0xe0004874L); return r; } -static inline void usb_ep_2_out_respond_write(unsigned char value) -{ - csr_writel(value, 0xe0004874); +static inline void usb_ep_2_out_respond_write(unsigned char value) { + csr_writel(value, 0xe0004874L); } -#define CSR_USB_EP_2_OUT_DTB_ADDR 0xe0004878 +#define CSR_USB_EP_2_OUT_DTB_ADDR 0xe0004878L #define CSR_USB_EP_2_OUT_DTB_SIZE 1 -static inline unsigned char usb_ep_2_out_dtb_read(void) -{ - unsigned char r = csr_readl(0xe0004878); +static inline unsigned char usb_ep_2_out_dtb_read(void) { + unsigned char r = csr_readl(0xe0004878L); return r; } -static inline void usb_ep_2_out_dtb_write(unsigned char value) -{ - csr_writel(value, 0xe0004878); +static inline void usb_ep_2_out_dtb_write(unsigned char value) { + csr_writel(value, 0xe0004878L); } -#define CSR_USB_EP_2_OUT_OBUF_HEAD_ADDR 0xe000487c +#define CSR_USB_EP_2_OUT_OBUF_HEAD_ADDR 0xe000487cL #define CSR_USB_EP_2_OUT_OBUF_HEAD_SIZE 1 -static inline unsigned char usb_ep_2_out_obuf_head_read(void) -{ - unsigned char r = csr_readl(0xe000487c); +static inline unsigned char usb_ep_2_out_obuf_head_read(void) { + unsigned char r = csr_readl(0xe000487cL); return r; } -static inline void usb_ep_2_out_obuf_head_write(unsigned char value) -{ - csr_writel(value, 0xe000487c); +static inline void usb_ep_2_out_obuf_head_write(unsigned char value) { + csr_writel(value, 0xe000487cL); } -#define CSR_USB_EP_2_OUT_OBUF_EMPTY_ADDR 0xe0004880 +#define CSR_USB_EP_2_OUT_OBUF_EMPTY_ADDR 0xe0004880L #define CSR_USB_EP_2_OUT_OBUF_EMPTY_SIZE 1 -static inline unsigned char usb_ep_2_out_obuf_empty_read(void) -{ - unsigned char r = csr_readl(0xe0004880); +static inline unsigned char usb_ep_2_out_obuf_empty_read(void) { + unsigned char r = csr_readl(0xe0004880L); return r; } -#define CSR_USB_EP_2_IN_EV_STATUS_ADDR 0xe0004884 +#define CSR_USB_EP_2_IN_EV_STATUS_ADDR 0xe0004884L #define CSR_USB_EP_2_IN_EV_STATUS_SIZE 1 -static inline unsigned char usb_ep_2_in_ev_status_read(void) -{ - unsigned char r = csr_readl(0xe0004884); +static inline unsigned char usb_ep_2_in_ev_status_read(void) { + unsigned char r = csr_readl(0xe0004884L); return r; } -static inline void usb_ep_2_in_ev_status_write(unsigned char value) -{ - csr_writel(value, 0xe0004884); +static inline void usb_ep_2_in_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0004884L); } -#define CSR_USB_EP_2_IN_EV_PENDING_ADDR 0xe0004888 +#define CSR_USB_EP_2_IN_EV_PENDING_ADDR 0xe0004888L #define CSR_USB_EP_2_IN_EV_PENDING_SIZE 1 -static inline unsigned char usb_ep_2_in_ev_pending_read(void) -{ - unsigned char r = csr_readl(0xe0004888); +static inline unsigned char usb_ep_2_in_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004888L); return r; } -static inline void usb_ep_2_in_ev_pending_write(unsigned char value) -{ - csr_writel(value, 0xe0004888); +static inline void usb_ep_2_in_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004888L); } -#define CSR_USB_EP_2_IN_EV_ENABLE_ADDR 0xe000488c +#define CSR_USB_EP_2_IN_EV_ENABLE_ADDR 0xe000488cL #define CSR_USB_EP_2_IN_EV_ENABLE_SIZE 1 -static inline unsigned char usb_ep_2_in_ev_enable_read(void) -{ - unsigned char r = csr_readl(0xe000488c); +static inline unsigned char usb_ep_2_in_ev_enable_read(void) { + unsigned char r = csr_readl(0xe000488cL); return r; } -static inline void usb_ep_2_in_ev_enable_write(unsigned char value) -{ - csr_writel(value, 0xe000488c); +static inline void usb_ep_2_in_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe000488cL); } -#define CSR_USB_EP_2_IN_LAST_TOK_ADDR 0xe0004890 +#define CSR_USB_EP_2_IN_LAST_TOK_ADDR 0xe0004890L #define CSR_USB_EP_2_IN_LAST_TOK_SIZE 1 -static inline unsigned char usb_ep_2_in_last_tok_read(void) -{ - unsigned char r = csr_readl(0xe0004890); +static inline unsigned char usb_ep_2_in_last_tok_read(void) { + unsigned char r = csr_readl(0xe0004890L); return r; } -#define CSR_USB_EP_2_IN_RESPOND_ADDR 0xe0004894 +#define CSR_USB_EP_2_IN_RESPOND_ADDR 0xe0004894L #define CSR_USB_EP_2_IN_RESPOND_SIZE 1 -static inline unsigned char usb_ep_2_in_respond_read(void) -{ - unsigned char r = csr_readl(0xe0004894); +static inline unsigned char usb_ep_2_in_respond_read(void) { + unsigned char r = csr_readl(0xe0004894L); return r; } -static inline void usb_ep_2_in_respond_write(unsigned char value) -{ - csr_writel(value, 0xe0004894); +static inline void usb_ep_2_in_respond_write(unsigned char value) { + csr_writel(value, 0xe0004894L); } -#define CSR_USB_EP_2_IN_DTB_ADDR 0xe0004898 +#define CSR_USB_EP_2_IN_DTB_ADDR 0xe0004898L #define CSR_USB_EP_2_IN_DTB_SIZE 1 -static inline unsigned char usb_ep_2_in_dtb_read(void) -{ - unsigned char r = csr_readl(0xe0004898); +static inline unsigned char usb_ep_2_in_dtb_read(void) { + unsigned char r = csr_readl(0xe0004898L); return r; } -static inline void usb_ep_2_in_dtb_write(unsigned char value) -{ - csr_writel(value, 0xe0004898); +static inline void usb_ep_2_in_dtb_write(unsigned char value) { + csr_writel(value, 0xe0004898L); } -#define CSR_USB_EP_2_IN_IBUF_HEAD_ADDR 0xe000489c +#define CSR_USB_EP_2_IN_IBUF_HEAD_ADDR 0xe000489cL #define CSR_USB_EP_2_IN_IBUF_HEAD_SIZE 1 -static inline unsigned char usb_ep_2_in_ibuf_head_read(void) -{ - unsigned char r = csr_readl(0xe000489c); +static inline unsigned char usb_ep_2_in_ibuf_head_read(void) { + unsigned char r = csr_readl(0xe000489cL); return r; } -static inline void usb_ep_2_in_ibuf_head_write(unsigned char value) -{ - csr_writel(value, 0xe000489c); +static inline void usb_ep_2_in_ibuf_head_write(unsigned char value) { + csr_writel(value, 0xe000489cL); } -#define CSR_USB_EP_2_IN_IBUF_EMPTY_ADDR 0xe00048a0 +#define CSR_USB_EP_2_IN_IBUF_EMPTY_ADDR 0xe00048a0L #define CSR_USB_EP_2_IN_IBUF_EMPTY_SIZE 1 -static inline unsigned char usb_ep_2_in_ibuf_empty_read(void) -{ - unsigned char r = csr_readl(0xe00048a0); +static inline unsigned char usb_ep_2_in_ibuf_empty_read(void) { + unsigned char r = csr_readl(0xe00048a0L); return r; } /* version */ -#define CSR_VERSION_BASE 0xe0007000 -#define CSR_VERSION_MAJOR_ADDR 0xe0007000 +#define CSR_VERSION_BASE 0xe0007000L +#define CSR_VERSION_MAJOR_ADDR 0xe0007000L #define CSR_VERSION_MAJOR_SIZE 1 -static inline unsigned char version_major_read(void) -{ - unsigned char r = csr_readl(0xe0007000); +static inline unsigned char version_major_read(void) { + unsigned char r = csr_readl(0xe0007000L); return r; } -#define CSR_VERSION_MINOR_ADDR 0xe0007004 +#define CSR_VERSION_MINOR_ADDR 0xe0007004L #define CSR_VERSION_MINOR_SIZE 1 -static inline unsigned char version_minor_read(void) -{ - unsigned char r = csr_readl(0xe0007004); +static inline unsigned char version_minor_read(void) { + unsigned char r = csr_readl(0xe0007004L); return r; } -#define CSR_VERSION_REVISION_ADDR 0xe0007008 +#define CSR_VERSION_REVISION_ADDR 0xe0007008L #define CSR_VERSION_REVISION_SIZE 1 -static inline unsigned char version_revision_read(void) -{ - unsigned char r = csr_readl(0xe0007008); +static inline unsigned char version_revision_read(void) { + unsigned char r = csr_readl(0xe0007008L); return r; } -#define CSR_VERSION_GITREV_ADDR 0xe000700c +#define CSR_VERSION_GITREV_ADDR 0xe000700cL #define CSR_VERSION_GITREV_SIZE 4 -static inline unsigned int version_gitrev_read(void) -{ - unsigned int r = csr_readl(0xe000700c); +static inline unsigned int version_gitrev_read(void) { + unsigned int r = csr_readl(0xe000700cL); r <<= 8; - r |= csr_readl(0xe0007010); + r |= csr_readl(0xe0007010L); r <<= 8; - r |= csr_readl(0xe0007014); + r |= csr_readl(0xe0007014L); r <<= 8; - r |= csr_readl(0xe0007018); + r |= csr_readl(0xe0007018L); return r; } -#define CSR_VERSION_GITEXTRA_ADDR 0xe000701c +#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL #define CSR_VERSION_GITEXTRA_SIZE 2 -static inline unsigned short int version_gitextra_read(void) -{ - unsigned short int r = csr_readl(0xe000701c); +static inline unsigned short int version_gitextra_read(void) { + unsigned short int r = csr_readl(0xe000701cL); r <<= 8; - r |= csr_readl(0xe0007020); + r |= csr_readl(0xe0007020L); return r; } -#define CSR_VERSION_DIRTY_ADDR 0xe0007024 +#define CSR_VERSION_DIRTY_ADDR 0xe0007024L #define CSR_VERSION_DIRTY_SIZE 1 -static inline unsigned char version_dirty_read(void) -{ - unsigned char r = csr_readl(0xe0007024); +static inline unsigned char version_dirty_read(void) { + unsigned char r = csr_readl(0xe0007024L); return r; } /* constants */ -#define NMI_INTERRUPT 0 -static inline int nmi_interrupt_read(void) -{ +#define TIMER0_INTERRUPT 0 +static inline int timer0_interrupt_read(void) { return 0; } -#define TIMER0_INTERRUPT 1 -static inline int timer0_interrupt_read(void) -{ - return 1; -} -#define UART_INTERRUPT 2 -static inline int uart_interrupt_read(void) -{ - return 2; -} #define USB_INTERRUPT 3 -static inline int usb_interrupt_read(void) -{ +static inline int usb_interrupt_read(void) { return 3; } #define CSR_DATA_WIDTH 8 -static inline int csr_data_width_read(void) -{ +static inline int csr_data_width_read(void) { return 8; } #define SYSTEM_CLOCK_FREQUENCY 12000000 -static inline int system_clock_frequency_read(void) -{ +static inline int system_clock_frequency_read(void) { return 12000000; } +#define ROM_DISABLE 1 +static inline int rom_disable_read(void) { + return 1; +} #define CONFIG_CLOCK_FREQUENCY 12000000 -static inline int config_clock_frequency_read(void) -{ +static inline int config_clock_frequency_read(void) { return 12000000; } #define CONFIG_CPU_RESET_ADDR 0 -static inline int config_cpu_reset_addr_read(void) -{ +static inline int config_cpu_reset_addr_read(void) { return 0; } #define CONFIG_CPU_TYPE "VEXRISCV" -static inline const char *config_cpu_type_read(void) -{ +static inline const char * config_cpu_type_read(void) { return "VEXRISCV"; } #define CONFIG_CPU_VARIANT "VEXRISCV" -static inline const char *config_cpu_variant_read(void) -{ +static inline const char * config_cpu_variant_read(void) { return "VEXRISCV"; } #define CONFIG_CSR_DATA_WIDTH 8 -static inline int config_csr_data_width_read(void) -{ +static inline int config_csr_data_width_read(void) { return 8; } diff --git a/sw/include/hw/common.h b/sw/include/hw/common.h new file mode 100644 index 0000000..af668f7 --- /dev/null +++ b/sw/include/hw/common.h @@ -0,0 +1,52 @@ +#ifndef __HW_COMMON_H +#define __HW_COMMON_H + +#include + +/* To overwrite CSR accessors, define extern, non-inlined versions + * of csr_read[bwl]() and csr_write[bwl](), and define + * CSR_ACCESSORS_DEFINED. + */ + +#ifndef CSR_ACCESSORS_DEFINED +#define CSR_ACCESSORS_DEFINED + +#ifdef __ASSEMBLER__ +#define MMPTR(x) x +#else /* ! __ASSEMBLER__ */ +#define MMPTR(x) (*((volatile unsigned int *)(x))) + +static inline void csr_writeb(uint8_t value, uint32_t addr) +{ + *((volatile uint8_t *)addr) = value; +} + +static inline uint8_t csr_readb(uint32_t addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline void csr_writew(uint16_t value, uint32_t addr) +{ + *((volatile uint16_t *)addr) = value; +} + +static inline uint16_t csr_readw(uint32_t addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline void csr_writel(uint32_t value, uint32_t addr) +{ + *((volatile uint32_t *)addr) = value; +} + +static inline uint32_t csr_readl(uint32_t addr) +{ + return *(volatile uint32_t *)addr; +} +#endif /* ! __ASSEMBLER__ */ + +#endif /* ! CSR_ACCESSORS_DEFINED */ + +#endif /* __HW_COMMON_H */ diff --git a/sw/include/rgb.h b/sw/include/rgb.h index 6a68122..399ee44 100644 --- a/sw/include/rgb.h +++ b/sw/include/rgb.h @@ -6,5 +6,6 @@ void rgb_mode_idle(void); void rgb_mode_done(void); void rgb_mode_writing(void); void rgb_mode_error(void); +void rgb_mode_off(void); #endif /* _RGB_H_ */ \ No newline at end of file diff --git a/sw/include/spi.h b/sw/include/spi.h index b537f2d..8df0f3e 100644 --- a/sw/include/spi.h +++ b/sw/include/spi.h @@ -50,45 +50,43 @@ struct spi_id { struct ff_spi; -void spiPause(struct ff_spi *spi); -void spiBegin(struct ff_spi *spi); -void spiEnd(struct ff_spi *spi); +void spiPause(void); +void spiBegin(void); +void spiEnd(void); -//void spiSingleTx(struct ff_spi *spi, uint8_t out); -//uint8_t spiSingleRx(struct ff_spi *spi); -//void spiDualTx(struct ff_spi *spi, uint8_t out); -//void spiQuadTx(struct ff_spi *spi, uint8_t out); -void spiCommand(struct ff_spi *spi, uint8_t cmd); -//uint8_t spiDualRx(struct ff_spi *spi); -//uint8_t spiQuadRx(struct ff_spi *spi); -int spiTx(struct ff_spi *spi, uint8_t word); -uint8_t spiRx(struct ff_spi *spi); -uint8_t spiReadStatus(struct ff_spi *spi, uint8_t sr); -void spiWriteStatus(struct ff_spi *spi, uint8_t sr, uint8_t val); -void spiReadSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]); -void spiWriteSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]); -int spiSetType(struct ff_spi *spi, enum spi_type type); -int spiRead(struct ff_spi *spi, uint32_t addr, uint8_t *data, unsigned int count); -int spiIsBusy(struct ff_spi *spi); -int spiBeginErase32(struct ff_spi *spi, uint32_t erase_addr); -int spiBeginErase64(struct ff_spi *spi, uint32_t erase_addr); -int spiBeginWrite(struct ff_spi *spi, uint32_t addr, const void *data, unsigned int count); +//void spiSingleTx(uint8_t out); +//uint8_t spiSingleRx(void); +//void spiDualTx(uint8_t out); +//void spiQuadTx(uint8_t out); +void spiCommand(uint8_t cmd); +//uint8_t spiDualRx(void); +//uint8_t spiQuadRx(void); +int spiTx(uint8_t word); +uint8_t spiRx(void); +uint8_t spiReadStatus(uint8_t sr); +void spiWriteStatus(uint8_t sr, uint8_t val); +void spiReadSecurity(uint8_t sr, uint8_t security[256]); +void spiWriteSecurity(uint8_t sr, uint8_t security[256]); +int spiSetType(enum spi_type type); +int spiRead(uint32_t addr, uint8_t *data, unsigned int count); +int spiIsBusy(void); +int spiBeginErase32(uint32_t erase_addr); +int spiBeginErase64(uint32_t erase_addr); +int spiBeginWrite(uint32_t addr, const void *data, unsigned int count); void spiEnableQuad(void); -struct spi_id spiId(struct ff_spi *spi); -void spiOverrideSize(struct ff_spi *spi, uint32_t new_size); +struct spi_id spiId(void); +void spiOverrideSize(uint32_t new_size); -//int spi_wait_for_not_busy(struct ff_spi *spi); -int spiWrite(struct ff_spi *spi, uint32_t addr, const uint8_t *data, unsigned int count); -uint8_t spiReset(struct ff_spi *spi); -int spiInit(struct ff_spi *spi); +int spiWrite(uint32_t addr, const uint8_t *data, unsigned int count); +uint8_t spiReset(void); +int spi_init(void); -void spiHold(struct ff_spi *spi); -void spiUnhold(struct ff_spi *spi); -void spiSwapTxRx(struct ff_spi *spi); +void spiHold(void); +void spiUnhold(void); +void spiSwapTxRx(void); -struct ff_spi *spiAlloc(void); -void spiSetPin(struct ff_spi *spi, enum spi_pin pin, int val); +void spiSetPin(enum spi_pin pin, int val); void spiFree(void); #endif /* BB_SPI_H_ */ diff --git a/sw/include/usb-desc.h b/sw/include/usb-desc.h index ba132ed..5af88f9 100644 --- a/sw/include/usb-desc.h +++ b/sw/include/usb-desc.h @@ -62,7 +62,7 @@ struct usb_string_descriptor_struct { #define PRODUCT_NAME u"Fomu Factory Test " GIT_VERSION #define PRODUCT_NAME_LEN sizeof(PRODUCT_NAME) #define EP0_SIZE 64 -#define NUM_INTERFACE 1 +#define NUM_INTERFACE 2 #define CONFIG_DESC_SIZE 67 #define USB_DT_INTERFACE_SIZE 9 diff --git a/sw/include/usb.h b/sw/include/usb.h index 7b0df47..bdb2a90 100644 --- a/sw/include/usb.h +++ b/sw/include/usb.h @@ -33,7 +33,7 @@ void usb_idle(void); void usb_disconnect(void); int usb_irq_happened(void); -void usb_setup(const struct usb_setup_request *setup); +int usb_setup(const struct usb_setup_request *setup); void usb_send(const void *data, int total_count); void usb_ack_in(void); void usb_ack_out(void); diff --git a/sw/src/main.c b/sw/src/main.c index 2d87c72..91a2178 100644 --- a/sw/src/main.c +++ b/sw/src/main.c @@ -22,13 +22,11 @@ void isr(void) static void init(void) { rgb_init(); - spi = spiAlloc(); - spiInit(spi); + spi_init(); irq_setmask(0); irq_setie(1); usb_init(); time_init(); - } int main(int argc, char **argv) diff --git a/sw/src/rgb.c b/sw/src/rgb.c index 3596989..c65612e 100644 --- a/sw/src/rgb.c +++ b/sw/src/rgb.c @@ -34,6 +34,7 @@ static enum { WRITING, ERROR, DONE, + OFF, } rgb_mode; static void rgb_write(uint8_t value, uint8_t addr) { @@ -86,4 +87,8 @@ void rgb_mode_error(void) { void rgb_mode_done(void) { rgb_switch_mode(DONE, 8, 8, 2, 3, 0x14/4, 0xff/4, 0x44/4); +} + +void rgb_mode_off(void) { + rgb_switch_mode(OFF, 0, 0, 0, 0, 0, 0, 0); } \ No newline at end of file diff --git a/sw/src/spi.c b/sw/src/spi.c index 56e7a31..b0923b1 100644 --- a/sw/src/spi.c +++ b/sw/src/spi.c @@ -39,12 +39,6 @@ static int gpioRead(int pin) { return !!(picorvspi_stat1_read() & (1 << pin)); } -static void gpioSync(void) { - // bbspi_do_write(do_mirror); -} - -#define SPI_ONLY_SINGLE - enum ff_spi_quirks { // There is no separate "Write SR 2" command. Instead, // you must write SR2 after writing SR1 @@ -67,251 +61,192 @@ struct ff_spi { int size_override; struct { + union { + int mosi; + int d0; + }; + union { + int miso; + int d1; + }; + union { + int wp; + int d2; + }; + union { + int hold; + int d3; + }; int clk; - int d0; - int d1; - int d2; - int d3; - int wp; - int hold; int cs; - int miso; - int mosi; } pins; }; +static struct ff_spi spi; -static void spi_get_id(struct ff_spi *spi); +static void spi_get_id(void); -static void spi_set_state(struct ff_spi *spi, enum spi_state state) { - return; - if (spi->state == state) +static void spi_set_state(enum spi_state state) { + if (spi.state == state) return; -#ifndef SPI_ONLY_SINGLE + switch (state) { case SS_SINGLE: -#endif - gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK - gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0# - gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI - gpioSetMode(spi->pins.miso, PI_INPUT); // MISO - gpioSetMode(spi->pins.hold, PI_OUTPUT); - gpioSetMode(spi->pins.wp, PI_OUTPUT); -#ifndef SPI_ONLY_SINGLE - break; - - case SS_DUAL_RX: - gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK - gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0# - gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI - gpioSetMode(spi->pins.miso, PI_INPUT); // MISO - gpioSetMode(spi->pins.hold, PI_OUTPUT); - gpioSetMode(spi->pins.wp, PI_OUTPUT); - break; - - case SS_DUAL_TX: - gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK - gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0# - gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI - gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO - gpioSetMode(spi->pins.hold, PI_OUTPUT); - gpioSetMode(spi->pins.wp, PI_OUTPUT); + gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK + gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0# + gpioSetMode(spi.pins.mosi, PI_OUTPUT); // MOSI + gpioSetMode(spi.pins.miso, PI_INPUT); // MISO + gpioSetMode(spi.pins.hold, PI_OUTPUT); + gpioSetMode(spi.pins.wp, PI_OUTPUT); break; case SS_QUAD_RX: - gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK - gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0# - gpioSetMode(spi->pins.mosi, PI_INPUT); // MOSI - gpioSetMode(spi->pins.miso, PI_INPUT); // MISO - gpioSetMode(spi->pins.hold, PI_INPUT); - gpioSetMode(spi->pins.wp, PI_INPUT); + gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK + gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0# + gpioSetMode(spi.pins.mosi, PI_INPUT); // MOSI + gpioSetMode(spi.pins.miso, PI_INPUT); // MISO + gpioSetMode(spi.pins.hold, PI_INPUT); + gpioSetMode(spi.pins.wp, PI_INPUT); break; case SS_QUAD_TX: - gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK - gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0# - gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI - gpioSetMode(spi->pins.miso, PI_OUTPUT); // MISO - gpioSetMode(spi->pins.hold, PI_OUTPUT); - gpioSetMode(spi->pins.wp, PI_OUTPUT); + gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK + gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0# + gpioSetMode(spi.pins.mosi, PI_OUTPUT); // MOSI + gpioSetMode(spi.pins.miso, PI_OUTPUT); // MISO + gpioSetMode(spi.pins.hold, PI_OUTPUT); + gpioSetMode(spi.pins.wp, PI_OUTPUT); break; case SS_HARDWARE: - gpioSetMode(spi->pins.clk, PI_ALT0); // CLK - gpioSetMode(spi->pins.cs, PI_ALT0); // CE0# - gpioSetMode(spi->pins.mosi, PI_ALT0); // MOSI - gpioSetMode(spi->pins.miso, PI_ALT0); // MISO - gpioSetMode(spi->pins.hold, PI_OUTPUT); - gpioSetMode(spi->pins.wp, PI_OUTPUT); + gpioSetMode(spi.pins.clk, PI_ALT0); // CLK + gpioSetMode(spi.pins.cs, PI_ALT0); // CE0# + gpioSetMode(spi.pins.mosi, PI_ALT0); // MOSI + gpioSetMode(spi.pins.miso, PI_ALT0); // MISO + gpioSetMode(spi.pins.hold, PI_OUTPUT); + gpioSetMode(spi.pins.wp, PI_OUTPUT); break; default: fprintf(stderr, "Unrecognized spi state\n"); return; } -#endif - spi->state = state; + spi.state = state; } -void spiPause(struct ff_spi *spi) { - (void)spi; - gpioSync(); +void spiPause(void) { // usleep(1); return; } -void spiBegin(struct ff_spi *spi) { - spi_set_state(spi, SS_SINGLE); - if ((spi->type == ST_SINGLE) || (spi->type == ST_DUAL)) { - gpioWrite(spi->pins.wp, 1); - gpioWrite(spi->pins.hold, 1); +void spiBegin(void) { + spi_set_state(SS_SINGLE); + if ((spi.type == ST_SINGLE)) { + gpioWrite(spi.pins.wp, 1); + gpioWrite(spi.pins.hold, 1); } - gpioWrite(spi->pins.cs, 0); + gpioWrite(spi.pins.cs, 0); } -void spiEnd(struct ff_spi *spi) { +void spiEnd(void) { (void)spi; - gpioWrite(spi->pins.cs, 1); + gpioWrite(spi.pins.cs, 1); } -static uint8_t spiXfer(struct ff_spi *spi, uint8_t out) { +static uint8_t spiXfer(uint8_t out) { int bit; uint8_t in = 0; for (bit = 7; bit >= 0; bit--) { if (out & (1 << bit)) { - gpioWrite(spi->pins.mosi, 1); + gpioWrite(spi.pins.mosi, 1); } else { - gpioWrite(spi->pins.mosi, 0); + gpioWrite(spi.pins.mosi, 0); } - gpioWrite(spi->pins.clk, 1); - spiPause(spi); - in |= ((!!gpioRead(spi->pins.miso)) << bit); - gpioWrite(spi->pins.clk, 0); - spiPause(spi); + gpioWrite(spi.pins.clk, 1); + spiPause(); + in |= ((!!gpioRead(spi.pins.miso)) << bit); + gpioWrite(spi.pins.clk, 0); + spiPause(); } return in; } -static void spiSingleTx(struct ff_spi *spi, uint8_t out) { - spi_set_state(spi, SS_SINGLE); - spiXfer(spi, out); +static void spiSingleTx(uint8_t out) { + spi_set_state(SS_SINGLE); + spiXfer(out); } -static uint8_t spiSingleRx(struct ff_spi *spi) { - spi_set_state(spi, SS_SINGLE); - return spiXfer(spi, 0xff); +static uint8_t spiSingleRx(void) { + spi_set_state(SS_SINGLE); + return spiXfer(0xff); } -static void spiDualTx(struct ff_spi *spi, uint8_t out) { - +static void spiQuadTx(uint8_t out) { int bit; - spi_set_state(spi, SS_DUAL_TX); - for (bit = 7; bit >= 0; bit -= 2) { - if (out & (1 << (bit - 1))) { - gpioWrite(spi->pins.d0, 1); - } - else { - gpioWrite(spi->pins.d0, 0); - } - - if (out & (1 << (bit - 0))) { - gpioWrite(spi->pins.d1, 1); - } - else { - gpioWrite(spi->pins.d1, 0); - } - gpioWrite(spi->pins.clk, 1); - spiPause(spi); - gpioWrite(spi->pins.clk, 0); - spiPause(spi); - } -} - -static void spiQuadTx(struct ff_spi *spi, uint8_t out) { - int bit; - spi_set_state(spi, SS_QUAD_TX); + spi_set_state(SS_QUAD_TX); for (bit = 7; bit >= 0; bit -= 4) { if (out & (1 << (bit - 3))) { - gpioWrite(spi->pins.d0, 1); + gpioWrite(spi.pins.d0, 1); } else { - gpioWrite(spi->pins.d0, 0); + gpioWrite(spi.pins.d0, 0); } if (out & (1 << (bit - 2))) { - gpioWrite(spi->pins.d1, 1); + gpioWrite(spi.pins.d1, 1); } else { - gpioWrite(spi->pins.d1, 0); + gpioWrite(spi.pins.d1, 0); } if (out & (1 << (bit - 1))) { - gpioWrite(spi->pins.d2, 1); + gpioWrite(spi.pins.d2, 1); } else { - gpioWrite(spi->pins.d2, 0); + gpioWrite(spi.pins.d2, 0); } if (out & (1 << (bit - 0))) { - gpioWrite(spi->pins.d3, 1); + gpioWrite(spi.pins.d3, 1); } else { - gpioWrite(spi->pins.d3, 0); + gpioWrite(spi.pins.d3, 0); } - gpioWrite(spi->pins.clk, 1); - spiPause(spi); - gpioWrite(spi->pins.clk, 0); - spiPause(spi); + gpioWrite(spi.pins.clk, 1); + spiPause(); + gpioWrite(spi.pins.clk, 0); + spiPause(); } } -static uint8_t spiDualRx(struct ff_spi *spi) { +static uint8_t spiQuadRx(void) { int bit; uint8_t in = 0; - spi_set_state(spi, SS_QUAD_RX); - for (bit = 7; bit >= 0; bit -= 2) { - gpioWrite(spi->pins.clk, 1); - spiPause(spi); - in |= ((!!gpioRead(spi->pins.d0)) << (bit - 1)); - in |= ((!!gpioRead(spi->pins.d1)) << (bit - 0)); - gpioWrite(spi->pins.clk, 0); - spiPause(spi); - } - return in; -} - -static uint8_t spiQuadRx(struct ff_spi *spi) { - int bit; - uint8_t in = 0; - - spi_set_state(spi, SS_QUAD_RX); + spi_set_state(SS_QUAD_RX); for (bit = 7; bit >= 0; bit -= 4) { - gpioWrite(spi->pins.clk, 1); - spiPause(spi); - in |= ((!!gpioRead(spi->pins.d0)) << (bit - 3)); - in |= ((!!gpioRead(spi->pins.d1)) << (bit - 2)); - in |= ((!!gpioRead(spi->pins.d2)) << (bit - 1)); - in |= ((!!gpioRead(spi->pins.d3)) << (bit - 0)); - gpioWrite(spi->pins.clk, 0); - spiPause(spi); + gpioWrite(spi.pins.clk, 1); + spiPause(); + in |= ((!!gpioRead(spi.pins.d0)) << (bit - 3)); + in |= ((!!gpioRead(spi.pins.d1)) << (bit - 2)); + in |= ((!!gpioRead(spi.pins.d2)) << (bit - 1)); + in |= ((!!gpioRead(spi.pins.d3)) << (bit - 0)); + gpioWrite(spi.pins.clk, 0); + spiPause(); } return in; } -int spiTx(struct ff_spi *spi, uint8_t word) { - switch (spi->type) { +int spiTx(uint8_t word) { + switch (spi.type) { case ST_SINGLE: - spiSingleTx(spi, word); - break; - case ST_DUAL: - spiDualTx(spi, word); + spiSingleTx(word); break; case ST_QUAD: case ST_QPI: - spiQuadTx(spi, word); + spiQuadTx(word); break; default: return -1; @@ -319,190 +254,180 @@ int spiTx(struct ff_spi *spi, uint8_t word) { return 0; } -uint8_t spiRx(struct ff_spi *spi) { - switch (spi->type) { +uint8_t spiRx(void) { + switch (spi.type) { case ST_SINGLE: - return spiSingleRx(spi); - case ST_DUAL: - return spiDualRx(spi); + return spiSingleRx(); case ST_QUAD: case ST_QPI: - return spiQuadRx(spi); + return spiQuadRx(); default: return 0xff; } } -void spiCommand(struct ff_spi *spi, uint8_t cmd) { - if (spi->type == ST_QPI) - spiQuadTx(spi, cmd); +void spiCommand(uint8_t cmd) { + if (spi.type == ST_QPI) + spiQuadTx(cmd); else - spiSingleTx(spi, cmd); + spiSingleTx(cmd); } -uint8_t spiCommandRx(struct ff_spi *spi) { - if (spi->type == ST_QPI) - return spiQuadRx(spi); +uint8_t spiCommandRx(void) { + if (spi.type == ST_QPI) + return spiQuadRx(); else - return spiSingleRx(spi); + return spiSingleRx(); } -uint8_t spiReadStatus(struct ff_spi *spi, uint8_t sr) { +uint8_t spiReadStatus(uint8_t sr) { uint8_t val = 0xff; (void)sr; -#if 0 switch (sr) { case 1: -#endif - spiBegin(spi); - spiCommand(spi, 0x05); - val = spiCommandRx(spi); - spiEnd(spi); -#if 0 - break; - case 2: - spiBegin(spi); - spiCommand(spi, 0x35); - val = spiCommandRx(spi); - spiEnd(spi); + spiBegin(); + spiCommand(0x05); + val = spiCommandRx(); + if (sr == 2) + val = spiCommandRx(); + spiEnd(); break; case 3: - spiBegin(spi); - spiCommand(spi, 0x15); - val = spiCommandRx(spi); - spiEnd(spi); + spiBegin(); + spiCommand(0x15); + val = spiCommandRx(); + spiEnd(); break; default: fprintf(stderr, "unrecognized status register: %d\n", sr); break; } -#endif return val; } -void spiWriteSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]) { +void spiWriteSecurity(uint8_t sr, uint8_t security[256]) { - if (spi->quirks & SQ_SECURITY_NYBBLE_SHIFT) + if (spi.quirks & SQ_SECURITY_NYBBLE_SHIFT) sr <<= 4; - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + spiBegin(); + spiCommand(0x06); + spiEnd(); // erase the register - spiBegin(spi); - spiCommand(spi, 0x44); - spiCommand(spi, 0x00); // A23-16 - spiCommand(spi, sr); // A15-8 - spiCommand(spi, 0x00); // A0-7 - spiEnd(spi); + spiBegin(); + spiCommand(0x44); + spiCommand(0x00); // A23-16 + spiCommand(sr); // A15-8 + spiCommand(0x00); // A0-7 + spiEnd(); - spi_get_id(spi); + spi_get_id(); sleep(1); // write enable - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + spiBegin(); + spiCommand(0x06); + spiEnd(); - spiBegin(spi); - spiCommand(spi, 0x42); - spiCommand(spi, 0x00); // A23-16 - spiCommand(spi, sr); // A15-8 - spiCommand(spi, 0x00); // A0-7 + spiBegin(); + spiCommand(0x42); + spiCommand(0x00); // A23-16 + spiCommand(sr); // A15-8 + spiCommand(0x00); // A0-7 int i; for (i = 0; i < 256; i++) - spiCommand(spi, security[i]); - spiEnd(spi); + spiCommand(security[i]); + spiEnd(); - spi_get_id(spi); + spi_get_id(); } -void spiReadSecurity(struct ff_spi *spi, uint8_t sr, uint8_t security[256]) { - if (spi->quirks & SQ_SECURITY_NYBBLE_SHIFT) +void spiReadSecurity(uint8_t sr, uint8_t security[256]) { + if (spi.quirks & SQ_SECURITY_NYBBLE_SHIFT) sr <<= 4; - spiBegin(spi); - spiCommand(spi, 0x48); // Read security registers - spiCommand(spi, 0x00); // A23-16 - spiCommand(spi, sr); // A15-8 - spiCommand(spi, 0x00); // A0-7 + spiBegin(); + spiCommand(0x48); // Read security registers + spiCommand(0x00); // A23-16 + spiCommand(sr); // A15-8 + spiCommand(0x00); // A0-7 int i; for (i = 0; i < 256; i++) - security[i] = spiCommandRx(spi); - spiEnd(spi); + security[i] = spiCommandRx(); + spiEnd(); } -void spiWriteStatus(struct ff_spi *spi, uint8_t sr, uint8_t val) { +void spiWriteStatus(uint8_t sr, uint8_t val) { switch (sr) { case 1: - if (!(spi->quirks & SQ_SKIP_SR_WEL)) { - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + if (!(spi.quirks & SQ_SKIP_SR_WEL)) { + spiBegin(); + spiCommand(0x06); + spiEnd(); } - spiBegin(spi); - spiCommand(spi, 0x50); - spiEnd(spi); + spiBegin(); + spiCommand(0x50); + spiEnd(); - spiBegin(spi); - spiCommand(spi, 0x01); - spiCommand(spi, val); - spiEnd(spi); + spiBegin(); + spiCommand(0x01); + spiCommand(val); + spiEnd(); break; case 2: { uint8_t sr1 = 0x00; - if (spi->quirks & SQ_SR2_FROM_SR1) - sr1 = spiReadStatus(spi, 1); + if (spi.quirks & SQ_SR2_FROM_SR1) + sr1 = spiReadStatus(1); - if (!(spi->quirks & SQ_SKIP_SR_WEL)) { - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + if (!(spi.quirks & SQ_SKIP_SR_WEL)) { + spiBegin(); + spiCommand(0x06); + spiEnd(); } - spiBegin(spi); - spiCommand(spi, 0x50); - spiEnd(spi); + spiBegin(); + spiCommand(0x50); + spiEnd(); - spiBegin(spi); - if (spi->quirks & SQ_SR2_FROM_SR1) { - spiCommand(spi, 0x01); - spiCommand(spi, sr1); - spiCommand(spi, val); + spiBegin(); + if (spi.quirks & SQ_SR2_FROM_SR1) { + spiCommand(0x01); + spiCommand(sr1); + spiCommand(val); } else { - spiCommand(spi, 0x31); - spiCommand(spi, val); + spiCommand(0x31); + spiCommand(val); } - spiEnd(spi); + spiEnd(); break; } case 3: - if (!(spi->quirks & SQ_SKIP_SR_WEL)) { - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + if (!(spi.quirks & SQ_SKIP_SR_WEL)) { + spiBegin(); + spiCommand(0x06); + spiEnd(); } - spiBegin(spi); - spiCommand(spi, 0x50); - spiEnd(spi); + spiBegin(); + spiCommand(0x50); + spiEnd(); - spiBegin(spi); - spiCommand(spi, 0x11); - spiCommand(spi, val); - spiEnd(spi); + spiBegin(); + spiCommand(0x11); + spiCommand(val); + spiEnd(); break; default: @@ -511,311 +436,387 @@ void spiWriteStatus(struct ff_spi *spi, uint8_t sr, uint8_t val) { } } -#if 0 -struct spi_id spiId(struct ff_spi *spi) { - return spi->id; +struct spi_id spiId(void) { + return spi.id; } -static void spi_decode_id(struct ff_spi *spi) { - spi->id.bytes = -1; // unknown +#if 0 +static void spi_decode_id(void) { + spi.id.bytes = -1; // unknown + spi.id.manufacturer = "Unknown"; + spi.id.model = "Unknown"; + spi.id.capacity = "Unknown"; - if (spi->id.manufacturer_id == 0xef) { - // spi->id.manufacturer = "Winbond"; - if ((spi->id.memory_type == 0x70) - && (spi->id.memory_size == 0x18)) { - // spi->id.model = "W25Q128JV"; - // spi->id.capacity = "128 Mbit"; - spi->id.bytes = 16 * 1024 * 1024; + if (spi.id.manufacturer_id == 0xef) { + spi.id.manufacturer = "Winbond"; + if ((spi.id.memory_type == 0x70) + && (spi.id.memory_size == 0x18)) { + spi.id.model = "W25Q128JV"; + spi.id.capacity = "128 Mbit"; + spi.id.bytes = 16 * 1024 * 1024; } } - if (spi->id.manufacturer_id == 0x1f) { - // spi->id.manufacturer = "Adesto"; - if ((spi->id.memory_type == 0x86) - && (spi->id.memory_size == 0x01)) { - // spi->id.model = "AT25SF161"; - // spi->id.capacity = "16 Mbit"; - spi->id.bytes = 1 * 1024 * 1024; + if (spi.id.manufacturer_id == 0x1f) { + spi.id.manufacturer = "Adesto"; + if ((spi.id.memory_type == 0x86) + && (spi.id.memory_size == 0x01)) { + spi.id.model = "AT25SF161"; + spi.id.capacity = "16 Mbit"; + spi.id.bytes = 1 * 1024 * 1024; } } return; } #endif -static void spi_get_id(struct ff_spi *spi) { - spiBegin(spi); - spiCommand(spi, 0x90); // Read manufacturer ID - spiCommand(spi, 0x00); // Dummy byte 1 - spiCommand(spi, 0x00); // Dummy byte 2 - spiCommand(spi, 0x00); // Dummy byte 3 - spi->id.manufacturer_id = spiCommandRx(spi); - spi->id.device_id = spiCommandRx(spi); - spiEnd(spi); + +static void spi_get_id(void) { + + spiBegin(); + spiCommand(0x90); // Read manufacturer ID + spiCommand(0x00); // Dummy byte 1 + spiCommand(0x00); // Dummy byte 2 + spiCommand(0x00); // Dummy byte 3 + spi.id.manufacturer_id = spiCommandRx(); + spi.id.device_id = spiCommandRx(); + spiEnd(); + + spiBegin(); + spiCommand(0x9f); // Read device id + spi.id._manufacturer_id = spiCommandRx(); + spi.id.memory_type = spiCommandRx(); + spi.id.memory_size = spiCommandRx(); + spiEnd(); + + spiBegin(); + spiCommand(0xab); // Read electronic signature + spiCommand(0x00); // Dummy byte 1 + spiCommand(0x00); // Dummy byte 2 + spiCommand(0x00); // Dummy byte 3 + spi.id.signature = spiCommandRx(); + spiEnd(); + + spiBegin(); + spiCommand(0x4b); // Read unique ID + spiCommand(0x00); // Dummy byte 1 + spiCommand(0x00); // Dummy byte 2 + spiCommand(0x00); // Dummy byte 3 + spiCommand(0x00); // Dummy byte 4 + spi.id.serial[0] = spiCommandRx(); + spi.id.serial[1] = spiCommandRx(); + spi.id.serial[2] = spiCommandRx(); + spi.id.serial[3] = spiCommandRx(); + spiEnd(); + + // spi_decode_id(); return; -#if 0 - spiBegin(spi); - spiCommand(spi, 0x9f); // Read device id - spi->id._manufacturer_id = spiCommandRx(spi); - spi->id.memory_type = spiCommandRx(spi); - spi->id.memory_size = spiCommandRx(spi); - spiEnd(spi); - - spiBegin(spi); - spiCommand(spi, 0xab); // Read electronic signature - spiCommand(spi, 0x00); // Dummy byte 1 - spiCommand(spi, 0x00); // Dummy byte 2 - spiCommand(spi, 0x00); // Dummy byte 3 - spi->id.signature = spiCommandRx(spi); - spiEnd(spi); - - spiBegin(spi); - spiCommand(spi, 0x4b); // Read unique ID - spiCommand(spi, 0x00); // Dummy byte 1 - spiCommand(spi, 0x00); // Dummy byte 2 - spiCommand(spi, 0x00); // Dummy byte 3 - spiCommand(spi, 0x00); // Dummy byte 4 - spi->id.serial[0] = spiCommandRx(spi); - spi->id.serial[1] = spiCommandRx(spi); - spi->id.serial[2] = spiCommandRx(spi); - spi->id.serial[3] = spiCommandRx(spi); - spiEnd(spi); - - spi_decode_id(spi); - return; -#endif } #if 0 -void spiOverrideSize(struct ff_spi *spi, uint32_t size) { - spi->size_override = size; +void spiOverrideSize(uint32_t size) { + spi.size_override = size; // If size is 0, re-read the capacity if (!size) - spi_decode_id(spi); + spi_decode_id(); else - spi->id.bytes = size; + spi.id.bytes = size; } #endif -int spiSetType(struct ff_spi *spi, enum spi_type type) { +int spiSetType(enum spi_type type) { - if (spi->type == type) + if (spi.type == type) return 0; -#ifndef SPI_ONLY_SINGLE switch (type) { case ST_SINGLE: -#endif - if (spi->type == ST_QPI) { - spiBegin(spi); - spiCommand(spi, 0xff); // Exit QPI Mode - spiEnd(spi); + if (spi.type == ST_QPI) { + spiBegin(); + spiCommand(0xff); // Exit QPI Mode + spiEnd(); } - spi->type = type; - spi_set_state(spi, SS_SINGLE); -#ifndef SPI_ONLY_SINGLE - break; - - case ST_DUAL: - if (spi->type == ST_QPI) { - spiBegin(spi); - spiCommand(spi, 0xff); // Exit QPI Mode - spiEnd(spi); - } - spi->type = type; - spi_set_state(spi, SS_DUAL_TX); + spi.type = type; + spi_set_state(SS_SINGLE); break; case ST_QUAD: - if (spi->type == ST_QPI) { - spiBegin(spi); - spiCommand(spi, 0xff); // Exit QPI Mode - spiEnd(spi); + if (spi.type == ST_QPI) { + spiBegin(); + spiCommand(0xff); // Exit QPI Mode + spiEnd(); } // Enable QE bit - spiWriteStatus(spi, 2, spiReadStatus(spi, 2) | (1 << 1)); + spiWriteStatus(2, spiReadStatus(2) | (1 << 1)); - spi->type = type; - spi_set_state(spi, SS_QUAD_TX); + spi.type = type; + spi_set_state(SS_QUAD_TX); break; case ST_QPI: // Enable QE bit - spiWriteStatus(spi, 2, spiReadStatus(spi, 2) | (1 << 1)); + spiWriteStatus(2, spiReadStatus(2) | (1 << 1)); - spiBegin(spi); - spiCommand(spi, 0x38); // Enter QPI Mode - spiEnd(spi); - spi->type = type; - spi_set_state(spi, SS_QUAD_TX); + spiBegin(); + spiCommand(0x38); // Enter QPI Mode + spiEnd(); + spi.type = type; + spi_set_state(SS_QUAD_TX); break; default: - fprintf(stderr, "Unrecognized SPI type: %d\n", type); return 1; } -#endif return 0; } -int spiIsBusy(struct ff_spi *spi) { - return spiReadStatus(spi, 1) & (1 << 0); +int spiIsBusy(void) { + return spiReadStatus(1) & (1 << 0); } -int spiBeginErase32(struct ff_spi *spi, uint32_t erase_addr) { +void spi_wait_for_not_busy(void) { + while (spiIsBusy()) + ; +} + +int spiBeginErase32(uint32_t erase_addr) { // Enable Write-Enable Latch (WEL) - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + spiBegin(); + spiCommand(0x06); + spiEnd(); - spiBegin(spi); - spiCommand(spi, 0x52); - spiCommand(spi, erase_addr >> 16); - spiCommand(spi, erase_addr >> 8); - spiCommand(spi, erase_addr >> 0); - spiEnd(spi); + spiBegin(); + spiCommand(0x52); + spiCommand(erase_addr >> 16); + spiCommand(erase_addr >> 8); + spiCommand(erase_addr >> 0); + spiEnd(); return 0; } -int spiBeginErase64(struct ff_spi *spi, uint32_t erase_addr) { +int spiBeginErase64(uint32_t erase_addr) { // Enable Write-Enable Latch (WEL) - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + spiBegin(); + spiCommand(0x06); + spiEnd(); - spiBegin(spi); - spiCommand(spi, 0xD8); - spiCommand(spi, erase_addr >> 16); - spiCommand(spi, erase_addr >> 8); - spiCommand(spi, erase_addr >> 0); - spiEnd(spi); + spiBegin(); + spiCommand(0xD8); + spiCommand(erase_addr >> 16); + spiCommand(erase_addr >> 8); + spiCommand(erase_addr >> 0); + spiEnd(); return 0; } -int spiBeginWrite(struct ff_spi *spi, uint32_t addr, const void *v_data, unsigned int count) { +int spiBeginWrite(uint32_t addr, const void *v_data, unsigned int count) { const uint8_t write_cmd = 0x02; const uint8_t *data = v_data; unsigned int i; // Enable Write-Enable Latch (WEL) - spiBegin(spi); - spiCommand(spi, 0x06); - spiEnd(spi); + spiBegin(); + spiCommand(0x06); + spiEnd(); - // uint8_t sr1 = spiReadStatus(spi, 1); + // uint8_t sr1 = spiReadStatus(1); // if (!(sr1 & (1 << 1))) // fprintf(stderr, "error: write-enable latch (WEL) not set, write will probably fail\n"); - spiBegin(spi); - spiCommand(spi, write_cmd); - spiCommand(spi, addr >> 16); - spiCommand(spi, addr >> 8); - spiCommand(spi, addr >> 0); + spiBegin(); + spiCommand(write_cmd); + spiCommand(addr >> 16); + spiCommand(addr >> 8); + spiCommand(addr >> 0); for (i = 0; (i < count) && (i < 256); i++) - spiTx(spi, *data++); - spiEnd(spi); + spiTx(*data++); + spiEnd(); return 0; } -uint8_t spiReset(struct ff_spi *spi) { +uint8_t spiReset(void) { // XXX You should check the "Ready" bit before doing this! // Shift to QPI mode, then back to Single mode, to ensure // we're actually in Single mode. - spiSetType(spi, ST_QPI); - spiSetType(spi, ST_SINGLE); + spiSetType(ST_QPI); + spiSetType(ST_SINGLE); - spiBegin(spi); - spiCommand(spi, 0x66); // "Enable Reset" command - spiEnd(spi); + spiBegin(); + spiCommand(0x66); // "Enable Reset" command + spiEnd(); - spiBegin(spi); - spiCommand(spi, 0x99); // "Reset Device" command - spiEnd(spi); + spiBegin(); + spiCommand(0x99); // "Reset Device" command + spiEnd(); // msleep(30); - spiBegin(spi); - spiCommand(spi, 0xab); // "Resume from Deep Power-Down" command - spiEnd(spi); + spiBegin(); + spiCommand(0xab); // "Resume from Deep Power-Down" command + spiEnd(); return 0; } -int spiInit(struct ff_spi *spi) { - spi->state = SS_UNCONFIGURED; - spi->type = ST_UNCONFIGURED; +int spi_init(void) { + spi.state = SS_UNCONFIGURED; + spi.type = ST_UNCONFIGURED; + + int i; + for (i = 0; i < 6; i++) + ((uint32_t *)&spi.pins)[i] = i; // Disable memory-mapped mode and enable bit-bang mode picorvspi_cfg4_write(0); // Reset the SPI flash, which will return it to SPI mode even // if it's in QPI mode. - spiReset(spi); + spiReset(); - spiSetType(spi, ST_SINGLE); + spiSetType(ST_SINGLE); // Have the SPI flash pay attention to us - gpioWrite(spi->pins.hold, 1); + gpioWrite(spi.pins.hold, 1); // Disable WP - gpioWrite(spi->pins.wp, 1); + gpioWrite(spi.pins.wp, 1); - gpioSetMode(spi->pins.clk, PI_OUTPUT); // CLK - gpioSetMode(spi->pins.cs, PI_OUTPUT); // CE0# - gpioSetMode(spi->pins.mosi, PI_OUTPUT); // MOSI - gpioSetMode(spi->pins.miso, PI_INPUT); // MISO - gpioSetMode(spi->pins.hold, PI_OUTPUT); - gpioSetMode(spi->pins.wp, PI_OUTPUT); + gpioSetMode(spi.pins.clk, PI_OUTPUT); // CLK + gpioSetMode(spi.pins.cs, PI_OUTPUT); // CE0# + gpioSetMode(spi.pins.mosi, PI_OUTPUT); // MOSI + gpioSetMode(spi.pins.miso, PI_INPUT); // MISO + gpioSetMode(spi.pins.hold, PI_OUTPUT); + gpioSetMode(spi.pins.wp, PI_OUTPUT); - spi_get_id(spi); + spi_get_id(); - spi->quirks |= SQ_SR2_FROM_SR1; - if (spi->id.manufacturer_id == 0xef) - spi->quirks |= SQ_SKIP_SR_WEL | SQ_SECURITY_NYBBLE_SHIFT; + spi.quirks |= SQ_SR2_FROM_SR1; + if (spi.id.manufacturer_id == 0xef) + spi.quirks |= SQ_SKIP_SR_WEL | SQ_SECURITY_NYBBLE_SHIFT; return 0; } void spiEnableQuad(void) { - struct ff_spi *spi = spiAlloc(); - spiInit(spi); - spiWriteStatus(spi, 2, spiReadStatus(spi, 2) | (1 << 1)); - spiFree(); + spiWriteStatus(2, spiReadStatus(2) | (1 << 1)); } -struct ff_spi *spiAlloc(void) { - static struct ff_spi spi; - return &spi; -} - -void spiSetPin(struct ff_spi *spi, enum spi_pin pin, int val) { +void spiSetPin(enum spi_pin pin, int val) { switch (pin) { - case SP_MOSI: spi->pins.mosi = val; break; - case SP_MISO: spi->pins.miso = val; break; - case SP_HOLD: spi->pins.hold = val; break; - case SP_WP: spi->pins.wp = val; break; - case SP_CS: spi->pins.cs = val; break; - case SP_CLK: spi->pins.clk = val; break; - case SP_D0: spi->pins.d0 = val; break; - case SP_D1: spi->pins.d1 = val; break; - case SP_D2: spi->pins.d2 = val; break; - case SP_D3: spi->pins.d3 = val; break; - default: fprintf(stderr, "unrecognized pin: %d\n", pin); break; + case SP_MOSI: spi.pins.mosi = val; break; + case SP_MISO: spi.pins.miso = val; break; + case SP_HOLD: spi.pins.hold = val; break; + case SP_WP: spi.pins.wp = val; break; + case SP_CS: spi.pins.cs = val; break; + case SP_CLK: spi.pins.clk = val; break; + case SP_D0: spi.pins.d0 = val; break; + case SP_D1: spi.pins.d1 = val; break; + case SP_D2: spi.pins.d2 = val; break; + case SP_D3: spi.pins.d3 = val; break; } } -void spiHold(struct ff_spi *spi) { - spiBegin(spi); - spiCommand(spi, 0xb9); - spiEnd(spi); +void spiHold(void) { + spiBegin(); + spiCommand(0xb9); + spiEnd(); } -void spiUnhold(struct ff_spi *spi) { - spiBegin(spi); - spiCommand(spi, 0xab); - spiEnd(spi); + +void spiUnhold(void) { + spiBegin(); + spiCommand(0xab); + spiEnd(); +} + +int spiWrite(uint32_t addr, const uint8_t *data, unsigned int count) { + + unsigned int i; + + if (addr & 0xff) { + return 1; + } + + // Erase all applicable blocks + uint32_t erase_addr; + for (erase_addr = 0; erase_addr < count; erase_addr += 32768) { + spiBegin(); + spiCommand(0x06); + spiEnd(); + + spiBegin(); + spiCommand(0x52); + spiCommand(erase_addr >> 16); + spiCommand(erase_addr >> 8); + spiCommand(erase_addr >> 0); + spiEnd(); + + spi_wait_for_not_busy(); + } + + uint8_t write_cmd; + switch (spi.type) { + case ST_SINGLE: + case ST_QPI: + write_cmd = 0x02; + break; + case ST_QUAD: + write_cmd = 0x32; + break; + default: + return 1; + } + + while (count) { + spiBegin(); + spiCommand(0x06); + spiEnd(); + + spiBegin(); + spiCommand(write_cmd); + spiCommand(addr >> 16); + spiCommand(addr >> 8); + spiCommand(addr >> 0); + for (i = 0; (i < count) && (i < 256); i++) + spiTx(*data++); + spiEnd(); + count -= i; + addr += i; + spi_wait_for_not_busy(); + } + return 0; +} + +int spiRead(uint32_t addr, uint8_t *data, unsigned int count) { + + unsigned int i; + + spiBegin(); + switch (spi.type) { + case ST_SINGLE: + case ST_QPI: + spiCommand(0x0b); + break; + case ST_QUAD: + spiCommand(0x6b); + break; + default: + spiEnd(); + return 1; + } + spiCommand(addr >> 16); + spiCommand(addr >> 8); + spiCommand(addr >> 0); + spiCommand(0x00); + for (i = 0; i < count; i++) { + data[i] = spiRx(); + } + + spiEnd(); + return 0; } void spiFree(void) { diff --git a/sw/src/tester.c b/sw/src/tester.c index 5acae18..8f00158 100644 --- a/sw/src/tester.c +++ b/sw/src/tester.c @@ -1,7 +1,68 @@ #include #include +#include +#include +#include +#include +#include -void tester_poll(void) { - printf("Hello, world!\n"); - return; +int test_spi(void) +{ + uint8_t test_buffer[64]; + uint8_t compare_buffer[sizeof(test_buffer)]; + unsigned int i; + int errors = 0; + + struct spi_id id = spiId(); + spiSetType(ST_QUAD); + // printf("SPI Manufacturer: %02x\n", id.manufacturer_id); + // printf("SPI Device ID: %02x\n", id.device_id); + // printf("SPI Capacity: %02x %02x\n", id.memory_type, id.memory_size); + + for (i = 0; i < sizeof(test_buffer); i++) { + test_buffer[i] = (i^0x9d) ^ (i<<5); + } + spiWrite(0, test_buffer, sizeof(test_buffer)-1); + + for (i = 0; i < sizeof(compare_buffer); i++) { + compare_buffer[i] = 0; + } + spiRead(0, compare_buffer, sizeof(compare_buffer)); + + for (i = 0; i < sizeof(compare_buffer); i++) { + if (test_buffer[i] != compare_buffer[i]) { + // printf("SPI: Offset %d Expected %02x Got %02x\n", i, test_buffer[i], compare_buffer[i]); + errors++; + } + } + + return errors; +} + +int test_led(void) { + uint32_t pulses_per_second; + touch_oe_write(touch_oe_read() & ~(1 << 1)); + // touch_oe_write(touch_oe_read() | (1 << 1)); + // touch_o_write(touch_o_read() & ~(1 << 1)); + rgb_bypass_write(1); + rgb_mode_off(); + rgb_pwm_count_write(SYSTEM_CLOCK_FREQUENCY/1000*125); + printf("Blinking: "); + msleep(1000); + pulses_per_second = rgb_pwm_count_read(); + rgb_pwm_count_write(SYSTEM_CLOCK_FREQUENCY/1000*125); + printf("%08x / %08x / %08x\n", pulses_per_second, rgb_sent_pulses_read(), rgb_detected_pulses_read()); + return 0; +} + +void tester_poll(void) +{ + int error_count = 0; + printf("\nHello, world!\n"); + // error_count = test_spi(); + // printf("SPI errors: %d\n", error_count); + while (1) { + usb_poll(); + test_led(); + } } \ No newline at end of file diff --git a/sw/src/usb-cdc.c b/sw/src/usb-cdc.c index 61972f0..1722038 100644 --- a/sw/src/usb-cdc.c +++ b/sw/src/usb-cdc.c @@ -16,6 +16,9 @@ void cdc_set_connected(int is_connected) void _putchar(char character) { + if (character == '\n') + _putchar('\r'); + // Wait for buffer to be empty while (usb_ep_2_in_respond_read() == EPF_ACK) ; diff --git a/sw/src/usb-desc.c b/sw/src/usb-desc.c index bebde8a..20a3d34 100644 --- a/sw/src/usb-desc.c +++ b/sw/src/usb-desc.c @@ -60,7 +60,7 @@ static const uint8_t device_descriptor[] = { 18, // bLength 1, // bDescriptorType - 0x01, 0x02, // bcdUSB + 0x10, 0x01, // bcdUSB USB_CLASS_CDC, // bDeviceClass 0x00, // bDeviceSubClass 0x00, // bDeviceProtocol diff --git a/sw/src/usb-epfifo.c b/sw/src/usb-epfifo.c index 989c2e6..2168886 100644 --- a/sw/src/usb-epfifo.c +++ b/sw/src/usb-epfifo.c @@ -11,11 +11,12 @@ static const int max_byte_length = 64; #define EP2OUT_BUFFERS 4 __attribute__((aligned(4))) #define EP0OUT_BUFFER_SIZE 256 -static uint8_t volatile usb_ep0out_buffer_len[EP0OUT_BUFFERS]; -static uint8_t volatile usb_ep0out_buffer[EP0OUT_BUFFERS][EP0OUT_BUFFER_SIZE]; -static uint8_t volatile usb_ep0out_last_tok[EP0OUT_BUFFERS]; -static volatile uint8_t usb_ep0out_wr_ptr; -static volatile uint8_t usb_ep0out_rd_ptr; +// static uint8_t volatile usb_ep0out_buffer_len[EP0OUT_BUFFERS]; +static uint8_t volatile usb_ep0out_buffer[EP0OUT_BUFFER_SIZE]; +static int wait_reply; +static int wait_type; +// static volatile uint8_t usb_ep0out_wr_ptr; +// static volatile uint8_t usb_ep0out_rd_ptr; #define EP2OUT_BUFFER_SIZE 256 static uint8_t volatile usb_ep2out_buffer_len[EP2OUT_BUFFERS]; @@ -76,8 +77,8 @@ void usb_connect(void) { } void usb_init(void) { - usb_ep0out_wr_ptr = 0; - usb_ep0out_rd_ptr = 0; + // usb_ep0out_wr_ptr = 0; + // usb_ep0out_rd_ptr = 0; usb_pullup_out_write(0); return; } @@ -133,8 +134,7 @@ static void process_tx(void) { } void usb_send(const void *data, int total_count) { - - while ((current_length || current_data))// && usb_ep_0_in_respond_read() != EPF_NAK) + while ((current_length || current_data) && (usb_ep_0_in_respond_read() != EPF_NAK)) ; current_data = (uint8_t *)data; current_length = total_count; @@ -157,34 +157,21 @@ void usb_isr(void) { uint8_t ep2in_pending = usb_ep_2_in_ev_pending_read(); uint8_t ep2out_pending = usb_ep_2_out_ev_pending_read(); - // We got an OUT or a SETUP packet. Copy it to usb_ep0out_buffer - // and clear the "pending" bit. - if (ep0out_pending) { - uint8_t last_tok = usb_ep_0_out_last_tok_read(); - - int byte_count = 0; - usb_ep0out_last_tok[usb_ep0out_wr_ptr] = last_tok; - volatile uint8_t * obuf = usb_ep0out_buffer[usb_ep0out_wr_ptr]; - while (!usb_ep_0_out_obuf_empty_read()) { - obuf[byte_count++] = usb_ep_0_out_obuf_head_read(); - usb_ep_0_out_obuf_head_write(0); - } - if (byte_count >= 2) - usb_ep0out_buffer_len[usb_ep0out_wr_ptr] = byte_count - 2 /* Strip off CRC16 */; - usb_ep0out_wr_ptr = (usb_ep0out_wr_ptr + 1) & (EP0OUT_BUFFERS-1); - - if (last_tok == USB_PID_SETUP) { - usb_ep_0_in_dtb_write(1); - data_offset = 0; - current_length = 0; - current_data = NULL; - } - usb_ep_0_out_ev_pending_write(ep0out_pending); - usb_ep_0_out_respond_write(EPF_ACK); - } - // We just got an "IN" token. Send data if we have it. if (ep0in_pending) { + if (wait_reply == 2) { + wait_reply--; + if (!wait_type) { + wait_type = 1; + } + } + else if (wait_reply == 1) { + if (wait_type == 2) { + current_data = NULL; + current_length = 0; + } + wait_type = 0; + } usb_ep_0_in_respond_write(EPF_NAK); usb_ep_0_in_ev_pending_write(ep0in_pending); } @@ -200,8 +187,17 @@ void usb_isr(void) { } if (ep2out_pending) { +#ifdef LOOPBACK_TEST volatile uint8_t * obuf = usb_ep2out_buffer[usb_ep2out_wr_ptr]; int sz = 0; + + if (wait_reply == 2) { + wait_reply--; + wait_type = 2; + } + else if (wait_reply == 1) { + wait_reply--; + } while (!usb_ep_2_out_obuf_empty_read()) { if (sz < EP2OUT_BUFFER_SIZE) obuf[sz++] = usb_ep_2_out_obuf_head_read() + 1; @@ -211,12 +207,40 @@ void usb_isr(void) { usb_ep2out_buffer_len[usb_ep2out_wr_ptr] = sz - 2; /* Strip off CRC16 */ usb_ep2out_wr_ptr = (usb_ep2out_wr_ptr + 1) & (EP2OUT_BUFFERS-1); } - +#else // !LOOPBACK_TEST + while (!usb_ep_2_out_obuf_empty_read()) { + usb_ep_2_out_obuf_head_write(0); + } +#endif usb_ep_2_out_respond_write(EPF_ACK); usb_ep_2_out_ev_pending_write(ep2out_pending); } - return; + // We got an OUT or a SETUP packet. Copy it to usb_ep0out_buffer + // and clear the "pending" bit. + if (ep0out_pending) { + unsigned int byte_count = 0; + for (byte_count = 0; byte_count < EP0OUT_BUFFER_SIZE; byte_count++) + usb_ep0out_buffer[byte_count] = 0; + + byte_count = 0; + while (!usb_ep_0_out_obuf_empty_read()) { + usb_ep0out_buffer[byte_count++] = usb_ep_0_out_obuf_head_read(); + usb_ep_0_out_obuf_head_write(0); + } + + if (byte_count >= 2) { + usb_ep_0_in_dtb_write(1); + data_offset = 0; + current_length = 0; + current_data = NULL; + wait_reply = usb_setup((void *)usb_ep0out_buffer); + } + usb_ep_0_out_ev_pending_write(ep0out_pending); + usb_ep_0_out_respond_write(EPF_ACK); + } + + process_tx(); } void usb_ack_in(void) { @@ -236,6 +260,7 @@ void usb_err(void) { usb_ep_0_in_respond_write(EPF_STALL); } +#if 0 int usb_recv(void *buffer, unsigned int buffer_len) { // Set the OUT response to ACK, since we are in a position to receive data now. @@ -256,23 +281,25 @@ int usb_recv(void *buffer, unsigned int buffer_len) { } return 0; } +#endif void usb_poll(void) { - // If some data was received, then process it. - while (usb_ep0out_rd_ptr != usb_ep0out_wr_ptr) { - const struct usb_setup_request *request = (const struct usb_setup_request *)(usb_ep0out_buffer[usb_ep0out_rd_ptr]); - // uint8_t len = usb_ep0out_buffer_len[usb_ep0out_rd_ptr]; - uint8_t last_tok = usb_ep0out_last_tok[usb_ep0out_rd_ptr]; - - // usb_ep0out_buffer_len[usb_ep0out_rd_ptr] = 0; - usb_ep0out_rd_ptr = (usb_ep0out_rd_ptr + 1) & (EP0OUT_BUFFERS-1); - - if (last_tok == USB_PID_SETUP) { - usb_setup(request); - } - } - process_tx(); +#ifdef LOOPBACK_TEST + if (usb_ep2out_rd_ptr != usb_ep2out_wr_ptr) { + volatile uint8_t *buf = usb_ep2out_buffer[usb_ep2out_rd_ptr]; + unsigned int len = usb_ep2out_buffer_len[usb_ep2out_rd_ptr]; + unsigned int i; + while (usb_ep_2_in_respond_read() == EPF_ACK) { + ; + } + for (i = 0; i < len; i++) { + usb_ep_2_in_ibuf_head_write(buf[i]); + } + usb_ep_2_in_respond_write(EPF_ACK); + usb_ep2out_rd_ptr = (usb_ep2out_rd_ptr + 1) & (EP2OUT_BUFFERS-1); + } +#endif } #endif /* CSR_USB_EP_0_OUT_EV_PENDING_ADDR */ \ No newline at end of file diff --git a/sw/src/usb-setup.c b/sw/src/usb-setup.c index 59e76b3..96d6560 100644 --- a/sw/src/usb-setup.c +++ b/sw/src/usb-setup.c @@ -8,16 +8,30 @@ static uint8_t reply_buffer[8]; static uint8_t usb_configuration = 0; -void usb_setup(const struct usb_setup_request *setup) +int usb_setup(const struct usb_setup_request *setup) { const uint8_t *data = NULL; uint32_t datalen = 0; const usb_descriptor_list_t *list; + uint32_t max_length = setup->wLength;//((setup->wLength >> 8) & 0xff) | ((setup->wLength << 8) & 0xff00); switch (setup->wRequestAndType) { + // case 0x21a1: // Get Line Coding + // reply_buffer[0] = 0x80; + // reply_buffer[1] = 0x25; + // reply_buffer[2] = 0x00; + // reply_buffer[3] = 0x00; + // reply_buffer[4] = 0x00; + // reply_buffer[5] = 0x00; + // reply_buffer[6] = 0x08; + // data = reply_buffer; + // datalen = 7; + // break; + case 0x2021: // Set Line Coding + case 0x20A1: // Set Line Coding break; case 0x2221: // Set control line state @@ -49,7 +63,7 @@ void usb_setup(const struct usb_setup_request *setup) if (setup->wIndex > 0) { usb_err(); - return; + return 0; } reply_buffer[0] = 0; reply_buffer[1] = 0; @@ -64,7 +78,7 @@ void usb_setup(const struct usb_setup_request *setup) { // TODO: do we need to handle IN vs OUT here? usb_err(); - return; + return 0; } break; @@ -73,7 +87,7 @@ void usb_setup(const struct usb_setup_request *setup) { // TODO: do we need to handle IN vs OUT here? usb_err(); - return; + return 0; } // XXX: Should we set the stall bit? // USB->DIEP0CTL |= USB_DIEP_CTL_STALL; @@ -104,20 +118,20 @@ void usb_setup(const struct usb_setup_request *setup) } } usb_err(); - return; + return 0; default: usb_err(); - return; + return 0; } send: if (data && datalen) { - if (datalen > setup->wLength) - datalen = setup->wLength; + if (datalen > max_length) + datalen = max_length; usb_send(data, datalen); } else usb_ack_in(); - return; + return 2; }