lxbuildenv: improve ice40/nextpnr support
Signed-off-by: Sean Cross <sean@xobs.io>
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@ -178,6 +178,9 @@ def check_yosys(args):
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def check_arachne(args):
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return check_cmd(args, "arachne-pnr")
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def check_icestorm(args):
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return check_cmd(args, "icepack") and check_cmd(args, "nextpnr-ice40")
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dependency_checkers = {
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'python': check_python_version,
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'vivado': check_vivado,
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@ -185,6 +188,7 @@ dependency_checkers = {
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'riscv': check_riscv,
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'yosys': check_yosys,
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'arachne-pnr': check_arachne,
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'icestorm': check_icestorm,
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}
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# Validate that the required dependencies (Vivado, compilers, etc.)
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@ -272,6 +276,18 @@ def lx_main(args):
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elif args.lx_print_deps:
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lx_print_deps()
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elif args.lx_run is not None:
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script_name=args.lx_run[0]
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get_required_dependencies(script_name)
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fixup_env(script_path, args)
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check_submodules(script_path, args)
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try:
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sys.exit(subprocess.Popen(
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[sys.executable] + [script_name] + args.lx_run[1:]).wait())
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except:
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sys.exit(1)
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elif args.init:
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if args.main is None:
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main_name = os.getcwd().split(os.path.sep)[-1] + '.py'
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@ -361,7 +377,11 @@ import lxbuildenv
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#pylint:disable=E1101
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx import VivadoProgrammer, XilinxPlatform
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from litex.build.generic_platform import Pins, IOStandard
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from litex.soc.integration import SoCSDRAM
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import csr_map_update
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_io = [
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("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
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@ -435,6 +455,12 @@ if __name__ == "__main__":
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parser.add_argument(
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'-d', '--print-deps', '--lx-print-deps', dest="lx_print_deps", help="print all possible dependencies and then exit", action="store_true"
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)
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parser.add_argument(
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"--lx-verbose", help="increase verboseness of some processes", action="store_true"
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)
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parser.add_argument(
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'-r', '--run', '--lx-run', dest='lx_run', help="run the given script under lxbuildenv", nargs=argparse.REMAINDER
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)
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args = parser.parse_args()
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if not lx_main(args):
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