55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
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#ifndef RISCV_DEFS_H__
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#define RISCV_DEFS_H__
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#include <fomu/csr.h>
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#define CSR_MSTATUS_MIE 0x8
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#define CSR_IRQ_MASK 0xBC0
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#define CSR_IRQ_PENDING 0xFC0
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#define CSR_DCACHE_INFO 0xCC0
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#ifdef __cplusplus
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extern "C" {
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#endif
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void flush_cpu_icache(void);
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void flush_cpu_dcache(void);
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void flush_l2_cache(void);
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#define csrr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define csrw(reg, val) ({ \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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#define csrs(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
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else \
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asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
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#define csrc(reg, bit) ({ \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
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else \
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asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
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#ifdef __cplusplus
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}
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#endif
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__attribute__((noreturn)) void reboot(void);
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__attribute__((noreturn)) static inline void warmboot_to_image(uint8_t image_index) {
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reboot_ctrl_write(0xac | (image_index & 3) << 0);
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while (1);
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}
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#endif /* RISCV_DEFS_H__ */
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