Sean Cross 4c3f0f2402 valentyusb: use experimental shorter pipeline ... This helps to improve timing. Signed-off-by: Sean Cross <sean@xobs.io>		2019-04-03 22:11:02 +08:00
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bin	Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'	2019-03-05 09:05:50 +08:00
deps	valentyusb: use experimental shorter pipeline	2019-04-03 22:11:02 +08:00
2-stage-1024-cache-debug.v	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
2-stage-1024-cache-debug.yaml	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
2-stage-1024-cache.v	hw: add 2-stage-1024-cache	2019-04-03 21:57:53 +08:00
2-stage-1024-cache.yaml	hw: add 2-stage-1024-cache	2019-04-03 21:57:53 +08:00
2-stage-no-cache-debug.v	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
2-stage-no-cache-debug.yaml	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
4-stage-1024-cache-debug.v	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
4-stage-1024-cache-debug.yaml	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
4-stage-no-cache-debug.v	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
4-stage-no-cache-debug.yaml	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
5-stage-pipelined-no-cache-debug.v	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
5-stage-pipelined-no-cache-debug.yaml	wip: just need to get WARMBOOT working	2019-03-28 11:11:36 +08:00
crc5-test.c	metastable fix: wip	2019-03-05 20:28:54 +08:00
csr-test.py	Add 'hw/' from commit 'd812378c4d61f7c957ac4bcba15a8344fb7fb458'	2019-03-05 09:05:50 +08:00
foboot-bitstream.py	foboot-bitstream: fix warmboot and add rgb block	2019-04-02 18:11:58 +08:00
lxbuildenv.py	hw: lxbuildenv: fix uninitialized repo issue	2019-03-05 22:08:11 +08:00