Sean Cross
cad2ae01d7
This fixes heterodyning that was occurring in the USB block, as it transitioned from the 48 MHz down to the 12 MHz domain. Signed-off-by: Sean Cross <sean@xobs.io>
267 lines
9.4 KiB
Python
Executable File
267 lines
9.4 KiB
Python
Executable File
#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]
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# Import lxbuildenv to integrate the deps/ directory
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import lxbuildenv
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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#from migen import *
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from migen import Module, Signal, Instance, ClockDomain, If
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.lattice.platform import LatticePlatform
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from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal
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from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import csr_map_update
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from litex.soc.interconnect import wishbone
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from valentyusb import usbcore
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import epmem, unififo, epfifo
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from valentyusb.usbcore.endpoint import EndpointType
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from lxsocsupport import up5kspram, cas, spi_flash
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import argparse
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_io = [
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("serial", 0,
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Subsignal("rx", Pins("21")),
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Subsignal("tx", Pins("13"), Misc("PULLUP")),
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IOStandard("LVCMOS33")
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),
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("usb", 0,
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Subsignal("d_p", Pins("34")),
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Subsignal("d_n", Pins("37")),
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Subsignal("pullup", Pins("35")),
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IOStandard("LVCMOS33")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
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Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
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Subsignal("wp", Pins("18"), IOStandard("LVCMOS33")),
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Subsignal("hold", Pins("19"), IOStandard("LVCMOS33")),
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
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Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
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Subsignal("dq", Pins("14 17 19 18"), IOStandard("LVCMOS33")),
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),
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("clk48", 0, Pins("44"), IOStandard("LVCMOS33"))
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]
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_connectors = []
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class _CRG(Module):
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def __init__(self, platform):
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clk12 = Signal()
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# # "0b00" Sets 48MHz HFOSC output
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# # "0b01" Sets 24MHz HFOSC output.
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# # "0b10" Sets 12MHz HFOSC output.
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# # "0b11" Sets 6MHz HFOSC output
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# self.specials += Instance(
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# "SB_HFOSC",
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# i_CLKHFEN=1,
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# i_CLKHFPU=1,
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# o_CLKHF=clk12,
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# p_CLKHF_DIV="0b10", # 12MHz
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# )
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.reset = Signal()
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# FIXME: Use PLL, increase system clock to 32 MHz, pending nextpnr
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# fixes.
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.clock_domains.cd_por = ClockDomain()
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reset_delay = Signal(12, reset=4095)
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0)
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]
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# Divide clk48 down to clk12, to ensure they're synchronized.
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clk12_counter = Signal(2)
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self.sync.usb_48 += [
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clk12_counter.eq(clk12_counter + 1),
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]
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_counter[1],
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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self.clock_domains.cd_usb_48 = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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self.comb += [
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self.cd_usb_48.clk.eq(platform.request("clk48")),
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]
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class RandomFirmwareROM(wishbone.SRAM):
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"""
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Seed the random data with a fixed number, so different bitstreams
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can all share firmware.
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"""
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def __init__(self, size, seed=2373):
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def xorshift32(x):
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x = x ^ (x << 13) & 0xffffffff
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x = x ^ (x >> 17) & 0xffffffff
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x = x ^ (x << 5) & 0xffffffff
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return x & 0xffffffff
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def get_rand(x):
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out = 0
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for i in range(32):
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x = xorshift32(x)
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if (x & 1) == 1:
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out = out | (1 << i)
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return out & 0xffffffff
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data = []
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seed = 1
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for d in range(int(size / 4)):
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seed = get_rand(seed)
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data.append(seed)
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print("Firmware {} bytes of random data".format(size))
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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class Platform(LatticePlatform):
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default_clk_name = "clk48"
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default_clk_period = 20.833
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gateware_size = 0x20000
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def __init__(self, toolchain="icestorm"):
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LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm")
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def create_programmer(self):
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raise ValueError("programming is not supported")
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# def do_finalize(self, fragment):
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# LatticePlatform.do_finalize(self, fragment)
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class BaseSoC(SoCCore):
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csr_peripherals = [
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"cpu_or_bridge",
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"usb",
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"usb_obuf",
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"usb_ibuf",
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]
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csr_map_update(SoCCore.csr_map, csr_peripherals)
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mem_map = {
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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}
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mem_map.update(SoCCore.mem_map)
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interrupt_map = {
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"usb": 3,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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def __init__(self, platform, boot_source="random_rom", **kwargs):
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# Disable integrated RAM as we'll add it later
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self.integrated_sram_size = 0
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clk_freq = int(12e6)
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self.submodules.crg = _CRG(platform)
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platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
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platform.add_period_constraint(self.crg.cd_usb_12.clk, 1e9/clk_freq)
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SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs)
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# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
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# free up scarce block RAM.
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spram_size = 128*1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
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if boot_source == "random_rom":
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kwargs['cpu_reset_address']=0
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bios_size = 0x2000
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self.submodules.random_rom = RandomFirmwareROM(bios_size)
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self.add_constant("ROM_DISABLE", 1)
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self.register_rom(self.random_rom.bus, bios_size)
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elif boot_source == "bios_rom":
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kwargs['cpu_reset_address']=0
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bios_size = 0x2000
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self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
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elif boot_source == "spi_rom":
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bios_size = 0x8000
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kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
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self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
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self.add_constant("ROM_DISABLE", 1)
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self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
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self.add_memory_region("user_flash",
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self.flash_boot_address,
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# Leave a grace area- possible one-by-off bug in add_memory_region?
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# Possible fix: addr < origin + length - 1
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platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100)
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else:
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raise ValueError("unrecognized boot_source: {}".format(boot_source))
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# Add USB pads
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usb_pads = platform.request("usb")
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usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
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self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, endpoints=[EndpointType.BIDIR])
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# self.submodules.usb = epmem.MemInterface(usb_iobuf)
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# self.submodules.usb = unififo.UsbUniFifo(usb_iobuf)
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# Disable final deep-sleep power down so firmware words are loaded
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# onto softcore's address bus.
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platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin"
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platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
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def main():
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platform = Platform()
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parser = argparse.ArgumentParser(
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description="Build Fomu Main Gateware",
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add_help=False)
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parser.add_argument(
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"--bios", help="use bios as boot source", action="store_true"
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)
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parser.add_argument(
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"--rand", help="use random data as boot source", action="store_false"
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)
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parser.add_argument(
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"--spi", help="boot from spi", action="store_true"
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)
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(args, rest) = parser.parse_known_args()
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if args.rand:
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boot_source="random_rom"
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compile_software=False
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elif args.bios:
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boot_source="bios_rom"
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compile_software=True
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elif args.spi:
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boot_source = "spi_rom"
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compile_software = False
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soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant="min", boot_source=boot_source)
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builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
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vns = builder.build()
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soc.do_exit(vns)
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if __name__ == "__main__":
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main()
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