112 lines
2.5 KiB
C
112 lines
2.5 KiB
C
#include <irq.h>
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#include <uart.h>
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#ifdef __or1k__
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#include <spr-defs.h>
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#endif
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#if defined (__vexriscv__)
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#include <csr-defs.h>
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#endif
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#include <system.h>
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#include <generated/mem.h>
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#include <generated/csr.h>
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void flush_cpu_icache(void)
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{
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#if defined (__lm32__)
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asm volatile(
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"wcsr ICC, r0\n"
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"nop\n"
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"nop\n"
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"nop\n"
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"nop\n"
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);
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#elif defined (__or1k__)
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unsigned long iccfgr;
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unsigned long cache_set_size;
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unsigned long cache_ways;
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unsigned long cache_block_size;
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unsigned long cache_size;
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int i;
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iccfgr = mfspr(SPR_ICCFGR);
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cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
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cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
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cache_size = cache_set_size * cache_ways * cache_block_size;
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for (i = 0; i < cache_size; i += cache_block_size)
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mtspr(SPR_ICBIR, i);
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#elif defined (__picorv32__)
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/* no instruction cache */
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asm volatile("nop");
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#elif defined (__vexriscv__)
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asm volatile(
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".word(0x400F)\n"
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"nop\n"
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"nop\n"
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"nop\n"
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"nop\n"
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"nop\n"
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);
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#elif defined (__minerva__)
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/* no instruction cache */
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asm volatile("nop");
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#else
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#error Unsupported architecture
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#endif
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}
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void flush_cpu_dcache(void)
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{
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#if defined (__lm32__)
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asm volatile(
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"wcsr DCC, r0\n"
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"nop\n"
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);
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#elif defined (__or1k__)
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unsigned long dccfgr;
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unsigned long cache_set_size;
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unsigned long cache_ways;
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unsigned long cache_block_size;
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unsigned long cache_size;
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int i;
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dccfgr = mfspr(SPR_DCCFGR);
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cache_ways = 1 << (dccfgr & SPR_ICCFGR_NCW);
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cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
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cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
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cache_size = cache_set_size * cache_ways * cache_block_size;
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for (i = 0; i < cache_size; i += cache_block_size)
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mtspr(SPR_DCBIR, i);
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#elif defined (__picorv32__)
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/* no data cache */
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asm volatile("nop");
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#elif defined (__vexriscv__)
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unsigned long cache_info;
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asm volatile ("csrr %0, %1" : "=r"(cache_info) : "i"(CSR_DCACHE_INFO));
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unsigned long cache_way_size = cache_info & 0xFFFFF;
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unsigned long cache_line_size = (cache_info >> 20) & 0xFFF;
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for(register unsigned long idx = 0;idx < cache_way_size;idx += cache_line_size){
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asm volatile("mv x10, %0 \n .word(0b01110000000001010101000000001111)"::"r"(idx));
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}
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#elif defined (__minerva__)
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/* no data cache */
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asm volatile("nop");
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#else
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#error Unsupported architecture
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#endif
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}
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#ifdef L2_SIZE
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void flush_l2_cache(void)
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{
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unsigned int i;
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for(i=0;i<2*L2_SIZE/4;i++) {
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((volatile unsigned int *) MAIN_RAM_BASE)[i];
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}
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}
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#endif
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