hw: foboot-bitstream: clean up debug generation
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
		@@ -250,9 +250,9 @@ class BaseSoC(SoCCore):
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        self.submodules.crg = _CRG(platform)
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					        self.submodules.crg = _CRG(platform)
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        SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs)
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					        SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs)
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        self.cpu.use_external_variant("vexriscv-2-stage-with-debug.v")
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        if debug:
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					        if debug:
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					            self.cpu.use_external_variant("vexriscv-2-stage-with-debug.v")
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            self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
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					            self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
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        # SPRAM- UP5K has single port RAM, might as well use it as SRAM to
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					        # SPRAM- UP5K has single port RAM, might as well use it as SRAM to
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@@ -331,6 +331,8 @@ def main():
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    )
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					    )
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    (args, rest) = parser.parse_known_args()
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					    (args, rest) = parser.parse_known_args()
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					    debug = False
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					    cpu_variant = "min"
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    if args.rand:
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					    if args.rand:
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        boot_source="random_rom"
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					        boot_source="random_rom"
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        compile_software=False
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					        compile_software=False
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@@ -340,14 +342,12 @@ def main():
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    elif args.spi:
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					    elif args.spi:
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        boot_source = "spi_rom"
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					        boot_source = "spi_rom"
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        compile_software = False
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					        compile_software = False
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    # if args.with_debug:
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					    if args.with_debug:
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    #     cpu_variant = "debug"
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					        cpu_variant = "debug"
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    #     debug = True
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					        debug = True
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    # else:
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					    else:
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    #     cpu_variant = "min"
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					        cpu_variant = "min"
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    #     debug = False
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					        debug = False
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    cpu_variant = "debug"
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    debug = True
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    soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant, debug=debug, boot_source=boot_source)
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					    soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant, debug=debug, boot_source=boot_source)
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    builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
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					    builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
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