hw: foboot-bitstream: clean up debug generation
Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
parent
4f0507fc77
commit
fa690d63ed
@ -250,9 +250,9 @@ class BaseSoC(SoCCore):
|
|||||||
self.submodules.crg = _CRG(platform)
|
self.submodules.crg = _CRG(platform)
|
||||||
|
|
||||||
SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs)
|
SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs)
|
||||||
self.cpu.use_external_variant("vexriscv-2-stage-with-debug.v")
|
|
||||||
|
|
||||||
if debug:
|
if debug:
|
||||||
|
self.cpu.use_external_variant("vexriscv-2-stage-with-debug.v")
|
||||||
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
|
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10)
|
||||||
|
|
||||||
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
|
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
|
||||||
@ -331,6 +331,8 @@ def main():
|
|||||||
)
|
)
|
||||||
(args, rest) = parser.parse_known_args()
|
(args, rest) = parser.parse_known_args()
|
||||||
|
|
||||||
|
debug = False
|
||||||
|
cpu_variant = "min"
|
||||||
if args.rand:
|
if args.rand:
|
||||||
boot_source="random_rom"
|
boot_source="random_rom"
|
||||||
compile_software=False
|
compile_software=False
|
||||||
@ -340,14 +342,12 @@ def main():
|
|||||||
elif args.spi:
|
elif args.spi:
|
||||||
boot_source = "spi_rom"
|
boot_source = "spi_rom"
|
||||||
compile_software = False
|
compile_software = False
|
||||||
# if args.with_debug:
|
if args.with_debug:
|
||||||
# cpu_variant = "debug"
|
cpu_variant = "debug"
|
||||||
# debug = True
|
debug = True
|
||||||
# else:
|
else:
|
||||||
# cpu_variant = "min"
|
cpu_variant = "min"
|
||||||
# debug = False
|
debug = False
|
||||||
cpu_variant = "debug"
|
|
||||||
debug = True
|
|
||||||
|
|
||||||
soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant, debug=debug, boot_source=boot_source)
|
soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant, debug=debug, boot_source=boot_source)
|
||||||
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
|
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
|
||||||
|
Loading…
Reference in New Issue
Block a user