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foboot-bitstream: send clk48 through shifter, then through pll

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-03-08 20:47:42 +08:00
parent 3df59a866d
commit d603113b6f
1 changed files with 49 additions and 17 deletions
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66
hw/foboot-bitstream.py
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@ -75,6 +75,7 @@ _connectors = []
class _CRG(Module): class _CRG(Module):
def __init__(self, platform): def __init__(self, platform):
clk48_raw = platform.request("clk48") clk48_raw = platform.request("clk48")
clk12_raw = Signal()
clk48 = Signal() clk48 = Signal()
clk12 = Signal() clk12 = Signal()
@ -97,16 +98,15 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain() self.clock_domains.cd_usb_48 = ClockDomain()
self.clock_domains.cd_usb_48_raw = ClockDomain()
platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6)
platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6) platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6) platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
self.reset = Signal() self.reset = Signal()
self.comb += self.cd_sys.clk.eq(clk12)
self.comb += self.cd_usb_12.clk.eq(clk12)
# POR reset logic- POR generated from sys clk, POR logic feeds sys clk # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
# reset. # reset.
self.clock_domains.cd_por = ClockDomain() self.clock_domains.cd_por = ClockDomain()
@ -114,28 +114,60 @@ class _CRG(Module):
self.comb += [ self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk), self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(reset_delay != 0), self.cd_sys.rst.eq(reset_delay != 0),
self.cd_usb_12.rst.eq(reset_delay != 0) self.cd_usb_12.rst.eq(reset_delay != 0),
# self.cd_usb_48.rst.eq(reset_delay != 0),
# self.cd_usb_48_raw.rst.eq(reset_delay != 0),
] ]
# self.specials += Instance( clk48_in = Signal()
# "SB_GB", self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw)
# i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_counter[1],
# o_GLOBAL_BUFFER_OUTPUT=clk12,
# )
self.specials += Instance( self.specials += Instance(
"SB_GB", "SB_GB",
i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw, i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw,
o_GLOBAL_BUFFER_OUTPUT=clk48, o_GLOBAL_BUFFER_OUTPUT=clk48_in,
)
self.comb += self.cd_usb_48.clk.eq(clk48)
self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1)
self.comb += clk12_raw.eq(clk12_counter[1])
self.specials += Instance(
"SB_GB",
i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
o_GLOBAL_BUFFER_OUTPUT=clk12,
) )
self.comb += [ self.specials += Instance(
self.cd_usb_48.clk.eq(clk48), "SB_PLL40_CORE",
] # Parameters
p_DIVR = 0,
p_DIVF = 3,
p_DIVQ = 2,
p_FILTER_RANGE = 1,
p_FEEDBACK_PATH = "PHASE_AND_DELAY",
p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
p_FDA_FEEDBACK = 15,
p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
p_FDA_RELATIVE = 0,
p_SHIFTREG_DIV_MODE = 1,
p_PLLOUT_SELECT = "SHIFTREG_0deg",
p_ENABLE_ICEGATE = 0,
# IO
i_REFERENCECLK = clk12,
# o_PLLOUTCORE = clk12,
o_PLLOUTGLOBAL = clk48,
#i_EXTFEEDBACK,
#i_DYNAMICDELAY,
#o_LOCK,
i_BYPASS = 0,
i_RESETB = 1,
#i_LATCHINPUTVALUE,
#o_SDO,
#i_SDI,
)
self.sync.usb_48 += [ self.comb += self.cd_sys.clk.eq(clk12)
clk12_counter.eq(clk12_counter + 1), self.comb += self.cd_usb_12.clk.eq(clk12)
]
self.comb += clk12.eq(clk12_counter[1])
self.sync.por += \ self.sync.por += \
If(reset_delay != 0, If(reset_delay != 0,