hw: bitstream: simplify command line argument parsing
Signed-off-by: Sean Cross <sean@xobs.io>
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@ -420,7 +420,7 @@ class BaseSoC(SoCCore):
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}
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interrupt_map.update(SoCCore.interrupt_map)
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def __init__(self, platform, boot_source="random_rom", debug=False, bios_file=None, use_pll=True, **kwargs):
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def __init__(self, platform, boot_source="rand", debug=False, bios_file=None, use_pll=True, **kwargs):
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# Disable integrated RAM as we'll add it later
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self.integrated_sram_size = 0
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@ -444,13 +444,13 @@ class BaseSoC(SoCCore):
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
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if boot_source == "random_rom":
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if boot_source == "rand":
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kwargs['cpu_reset_address']=0
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bios_size = 0x2000
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self.submodules.random_rom = RandomFirmwareROM(bios_size)
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self.add_constant("ROM_DISABLE", 1)
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self.register_rom(self.random_rom.bus, bios_size)
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elif boot_source == "bios_rom":
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elif boot_source == "bios":
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kwargs['cpu_reset_address']=0
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if bios_file is None:
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bios_size = 0x2000
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@ -461,7 +461,7 @@ class BaseSoC(SoCCore):
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self.add_constant("ROM_DISABLE", 1)
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self.register_rom(self.firmware_rom.bus, bios_size)
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elif boot_source == "spi_rom":
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elif boot_source == "spi":
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bios_size = 0x8000
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kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
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self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
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@ -587,18 +587,9 @@ def main():
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print("{:08x}".format(seed), file=output)
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return 0
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bios_file = None
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compile_software = False
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if args.boot_source == "rand":
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boot_source = "random_rom"
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elif args.boot_source == "bios":
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boot_source = "bios_rom"
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if args.bios is not None:
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bios_file = args.bios
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else:
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if args.boot_source == "bios" and args.bios is None:
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compile_software = True
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elif args.boot_source == "spi":
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boot_source = "spi_rom"
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cpu_variant = "min"
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debug = False
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@ -608,8 +599,8 @@ def main():
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platform = Platform(revision=args.revision)
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soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant,
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debug=debug, boot_source=boot_source,
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bios_file=bios_file, use_pll=args.no_pll)
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debug=debug, boot_source=args.boot_source,
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bios_file=args.bios, use_pll=args.no_pll)
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builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software)
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vns = builder.build()
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soc.do_exit(vns)
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