From 7191c12490718d4a921b8adc5c8a364e1cce9013 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Thu, 28 Mar 2019 11:11:36 +0800 Subject: [PATCH] wip: just need to get WARMBOOT working Signed-off-by: Sean Cross --- ...ith-debug.v => 2-stage-1024-cache-debug.v} | 686 +-- hw/2-stage-1024-cache-debug.yaml | 5 + hw/2-stage-no-cache-debug.v | 3769 +++++++++++++++ hw/2-stage-no-cache-debug.yaml | 5 + hw/4-stage-1024-cache-debug.v | 4099 +++++++++++++++++ hw/4-stage-1024-cache-debug.yaml | 5 + hw/4-stage-no-cache-debug.v | 4099 +++++++++++++++++ hw/4-stage-no-cache-debug.yaml | 5 + hw/5-stage-pipelined-no-cache-debug.v | 3902 ++++++++++++++++ hw/5-stage-pipelined-no-cache-debug.yaml | 1 + hw/foboot-bitstream.py | 400 +- 11 files changed, 16546 insertions(+), 430 deletions(-) rename hw/{vexriscv-2-stage-with-debug.v => 2-stage-1024-cache-debug.v} (89%) create mode 100644 hw/2-stage-1024-cache-debug.yaml create mode 100644 hw/2-stage-no-cache-debug.v create mode 100644 hw/2-stage-no-cache-debug.yaml create mode 100644 hw/4-stage-1024-cache-debug.v create mode 100644 hw/4-stage-1024-cache-debug.yaml create mode 100644 hw/4-stage-no-cache-debug.v create mode 100644 hw/4-stage-no-cache-debug.yaml create mode 100644 hw/5-stage-pipelined-no-cache-debug.v create mode 100644 hw/5-stage-pipelined-no-cache-debug.yaml diff --git a/hw/vexriscv-2-stage-with-debug.v b/hw/2-stage-1024-cache-debug.v similarity index 89% rename from hw/vexriscv-2-stage-with-debug.v rename to hw/2-stage-1024-cache-debug.v index 27fc4a9..bb89379 100644 --- a/hw/vexriscv-2-stage-with-debug.v +++ b/hw/2-stage-1024-cache-debug.v @@ -1,5 +1,5 @@ // Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26 -// Date : 20/03/2019, 09:30:48 +// Date : 26/03/2019, 08:02:43 // Component : VexRiscv @@ -92,19 +92,19 @@ module InstructionCache ( input io_mem_rsp_payload_error, input clk, input reset); - reg [22:0] _zz_12_; + reg [23:0] _zz_12_; reg [31:0] _zz_13_; wire _zz_14_; wire [0:0] _zz_15_; wire [0:0] _zz_16_; - wire [22:0] _zz_17_; + wire [23:0] _zz_17_; reg _zz_1_; reg _zz_2_; reg lineLoader_fire; reg lineLoader_valid; reg [31:0] lineLoader_address; reg lineLoader_hadError; - reg [6:0] lineLoader_flushCounter; + reg [5:0] lineLoader_flushCounter; reg _zz_3_; reg lineLoader_flushFromInterface; wire _zz_4_; @@ -116,21 +116,21 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; reg [2:0] lineLoader_wordIndex; wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; + wire [4:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire [21:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [8:0] lineLoader_write_data_0_payload_address; + wire [7:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; wire _zz_5_; - wire [5:0] _zz_6_; + wire [4:0] _zz_6_; wire _zz_7_; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8_; - wire [8:0] _zz_9_; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_8_; + wire [7:0] _zz_9_; wire _zz_10_; wire [31:0] fetchStage_read_waysValues_0_data; reg [31:0] decodeStage_mmuRsp_physicalAddress; @@ -143,7 +143,7 @@ module InstructionCache ( reg decodeStage_mmuRsp_hit; reg decodeStage_hit_tags_0_valid; reg decodeStage_hit_tags_0_error; - reg [20:0] decodeStage_hit_tags_0_address; + reg [21:0] decodeStage_hit_tags_0_address; wire decodeStage_hit_hits_0; wire decodeStage_hit_valid; wire decodeStage_hit_error; @@ -152,9 +152,9 @@ module InstructionCache ( reg [31:0] decodeStage_hit_word; reg io_cpu_fetch_dataBypassValid_regNextWhen; reg [31:0] io_cpu_fetch_dataBypass_regNextWhen; - reg [22:0] ways_0_tags [0:63]; - reg [31:0] ways_0_datas [0:511]; - assign _zz_14_ = (! lineLoader_flushCounter[6]); + reg [23:0] ways_0_tags [0:31]; + reg [31:0] ways_0_datas [0:255]; + assign _zz_14_ = (! lineLoader_flushCounter[5]); assign _zz_15_ = _zz_8_[0 : 0]; assign _zz_16_ = _zz_8_[1 : 1]; assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; @@ -222,7 +222,7 @@ module InstructionCache ( end assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid)); - assign _zz_4_ = lineLoader_flushCounter[6]; + assign _zz_4_ = lineLoader_flushCounter[5]; assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; @@ -238,21 +238,21 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); assign _zz_5_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_6_ = io_cpu_prefetch_pc[10 : 5]; + assign _zz_6_ = io_cpu_prefetch_pc[9 : 5]; assign _zz_7_ = (! io_cpu_fetch_isStuck); assign _zz_8_ = _zz_12_; assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8_[22 : 2]; - assign _zz_9_ = io_cpu_prefetch_pc[10 : 2]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2]; + assign _zz_9_ = io_cpu_prefetch_pc[9 : 2]; assign _zz_10_ = (! io_cpu_fetch_isStuck); assign fetchStage_read_waysValues_0_data = _zz_13_; assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]); @@ -261,7 +261,7 @@ module InstructionCache ( assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 11])); + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10])); assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); assign decodeStage_hit_error = decodeStage_hit_tags_0_error; assign decodeStage_hit_data = _zz_11_; @@ -282,7 +282,7 @@ module InstructionCache ( if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; - lineLoader_flushCounter <= (7'b0000000); + lineLoader_flushCounter <= (6'b000000); lineLoader_flushFromInterface <= 1'b0; lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= (3'b000); @@ -297,11 +297,11 @@ module InstructionCache ( lineLoader_valid <= 1'b1; end if(_zz_14_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); + lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); end if(io_flush_cmd_valid)begin if(io_flush_cmd_ready)begin - lineLoader_flushCounter <= (7'b0000000); + lineLoader_flushCounter <= (6'b000000); lineLoader_flushFromInterface <= 1'b1; end end @@ -324,7 +324,7 @@ module InstructionCache ( if(io_cpu_fill_valid)begin lineLoader_address <= io_cpu_fill_payload; end - _zz_3_ <= lineLoader_flushCounter[6]; + _zz_3_ <= lineLoader_flushCounter[5]; _zz_4__regNext <= _zz_4_; if((! io_cpu_decode_isStuck))begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; @@ -492,141 +492,149 @@ module VexRiscv ( wire [0:0] _zz_247_; wire [0:0] _zz_248_; wire [0:0] _zz_249_; - wire [0:0] _zz_250_; - wire [0:0] _zz_251_; - wire [26:0] _zz_252_; - wire [6:0] _zz_253_; - wire [1:0] _zz_254_; + wire [30:0] _zz_250_; + wire [30:0] _zz_251_; + wire [30:0] _zz_252_; + wire [30:0] _zz_253_; + wire [0:0] _zz_254_; wire [0:0] _zz_255_; - wire [7:0] _zz_256_; - wire _zz_257_; + wire [0:0] _zz_256_; + wire [0:0] _zz_257_; wire [0:0] _zz_258_; wire [0:0] _zz_259_; - wire [31:0] _zz_260_; - wire [31:0] _zz_261_; - wire [31:0] _zz_262_; - wire [31:0] _zz_263_; - wire [0:0] _zz_264_; - wire [0:0] _zz_265_; - wire [2:0] _zz_266_; - wire [2:0] _zz_267_; - wire _zz_268_; - wire [0:0] _zz_269_; - wire [19:0] _zz_270_; + wire [26:0] _zz_260_; + wire [6:0] _zz_261_; + wire [1:0] _zz_262_; + wire [0:0] _zz_263_; + wire [7:0] _zz_264_; + wire _zz_265_; + wire [0:0] _zz_266_; + wire [0:0] _zz_267_; + wire [31:0] _zz_268_; + wire [31:0] _zz_269_; + wire [31:0] _zz_270_; wire [31:0] _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire [0:0] _zz_274_; - wire [3:0] _zz_275_; + wire [0:0] _zz_272_; + wire [0:0] _zz_273_; + wire [2:0] _zz_274_; + wire [2:0] _zz_275_; wire _zz_276_; - wire [2:0] _zz_277_; - wire [2:0] _zz_278_; - wire _zz_279_; - wire [0:0] _zz_280_; - wire [16:0] _zz_281_; - wire [31:0] _zz_282_; - wire [31:0] _zz_283_; - wire [31:0] _zz_284_; - wire [31:0] _zz_285_; - wire _zz_286_; - wire [0:0] _zz_287_; - wire [1:0] _zz_288_; - wire [31:0] _zz_289_; - wire _zz_290_; - wire [0:0] _zz_291_; - wire [0:0] _zz_292_; - wire [0:0] _zz_293_; - wire [0:0] _zz_294_; + wire [0:0] _zz_277_; + wire [19:0] _zz_278_; + wire [31:0] _zz_279_; + wire _zz_280_; + wire _zz_281_; + wire [0:0] _zz_282_; + wire [3:0] _zz_283_; + wire _zz_284_; + wire [2:0] _zz_285_; + wire [2:0] _zz_286_; + wire _zz_287_; + wire [0:0] _zz_288_; + wire [16:0] _zz_289_; + wire [31:0] _zz_290_; + wire [31:0] _zz_291_; + wire [31:0] _zz_292_; + wire [31:0] _zz_293_; + wire _zz_294_; wire [0:0] _zz_295_; - wire [0:0] _zz_296_; - wire _zz_297_; - wire [0:0] _zz_298_; - wire [14:0] _zz_299_; - wire [31:0] _zz_300_; - wire _zz_301_; - wire _zz_302_; - wire [31:0] _zz_303_; - wire [31:0] _zz_304_; - wire [31:0] _zz_305_; - wire [31:0] _zz_306_; - wire [31:0] _zz_307_; + wire [1:0] _zz_296_; + wire [31:0] _zz_297_; + wire _zz_298_; + wire [0:0] _zz_299_; + wire [0:0] _zz_300_; + wire [0:0] _zz_301_; + wire [0:0] _zz_302_; + wire [0:0] _zz_303_; + wire [0:0] _zz_304_; + wire _zz_305_; + wire [0:0] _zz_306_; + wire [14:0] _zz_307_; wire [31:0] _zz_308_; - wire [31:0] _zz_309_; - wire [31:0] _zz_310_; + wire _zz_309_; + wire _zz_310_; wire [31:0] _zz_311_; - wire [0:0] _zz_312_; - wire [0:0] _zz_313_; - wire [1:0] _zz_314_; - wire [1:0] _zz_315_; - wire _zz_316_; - wire [0:0] _zz_317_; - wire [12:0] _zz_318_; + wire [31:0] _zz_312_; + wire [31:0] _zz_313_; + wire [31:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire [31:0] _zz_317_; + wire [31:0] _zz_318_; wire [31:0] _zz_319_; - wire [31:0] _zz_320_; - wire [31:0] _zz_321_; - wire [31:0] _zz_322_; - wire [31:0] _zz_323_; - wire [0:0] _zz_324_; + wire [0:0] _zz_320_; + wire [0:0] _zz_321_; + wire [1:0] _zz_322_; + wire [1:0] _zz_323_; + wire _zz_324_; wire [0:0] _zz_325_; - wire [0:0] _zz_326_; - wire [0:0] _zz_327_; - wire _zz_328_; - wire [0:0] _zz_329_; - wire [9:0] _zz_330_; + wire [12:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [31:0] _zz_329_; + wire [31:0] _zz_330_; wire [31:0] _zz_331_; - wire _zz_332_; - wire _zz_333_; + wire [0:0] _zz_332_; + wire [0:0] _zz_333_; wire [0:0] _zz_334_; wire [0:0] _zz_335_; - wire [3:0] _zz_336_; - wire [3:0] _zz_337_; - wire _zz_338_; - wire [0:0] _zz_339_; - wire [5:0] _zz_340_; - wire [31:0] _zz_341_; - wire [31:0] _zz_342_; - wire [31:0] _zz_343_; - wire [31:0] _zz_344_; - wire _zz_345_; - wire [0:0] _zz_346_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [9:0] _zz_338_; + wire [31:0] _zz_339_; + wire _zz_340_; + wire _zz_341_; + wire [0:0] _zz_342_; + wire [0:0] _zz_343_; + wire [3:0] _zz_344_; + wire [3:0] _zz_345_; + wire _zz_346_; wire [0:0] _zz_347_; - wire _zz_348_; - wire [0:0] _zz_349_; - wire [0:0] _zz_350_; - wire [2:0] _zz_351_; - wire [2:0] _zz_352_; + wire [5:0] _zz_348_; + wire [31:0] _zz_349_; + wire [31:0] _zz_350_; + wire [31:0] _zz_351_; + wire [31:0] _zz_352_; wire _zz_353_; wire [0:0] _zz_354_; - wire [2:0] _zz_355_; - wire [31:0] _zz_356_; - wire [31:0] _zz_357_; - wire [31:0] _zz_358_; - wire [31:0] _zz_359_; - wire [31:0] _zz_360_; - wire [31:0] _zz_361_; - wire [31:0] _zz_362_; - wire [31:0] _zz_363_; - wire _zz_364_; - wire [0:0] _zz_365_; - wire [0:0] _zz_366_; - wire _zz_367_; - wire [1:0] _zz_368_; - wire [1:0] _zz_369_; - wire _zz_370_; - wire [0:0] _zz_371_; - wire [0:0] _zz_372_; - wire [31:0] _zz_373_; - wire [31:0] _zz_374_; - wire [31:0] _zz_375_; - wire [31:0] _zz_376_; - wire [31:0] _zz_377_; - wire [31:0] _zz_378_; - wire [31:0] _zz_379_; - wire [31:0] _zz_380_; - wire _zz_381_; - wire _zz_382_; - wire _zz_383_; - wire _zz_384_; + wire [0:0] _zz_355_; + wire _zz_356_; + wire [0:0] _zz_357_; + wire [0:0] _zz_358_; + wire [2:0] _zz_359_; + wire [2:0] _zz_360_; + wire _zz_361_; + wire [0:0] _zz_362_; + wire [2:0] _zz_363_; + wire [31:0] _zz_364_; + wire [31:0] _zz_365_; + wire [31:0] _zz_366_; + wire [31:0] _zz_367_; + wire [31:0] _zz_368_; + wire [31:0] _zz_369_; + wire [31:0] _zz_370_; + wire [31:0] _zz_371_; + wire _zz_372_; + wire [0:0] _zz_373_; + wire [0:0] _zz_374_; + wire _zz_375_; + wire [1:0] _zz_376_; + wire [1:0] _zz_377_; + wire _zz_378_; + wire [0:0] _zz_379_; + wire [0:0] _zz_380_; + wire [31:0] _zz_381_; + wire [31:0] _zz_382_; + wire [31:0] _zz_383_; + wire [31:0] _zz_384_; + wire [31:0] _zz_385_; + wire [31:0] _zz_386_; + wire [31:0] _zz_387_; + wire [31:0] _zz_388_; + wire _zz_389_; + wire _zz_390_; + wire _zz_391_; + wire _zz_392_; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire decode_SRC_LESS_UNSIGNED; @@ -1027,6 +1035,14 @@ module VexRiscv ( reg DebugPlugin_isPipActive_regNext; wire DebugPlugin_isPipBusy; reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; reg [31:0] DebugPlugin_busReadDataReg; reg _zz_163_; reg DebugPlugin_resetIt_regNext; @@ -1191,145 +1207,153 @@ module VexRiscv ( assign _zz_243_ = (_zz_156_ - (3'b001)); assign _zz_244_ = (execute_INSTRUCTION[5] ? (3'b110) : (3'b100)); assign _zz_245_ = {1'd0, _zz_244_}; - assign _zz_246_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_247_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_248_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_249_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_250_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_251_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_252_ = (iBus_cmd_payload_address >>> 5); - assign _zz_253_ = ({3'd0,_zz_168_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - assign _zz_254_ = {_zz_91_,_zz_90_}; - assign _zz_255_ = decode_INSTRUCTION[31]; - assign _zz_256_ = decode_INSTRUCTION[19 : 12]; - assign _zz_257_ = decode_INSTRUCTION[20]; - assign _zz_258_ = decode_INSTRUCTION[31]; - assign _zz_259_ = decode_INSTRUCTION[7]; - assign _zz_260_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_261_ = (32'b00000000000000000001000001010000); - assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_263_ = (32'b00000000000000000010000001010000); - assign _zz_264_ = ((decode_INSTRUCTION & _zz_271_) == (32'b00000000000000000001000000000000)); - assign _zz_265_ = _zz_117_; - assign _zz_266_ = {_zz_117_,{_zz_272_,_zz_273_}}; - assign _zz_267_ = (3'b000); - assign _zz_268_ = ({_zz_119_,{_zz_274_,_zz_275_}} != (6'b000000)); - assign _zz_269_ = (_zz_276_ != (1'b0)); - assign _zz_270_ = {(_zz_277_ != _zz_278_),{_zz_279_,{_zz_280_,_zz_281_}}}; - assign _zz_271_ = (32'b00000000000000000001000000000000); - assign _zz_272_ = ((decode_INSTRUCTION & _zz_282_) == (32'b00000000000000000001000000000000)); - assign _zz_273_ = ((decode_INSTRUCTION & _zz_283_) == (32'b00000000000000000010000000000000)); - assign _zz_274_ = (_zz_284_ == _zz_285_); - assign _zz_275_ = {_zz_286_,{_zz_287_,_zz_288_}}; - assign _zz_276_ = ((decode_INSTRUCTION & _zz_289_) == (32'b00000000000000000000000000010000)); - assign _zz_277_ = {_zz_290_,{_zz_291_,_zz_292_}}; - assign _zz_278_ = (3'b000); - assign _zz_279_ = ({_zz_293_,_zz_294_} != (2'b00)); - assign _zz_280_ = (_zz_295_ != _zz_296_); - assign _zz_281_ = {_zz_297_,{_zz_298_,_zz_299_}}; - assign _zz_282_ = (32'b00000000000000000011000000000000); - assign _zz_283_ = (32'b00000000000000000011000000000000); - assign _zz_284_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_285_ = (32'b00000000000000000001000000010000); - assign _zz_286_ = ((decode_INSTRUCTION & _zz_300_) == (32'b00000000000000000010000000010000)); - assign _zz_287_ = _zz_120_; - assign _zz_288_ = {_zz_301_,_zz_302_}; - assign _zz_289_ = (32'b00000000000000000000000000010000); - assign _zz_290_ = ((decode_INSTRUCTION & _zz_303_) == (32'b00000000000000000000000001000000)); - assign _zz_291_ = (_zz_304_ == _zz_305_); - assign _zz_292_ = (_zz_306_ == _zz_307_); - assign _zz_293_ = _zz_119_; - assign _zz_294_ = (_zz_308_ == _zz_309_); - assign _zz_295_ = (_zz_310_ == _zz_311_); - assign _zz_296_ = (1'b0); - assign _zz_297_ = ({_zz_312_,_zz_313_} != (2'b00)); - assign _zz_298_ = (_zz_314_ != _zz_315_); - assign _zz_299_ = {_zz_316_,{_zz_317_,_zz_318_}}; - assign _zz_300_ = (32'b00000000000000000010000000010000); - assign _zz_301_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000)); - assign _zz_302_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_303_ = (32'b00000000000000000000000001000100); - assign _zz_304_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110000)); - assign _zz_305_ = (32'b01000000000000000000000000110000); - assign _zz_306_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_307_ = (32'b00000000000000000010000000010000); - assign _zz_308_ = (decode_INSTRUCTION & (32'b00000000000000000101000000010100)); - assign _zz_309_ = (32'b00000000000000000000000000000100); - assign _zz_310_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_311_ = (32'b00000000000000000000000001000000); - assign _zz_312_ = ((decode_INSTRUCTION & _zz_319_) == (32'b00000000000000000000000000000100)); - assign _zz_313_ = _zz_118_; - assign _zz_314_ = {(_zz_320_ == _zz_321_),_zz_118_}; - assign _zz_315_ = (2'b00); - assign _zz_316_ = ((_zz_322_ == _zz_323_) != (1'b0)); - assign _zz_317_ = ({_zz_324_,_zz_325_} != (2'b00)); - assign _zz_318_ = {(_zz_326_ != _zz_327_),{_zz_328_,{_zz_329_,_zz_330_}}}; - assign _zz_319_ = (32'b00000000000000000000000000010100); - assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_321_ = (32'b00000000000000000000000000000100); - assign _zz_322_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); - assign _zz_323_ = (32'b00000000000000000000000001010000); - assign _zz_324_ = _zz_116_; - assign _zz_325_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); - assign _zz_326_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_327_ = (1'b0); - assign _zz_328_ = (((decode_INSTRUCTION & _zz_331_) == (32'b00000000000000000101000000010000)) != (1'b0)); - assign _zz_329_ = ({_zz_332_,_zz_333_} != (2'b00)); - assign _zz_330_ = {({_zz_334_,_zz_335_} != (2'b00)),{(_zz_336_ != _zz_337_),{_zz_338_,{_zz_339_,_zz_340_}}}}; - assign _zz_331_ = (32'b00000000000000000111000001010100); - assign _zz_332_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); - assign _zz_333_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); - assign _zz_334_ = ((decode_INSTRUCTION & _zz_341_) == (32'b00000000000000000000000000100000)); - assign _zz_335_ = ((decode_INSTRUCTION & _zz_342_) == (32'b00000000000000000000000000100000)); - assign _zz_336_ = {(_zz_343_ == _zz_344_),{_zz_345_,{_zz_346_,_zz_347_}}}; - assign _zz_337_ = (4'b0000); - assign _zz_338_ = ({_zz_117_,_zz_348_} != (2'b00)); - assign _zz_339_ = ({_zz_349_,_zz_350_} != (2'b00)); - assign _zz_340_ = {(_zz_351_ != _zz_352_),{_zz_353_,{_zz_354_,_zz_355_}}}; - assign _zz_341_ = (32'b00000000000000000000000000110100); - assign _zz_342_ = (32'b00000000000000000000000001100100); - assign _zz_343_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_344_ = (32'b00000000000000000000000000000000); - assign _zz_345_ = ((decode_INSTRUCTION & _zz_356_) == (32'b00000000000000000000000000000000)); - assign _zz_346_ = (_zz_357_ == _zz_358_); - assign _zz_347_ = (_zz_359_ == _zz_360_); - assign _zz_348_ = ((decode_INSTRUCTION & _zz_361_) == (32'b00000000000000000000000000100000)); - assign _zz_349_ = _zz_117_; - assign _zz_350_ = (_zz_362_ == _zz_363_); - assign _zz_351_ = {_zz_364_,{_zz_365_,_zz_366_}}; - assign _zz_352_ = (3'b000); - assign _zz_353_ = (_zz_367_ != (1'b0)); - assign _zz_354_ = (_zz_368_ != _zz_369_); - assign _zz_355_ = {_zz_370_,{_zz_371_,_zz_372_}}; - assign _zz_356_ = (32'b00000000000000000000000000011000); - assign _zz_357_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_358_ = (32'b00000000000000000010000000000000); - assign _zz_359_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_360_ = (32'b00000000000000000001000000000000); - assign _zz_361_ = (32'b00000000000000000000000001110000); - assign _zz_362_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_363_ = (32'b00000000000000000000000000000000); - assign _zz_364_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); - assign _zz_365_ = ((decode_INSTRUCTION & _zz_373_) == (32'b00000000000000000100000000010000)); - assign _zz_366_ = ((decode_INSTRUCTION & _zz_374_) == (32'b00000000000000000001000000010000)); - assign _zz_367_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); - assign _zz_368_ = {(_zz_375_ == _zz_376_),(_zz_377_ == _zz_378_)}; - assign _zz_369_ = (2'b00); - assign _zz_370_ = ((_zz_379_ == _zz_380_) != (1'b0)); - assign _zz_371_ = (_zz_116_ != (1'b0)); - assign _zz_372_ = (_zz_381_ != (1'b0)); - assign _zz_373_ = (32'b00000000000000000100000000010100); - assign _zz_374_ = (32'b00000000000000000011000000010100); - assign _zz_375_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_376_ = (32'b00000000000000000010000000000000); - assign _zz_377_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); - assign _zz_378_ = (32'b00000000000000000001000000000000); - assign _zz_379_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_380_ = (32'b00000000000000000000000000000000); - assign _zz_381_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000000000000001000)); - assign _zz_382_ = execute_INSTRUCTION[31]; - assign _zz_383_ = execute_INSTRUCTION[31]; - assign _zz_384_ = execute_INSTRUCTION[7]; + assign _zz_246_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_247_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_248_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_249_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_250_ = (decode_PC >>> 1); + assign _zz_251_ = (decode_PC >>> 1); + assign _zz_252_ = (decode_PC >>> 1); + assign _zz_253_ = (decode_PC >>> 1); + assign _zz_254_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_255_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_256_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_257_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_258_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_259_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_260_ = (iBus_cmd_payload_address >>> 5); + assign _zz_261_ = ({3'd0,_zz_168_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_262_ = {_zz_91_,_zz_90_}; + assign _zz_263_ = decode_INSTRUCTION[31]; + assign _zz_264_ = decode_INSTRUCTION[19 : 12]; + assign _zz_265_ = decode_INSTRUCTION[20]; + assign _zz_266_ = decode_INSTRUCTION[31]; + assign _zz_267_ = decode_INSTRUCTION[7]; + assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_269_ = (32'b00000000000000000001000001010000); + assign _zz_270_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_271_ = (32'b00000000000000000010000001010000); + assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000001000000000000)); + assign _zz_273_ = _zz_117_; + assign _zz_274_ = {_zz_117_,{_zz_280_,_zz_281_}}; + assign _zz_275_ = (3'b000); + assign _zz_276_ = ({_zz_119_,{_zz_282_,_zz_283_}} != (6'b000000)); + assign _zz_277_ = (_zz_284_ != (1'b0)); + assign _zz_278_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}}; + assign _zz_279_ = (32'b00000000000000000001000000000000); + assign _zz_280_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000001000000000000)); + assign _zz_281_ = ((decode_INSTRUCTION & _zz_291_) == (32'b00000000000000000010000000000000)); + assign _zz_282_ = (_zz_292_ == _zz_293_); + assign _zz_283_ = {_zz_294_,{_zz_295_,_zz_296_}}; + assign _zz_284_ = ((decode_INSTRUCTION & _zz_297_) == (32'b00000000000000000000000000010000)); + assign _zz_285_ = {_zz_298_,{_zz_299_,_zz_300_}}; + assign _zz_286_ = (3'b000); + assign _zz_287_ = ({_zz_301_,_zz_302_} != (2'b00)); + assign _zz_288_ = (_zz_303_ != _zz_304_); + assign _zz_289_ = {_zz_305_,{_zz_306_,_zz_307_}}; + assign _zz_290_ = (32'b00000000000000000011000000000000); + assign _zz_291_ = (32'b00000000000000000011000000000000); + assign _zz_292_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_293_ = (32'b00000000000000000001000000010000); + assign _zz_294_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000000010000)); + assign _zz_295_ = _zz_120_; + assign _zz_296_ = {_zz_309_,_zz_310_}; + assign _zz_297_ = (32'b00000000000000000000000000010000); + assign _zz_298_ = ((decode_INSTRUCTION & _zz_311_) == (32'b00000000000000000000000001000000)); + assign _zz_299_ = (_zz_312_ == _zz_313_); + assign _zz_300_ = (_zz_314_ == _zz_315_); + assign _zz_301_ = _zz_119_; + assign _zz_302_ = (_zz_316_ == _zz_317_); + assign _zz_303_ = (_zz_318_ == _zz_319_); + assign _zz_304_ = (1'b0); + assign _zz_305_ = ({_zz_320_,_zz_321_} != (2'b00)); + assign _zz_306_ = (_zz_322_ != _zz_323_); + assign _zz_307_ = {_zz_324_,{_zz_325_,_zz_326_}}; + assign _zz_308_ = (32'b00000000000000000010000000010000); + assign _zz_309_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000)); + assign _zz_310_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_311_ = (32'b00000000000000000000000001000100); + assign _zz_312_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110000)); + assign _zz_313_ = (32'b01000000000000000000000000110000); + assign _zz_314_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); + assign _zz_315_ = (32'b00000000000000000010000000010000); + assign _zz_316_ = (decode_INSTRUCTION & (32'b00000000000000000101000000010100)); + assign _zz_317_ = (32'b00000000000000000000000000000100); + assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_319_ = (32'b00000000000000000000000001000000); + assign _zz_320_ = ((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000000000000000100)); + assign _zz_321_ = _zz_118_; + assign _zz_322_ = {(_zz_328_ == _zz_329_),_zz_118_}; + assign _zz_323_ = (2'b00); + assign _zz_324_ = ((_zz_330_ == _zz_331_) != (1'b0)); + assign _zz_325_ = ({_zz_332_,_zz_333_} != (2'b00)); + assign _zz_326_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}; + assign _zz_327_ = (32'b00000000000000000000000000010100); + assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_329_ = (32'b00000000000000000000000000000100); + assign _zz_330_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); + assign _zz_331_ = (32'b00000000000000000000000001010000); + assign _zz_332_ = _zz_116_; + assign _zz_333_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_334_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_335_ = (1'b0); + assign _zz_336_ = (((decode_INSTRUCTION & _zz_339_) == (32'b00000000000000000101000000010000)) != (1'b0)); + assign _zz_337_ = ({_zz_340_,_zz_341_} != (2'b00)); + assign _zz_338_ = {({_zz_342_,_zz_343_} != (2'b00)),{(_zz_344_ != _zz_345_),{_zz_346_,{_zz_347_,_zz_348_}}}}; + assign _zz_339_ = (32'b00000000000000000111000001010100); + assign _zz_340_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); + assign _zz_341_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_342_ = ((decode_INSTRUCTION & _zz_349_) == (32'b00000000000000000000000000100000)); + assign _zz_343_ = ((decode_INSTRUCTION & _zz_350_) == (32'b00000000000000000000000000100000)); + assign _zz_344_ = {(_zz_351_ == _zz_352_),{_zz_353_,{_zz_354_,_zz_355_}}}; + assign _zz_345_ = (4'b0000); + assign _zz_346_ = ({_zz_117_,_zz_356_} != (2'b00)); + assign _zz_347_ = ({_zz_357_,_zz_358_} != (2'b00)); + assign _zz_348_ = {(_zz_359_ != _zz_360_),{_zz_361_,{_zz_362_,_zz_363_}}}; + assign _zz_349_ = (32'b00000000000000000000000000110100); + assign _zz_350_ = (32'b00000000000000000000000001100100); + assign _zz_351_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_352_ = (32'b00000000000000000000000000000000); + assign _zz_353_ = ((decode_INSTRUCTION & _zz_364_) == (32'b00000000000000000000000000000000)); + assign _zz_354_ = (_zz_365_ == _zz_366_); + assign _zz_355_ = (_zz_367_ == _zz_368_); + assign _zz_356_ = ((decode_INSTRUCTION & _zz_369_) == (32'b00000000000000000000000000100000)); + assign _zz_357_ = _zz_117_; + assign _zz_358_ = (_zz_370_ == _zz_371_); + assign _zz_359_ = {_zz_372_,{_zz_373_,_zz_374_}}; + assign _zz_360_ = (3'b000); + assign _zz_361_ = (_zz_375_ != (1'b0)); + assign _zz_362_ = (_zz_376_ != _zz_377_); + assign _zz_363_ = {_zz_378_,{_zz_379_,_zz_380_}}; + assign _zz_364_ = (32'b00000000000000000000000000011000); + assign _zz_365_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); + assign _zz_366_ = (32'b00000000000000000010000000000000); + assign _zz_367_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_368_ = (32'b00000000000000000001000000000000); + assign _zz_369_ = (32'b00000000000000000000000001110000); + assign _zz_370_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); + assign _zz_371_ = (32'b00000000000000000000000000000000); + assign _zz_372_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); + assign _zz_373_ = ((decode_INSTRUCTION & _zz_381_) == (32'b00000000000000000100000000010000)); + assign _zz_374_ = ((decode_INSTRUCTION & _zz_382_) == (32'b00000000000000000001000000010000)); + assign _zz_375_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); + assign _zz_376_ = {(_zz_383_ == _zz_384_),(_zz_385_ == _zz_386_)}; + assign _zz_377_ = (2'b00); + assign _zz_378_ = ((_zz_387_ == _zz_388_) != (1'b0)); + assign _zz_379_ = (_zz_116_ != (1'b0)); + assign _zz_380_ = (_zz_389_ != (1'b0)); + assign _zz_381_ = (32'b00000000000000000100000000010100); + assign _zz_382_ = (32'b00000000000000000011000000010100); + assign _zz_383_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_384_ = (32'b00000000000000000010000000000000); + assign _zz_385_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); + assign _zz_386_ = (32'b00000000000000000001000000000000); + assign _zz_387_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_388_ = (32'b00000000000000000000000000000000); + assign _zz_389_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000000000000001000)); + assign _zz_390_ = execute_INSTRUCTION[31]; + assign _zz_391_ = execute_INSTRUCTION[31]; + assign _zz_392_ = execute_INSTRUCTION[7]; always @ (posedge clk) begin if(_zz_41_) begin RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data; @@ -1398,7 +1422,7 @@ module VexRiscv ( .reset(reset) ); always @(*) begin - case(_zz_254_) + case(_zz_262_) 2'b00 : begin _zz_187_ = execute_BRANCH_CALC; end @@ -2402,7 +2426,7 @@ module VexRiscv ( _zz_108_[0] = _zz_107_; end - assign _zz_71_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_106_,{{{_zz_255_,_zz_256_},_zz_257_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_108_,{{{_zz_258_,_zz_259_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_71_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_106_,{{{_zz_263_,_zz_264_},_zz_265_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_108_,{{{_zz_266_,_zz_267_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -2564,7 +2588,7 @@ module VexRiscv ( assign _zz_118_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); assign _zz_119_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); assign _zz_120_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); - assign _zz_115_ = {({(_zz_260_ == _zz_261_),(_zz_262_ == _zz_263_)} != (2'b00)),{(_zz_120_ != (1'b0)),{({_zz_264_,_zz_265_} != (2'b00)),{(_zz_266_ != _zz_267_),{_zz_268_,{_zz_269_,_zz_270_}}}}}}; + assign _zz_115_ = {({(_zz_268_ == _zz_269_),(_zz_270_ == _zz_271_)} != (2'b00)),{(_zz_120_ != (1'b0)),{({_zz_272_,_zz_273_} != (2'b00)),{(_zz_274_ != _zz_275_),{_zz_276_,{_zz_277_,_zz_278_}}}}}}; assign _zz_57_ = _zz_211_[0]; assign _zz_56_ = _zz_212_[0]; assign _zz_55_ = _zz_213_[0]; @@ -2851,7 +2875,7 @@ module VexRiscv ( end default : begin execute_BranchPlugin_branch_src1 = execute_PC; - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_150_,{{{_zz_382_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_152_,{{{_zz_383_,_zz_384_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_150_,{{{_zz_390_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_152_,{{{_zz_391_,_zz_392_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if((execute_PREDICTION_HAD_BRANCHED2 && (! execute_BranchPlugin_missAlignedTarget)))begin execute_BranchPlugin_branch_src2 = {29'd0, _zz_242_}; end @@ -3126,6 +3150,14 @@ module VexRiscv ( debug_bus_cmd_ready = _zz_86_; end end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + 6'b010011 : begin + end default : begin end endcase @@ -3143,7 +3175,7 @@ module VexRiscv ( end end - assign _zz_21_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign _zz_21_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_250_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_251_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_252_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_253_))))); assign debug_resetOut = DebugPlugin_resetIt_regNext; assign _zz_20_ = decode_SRC2_CTRL; assign _zz_18_ = _zz_52_; @@ -3176,7 +3208,7 @@ module VexRiscv ( assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_252_,_zz_166_}; + assign iBusWishbone_ADR = {_zz_260_,_zz_166_}; assign iBusWishbone_CTI = ((_zz_166_ == (3'b111)) ? (3'b111) : (3'b010)); assign iBusWishbone_BTE = (2'b00); assign iBusWishbone_SEL = (4'b1111); @@ -3219,7 +3251,7 @@ module VexRiscv ( end always @ (*) begin - dBusWishbone_SEL = _zz_253_[3:0]; + dBusWishbone_SEL = _zz_261_[3:0]; if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = (4'b1111); end @@ -3408,8 +3440,8 @@ module VexRiscv ( 12'b001100000000 : begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_246_[0]; - CsrPlugin_mstatus_MIE <= _zz_247_[0]; + CsrPlugin_mstatus_MPIE <= _zz_254_[0]; + CsrPlugin_mstatus_MIE <= _zz_255_[0]; end end 12'b001101000001 : begin @@ -3418,7 +3450,7 @@ module VexRiscv ( end 12'b001101000100 : begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_248_[0]; + CsrPlugin_mip_MSIP <= _zz_256_[0]; end end 12'b001101000011 : begin @@ -3429,9 +3461,9 @@ module VexRiscv ( end 12'b001100000100 : begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_249_[0]; - CsrPlugin_mie_MTIE <= _zz_250_[0]; - CsrPlugin_mie_MSIE <= _zz_251_[0]; + CsrPlugin_mie_MEIE <= _zz_257_[0]; + CsrPlugin_mie_MTIE <= _zz_258_[0]; + CsrPlugin_mie_MSIE <= _zz_259_[0]; end end 12'b001101000010 : begin @@ -3617,6 +3649,36 @@ module VexRiscv ( DebugPlugin_busReadDataReg <= _zz_58_; end _zz_163_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_198_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end if(_zz_194_)begin DebugPlugin_busReadDataReg <= execute_PC; end @@ -3629,6 +3691,10 @@ module VexRiscv ( DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; end else begin if(debug_bus_cmd_valid)begin case(_zz_198_) @@ -3654,6 +3720,26 @@ module VexRiscv ( end 6'b000001 : begin end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_246_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_247_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_248_[0]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_valid <= _zz_249_[0]; + end + end default : begin end endcase diff --git a/hw/2-stage-1024-cache-debug.yaml b/hw/2-stage-1024-cache-debug.yaml new file mode 100644 index 0000000..156f2e4 --- /dev/null +++ b/hw/2-stage-1024-cache-debug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} +iBus: !!vexriscv.BusReport + flushInstructions: [16399, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} + kind: cached diff --git a/hw/2-stage-no-cache-debug.v b/hw/2-stage-no-cache-debug.v new file mode 100644 index 0000000..16ac3ae --- /dev/null +++ b/hw/2-stage-no-cache-debug.v @@ -0,0 +1,3769 @@ +// Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26 +// Date : 26/03/2019, 08:00:42 +// Component : VexRiscv + + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +module InstructionCache ( + input io_flush_cmd_valid, + output io_flush_cmd_ready, + output io_flush_rsp, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_allowUser, + input io_cpu_fetch_mmuBus_rsp_miss, + input io_cpu_fetch_mmuBus_rsp_hit, + output io_cpu_fetch_mmuBus_end, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuMiss, + output io_cpu_decode_illegalAccess, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [23:0] _zz_12_; + reg [31:0] _zz_13_; + wire _zz_14_; + wire [0:0] _zz_15_; + wire [0:0] _zz_16_; + wire [23:0] _zz_17_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg [5:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_flushFromInterface; + wire _zz_4_; + reg _zz_4__regNext; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [4:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [7:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_5_; + wire [4:0] _zz_6_; + wire _zz_7_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_8_; + wire [7:0] _zz_9_; + wire _zz_10_; + wire [31:0] fetchStage_read_waysValues_0_data; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_allowUser; + reg decodeStage_mmuRsp_miss; + reg decodeStage_mmuRsp_hit; + reg decodeStage_hit_tags_0_valid; + reg decodeStage_hit_tags_0_error; + reg [21:0] decodeStage_hit_tags_0_address; + wire decodeStage_hit_hits_0; + wire decodeStage_hit_valid; + wire decodeStage_hit_error; + reg [31:0] _zz_11_; + wire [31:0] decodeStage_hit_data; + reg [31:0] decodeStage_hit_word; + reg io_cpu_fetch_dataBypassValid_regNextWhen; + reg [31:0] io_cpu_fetch_dataBypass_regNextWhen; + reg [23:0] ways_0_tags [0:31]; + reg [31:0] ways_0_datas [0:255]; + assign _zz_14_ = (! lineLoader_flushCounter[5]); + assign _zz_15_ = _zz_8_[0 : 0]; + assign _zz_16_ = _zz_8_[1 : 1]; + assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_; + end + end + + always @ (posedge clk) begin + if(_zz_7_) begin + _zz_12_ <= ways_0_tags[_zz_6_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_10_) begin + _zz_13_ <= ways_0_datas[_zz_9_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = 1'b0; + if(lineLoader_valid)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(_zz_14_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush_cmd_valid)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid)); + assign _zz_4_ = lineLoader_flushCounter[5]; + assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_5_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_6_ = io_cpu_prefetch_pc[9 : 5]; + assign _zz_7_ = (! io_cpu_fetch_isStuck); + assign _zz_8_ = _zz_12_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2]; + assign _zz_9_ = io_cpu_prefetch_pc[9 : 2]; + assign _zz_10_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_13_; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]); + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10])); + assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); + assign decodeStage_hit_error = decodeStage_hit_tags_0_error; + assign decodeStage_hit_data = _zz_11_; + always @ (*) begin + decodeStage_hit_word = decodeStage_hit_data[31 : 0]; + if(io_cpu_fetch_dataBypassValid_regNextWhen)begin + decodeStage_hit_word = io_cpu_fetch_dataBypass_regNextWhen; + end + end + + assign io_cpu_decode_data = decodeStage_hit_word; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuMiss = decodeStage_mmuRsp_miss; + assign io_cpu_decode_illegalAccess = ((! decodeStage_mmuRsp_allowExecute) || (io_cpu_decode_isUser && (! decodeStage_mmuRsp_allowUser))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushCounter <= (6'b000000); + lineLoader_flushFromInterface <= 1'b0; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(_zz_14_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); + end + if(io_flush_cmd_valid)begin + if(io_flush_cmd_ready)begin + lineLoader_flushCounter <= (6'b000000); + lineLoader_flushFromInterface <= 1'b1; + end + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + _zz_3_ <= lineLoader_flushCounter[5]; + _zz_4__regNext <= _zz_4_; + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_allowUser <= io_cpu_fetch_mmuBus_rsp_allowUser; + decodeStage_mmuRsp_miss <= io_cpu_fetch_mmuBus_rsp_miss; + decodeStage_mmuRsp_hit <= io_cpu_fetch_mmuBus_rsp_hit; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; + decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; + decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; + end + if((! io_cpu_decode_isStuck))begin + _zz_11_ <= fetchStage_read_waysValues_0_data; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_dataBypassValid_regNextWhen <= io_cpu_fetch_dataBypassValid; + end + end + + always @ (posedge clk) begin + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_dataBypass_regNextWhen <= io_cpu_fetch_dataBypass; + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset, + input debugReset); + reg _zz_169_; + wire _zz_170_; + wire _zz_171_; + wire _zz_172_; + wire _zz_173_; + wire [31:0] _zz_174_; + wire _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire _zz_180_; + wire _zz_181_; + wire _zz_182_; + wire _zz_183_; + wire _zz_184_; + reg [31:0] _zz_185_; + reg [31:0] _zz_186_; + reg [31:0] _zz_187_; + reg [3:0] _zz_188_; + reg [31:0] _zz_189_; + wire IBusCachedPlugin_cache_io_flush_cmd_ready; + wire IBusCachedPlugin_cache_io_flush_rsp; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuMiss; + wire IBusCachedPlugin_cache_io_cpu_decode_illegalAccess; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_190_; + wire _zz_191_; + wire _zz_192_; + wire _zz_193_; + wire _zz_194_; + wire _zz_195_; + wire _zz_196_; + wire _zz_197_; + wire [5:0] _zz_198_; + wire _zz_199_; + wire _zz_200_; + wire [1:0] _zz_201_; + wire [1:0] _zz_202_; + wire _zz_203_; + wire [3:0] _zz_204_; + wire [2:0] _zz_205_; + wire [31:0] _zz_206_; + wire [11:0] _zz_207_; + wire [31:0] _zz_208_; + wire [19:0] _zz_209_; + wire [11:0] _zz_210_; + wire [0:0] _zz_211_; + wire [0:0] _zz_212_; + wire [0:0] _zz_213_; + wire [0:0] _zz_214_; + wire [0:0] _zz_215_; + wire [0:0] _zz_216_; + wire [0:0] _zz_217_; + wire [0:0] _zz_218_; + wire [2:0] _zz_219_; + wire [4:0] _zz_220_; + wire [11:0] _zz_221_; + wire [11:0] _zz_222_; + wire [31:0] _zz_223_; + wire [31:0] _zz_224_; + wire [31:0] _zz_225_; + wire [31:0] _zz_226_; + wire [1:0] _zz_227_; + wire [31:0] _zz_228_; + wire [1:0] _zz_229_; + wire [1:0] _zz_230_; + wire [31:0] _zz_231_; + wire [32:0] _zz_232_; + wire [11:0] _zz_233_; + wire [19:0] _zz_234_; + wire [11:0] _zz_235_; + wire [31:0] _zz_236_; + wire [31:0] _zz_237_; + wire [31:0] _zz_238_; + wire [11:0] _zz_239_; + wire [19:0] _zz_240_; + wire [11:0] _zz_241_; + wire [2:0] _zz_242_; + wire [2:0] _zz_243_; + wire [2:0] _zz_244_; + wire [3:0] _zz_245_; + wire [0:0] _zz_246_; + wire [0:0] _zz_247_; + wire [0:0] _zz_248_; + wire [0:0] _zz_249_; + wire [30:0] _zz_250_; + wire [30:0] _zz_251_; + wire [30:0] _zz_252_; + wire [30:0] _zz_253_; + wire [0:0] _zz_254_; + wire [0:0] _zz_255_; + wire [0:0] _zz_256_; + wire [0:0] _zz_257_; + wire [0:0] _zz_258_; + wire [0:0] _zz_259_; + wire [26:0] _zz_260_; + wire [6:0] _zz_261_; + wire [1:0] _zz_262_; + wire [0:0] _zz_263_; + wire [7:0] _zz_264_; + wire _zz_265_; + wire [0:0] _zz_266_; + wire [0:0] _zz_267_; + wire [31:0] _zz_268_; + wire [31:0] _zz_269_; + wire [31:0] _zz_270_; + wire [31:0] _zz_271_; + wire [0:0] _zz_272_; + wire [0:0] _zz_273_; + wire [2:0] _zz_274_; + wire [2:0] _zz_275_; + wire _zz_276_; + wire [0:0] _zz_277_; + wire [19:0] _zz_278_; + wire [31:0] _zz_279_; + wire _zz_280_; + wire _zz_281_; + wire [0:0] _zz_282_; + wire [3:0] _zz_283_; + wire _zz_284_; + wire [2:0] _zz_285_; + wire [2:0] _zz_286_; + wire _zz_287_; + wire [0:0] _zz_288_; + wire [16:0] _zz_289_; + wire [31:0] _zz_290_; + wire [31:0] _zz_291_; + wire [31:0] _zz_292_; + wire [31:0] _zz_293_; + wire _zz_294_; + wire [0:0] _zz_295_; + wire [1:0] _zz_296_; + wire [31:0] _zz_297_; + wire _zz_298_; + wire [0:0] _zz_299_; + wire [0:0] _zz_300_; + wire [0:0] _zz_301_; + wire [0:0] _zz_302_; + wire [0:0] _zz_303_; + wire [0:0] _zz_304_; + wire _zz_305_; + wire [0:0] _zz_306_; + wire [14:0] _zz_307_; + wire [31:0] _zz_308_; + wire _zz_309_; + wire _zz_310_; + wire [31:0] _zz_311_; + wire [31:0] _zz_312_; + wire [31:0] _zz_313_; + wire [31:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire [31:0] _zz_317_; + wire [31:0] _zz_318_; + wire [31:0] _zz_319_; + wire [0:0] _zz_320_; + wire [0:0] _zz_321_; + wire [1:0] _zz_322_; + wire [1:0] _zz_323_; + wire _zz_324_; + wire [0:0] _zz_325_; + wire [12:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [31:0] _zz_329_; + wire [31:0] _zz_330_; + wire [31:0] _zz_331_; + wire [0:0] _zz_332_; + wire [0:0] _zz_333_; + wire [0:0] _zz_334_; + wire [0:0] _zz_335_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [9:0] _zz_338_; + wire [31:0] _zz_339_; + wire _zz_340_; + wire _zz_341_; + wire [0:0] _zz_342_; + wire [0:0] _zz_343_; + wire [3:0] _zz_344_; + wire [3:0] _zz_345_; + wire _zz_346_; + wire [0:0] _zz_347_; + wire [5:0] _zz_348_; + wire [31:0] _zz_349_; + wire [31:0] _zz_350_; + wire [31:0] _zz_351_; + wire [31:0] _zz_352_; + wire _zz_353_; + wire [0:0] _zz_354_; + wire [0:0] _zz_355_; + wire _zz_356_; + wire [0:0] _zz_357_; + wire [0:0] _zz_358_; + wire [2:0] _zz_359_; + wire [2:0] _zz_360_; + wire _zz_361_; + wire [0:0] _zz_362_; + wire [2:0] _zz_363_; + wire [31:0] _zz_364_; + wire [31:0] _zz_365_; + wire [31:0] _zz_366_; + wire [31:0] _zz_367_; + wire [31:0] _zz_368_; + wire [31:0] _zz_369_; + wire [31:0] _zz_370_; + wire [31:0] _zz_371_; + wire _zz_372_; + wire [0:0] _zz_373_; + wire [0:0] _zz_374_; + wire _zz_375_; + wire [1:0] _zz_376_; + wire [1:0] _zz_377_; + wire _zz_378_; + wire [0:0] _zz_379_; + wire [0:0] _zz_380_; + wire [31:0] _zz_381_; + wire [31:0] _zz_382_; + wire [31:0] _zz_383_; + wire [31:0] _zz_384_; + wire [31:0] _zz_385_; + wire [31:0] _zz_386_; + wire [31:0] _zz_387_; + wire [31:0] _zz_388_; + wire _zz_389_; + wire _zz_390_; + wire _zz_391_; + wire _zz_392_; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire decode_SRC_LESS_UNSIGNED; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_CSR_WRITE_OPCODE; + wire execute_REGFILE_WRITE_VALID; + wire decode_DO_EBREAK; + wire decode_IS_CSR; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_7_; + wire `AluCtrlEnum_defaultEncoding_type _zz_8_; + wire `AluCtrlEnum_defaultEncoding_type _zz_9_; + wire decode_CSR_READ_OPCODE; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_13_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_15_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_16_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_17_; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20_; + wire decode_SRC_USE_SUB_LESS; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire _zz_21_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire _zz_22_; + wire _zz_23_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_25_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_26_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_27_; + wire _zz_28_; + wire _zz_29_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_30_; + wire _zz_31_; + wire [31:0] _zz_32_; + wire [31:0] _zz_33_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC_USE_SUB_LESS; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_34_; + wire [31:0] _zz_35_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_36_; + wire [31:0] _zz_37_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38_; + wire [31:0] _zz_39_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40_; + reg _zz_41_; + wire [31:0] _zz_42_; + wire [31:0] _zz_43_; + reg decode_REGFILE_WRITE_VALID; + wire _zz_44_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45_; + wire _zz_46_; + wire _zz_47_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_48_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_51_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_52_; + wire `AluCtrlEnum_defaultEncoding_type _zz_53_; + wire _zz_54_; + wire _zz_55_; + wire _zz_56_; + wire _zz_57_; + reg [31:0] _zz_58_; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_MEMORY_READ_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] _zz_59_; + wire [1:0] _zz_60_; + wire [31:0] execute_RS2; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_INSTRUCTION; + wire execute_ALIGNEMENT_FAULT; + wire execute_MEMORY_ENABLE; + wire _zz_61_; + wire execute_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_62_; + reg [31:0] _zz_63_; + wire [31:0] _zz_64_; + wire [31:0] _zz_65_; + wire [31:0] _zz_66_; + wire [31:0] decode_PC /* verilator public */ ; + reg [31:0] decode_INSTRUCTION /* verilator public */ ; + reg decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + wire decode_arbitration_redoIt; + reg decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + wire execute_arbitration_redoIt; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg _zz_67_; + reg _zz_68_; + reg _zz_69_; + wire _zz_70_; + wire [31:0] _zz_71_; + wire _zz_72_; + wire _zz_73_; + wire [31:0] _zz_74_; + wire [31:0] _zz_75_; + reg _zz_76_; + wire _zz_77_; + reg _zz_78_; + reg _zz_79_; + reg [31:0] _zz_80_; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg _zz_81_; + reg [3:0] _zz_82_; + reg _zz_83_; + reg _zz_84_; + reg _zz_85_; + reg _zz_86_; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_87_; + wire [3:0] _zz_88_; + wire _zz_89_; + wire _zz_90_; + wire _zz_91_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_92_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_93_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_94_; + wire _zz_95_; + wire _zz_96_; + wire _zz_97_; + wire _zz_98_; + reg _zz_99_; + wire _zz_100_; + reg _zz_101_; + reg [31:0] _zz_102_; + wire IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_decodeRemoved; + wire _zz_103_; + reg [18:0] _zz_104_; + wire _zz_105_; + reg [10:0] _zz_106_; + wire _zz_107_; + reg [18:0] _zz_108_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + reg execute_DBusSimplePlugin_cmdSent; + reg [31:0] _zz_109_; + reg [3:0] _zz_110_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] execute_DBusSimplePlugin_rspShifted; + wire _zz_111_; + reg [31:0] _zz_112_; + wire _zz_113_; + reg [31:0] _zz_114_; + reg [31:0] execute_DBusSimplePlugin_rspFormated; + wire [25:0] _zz_115_; + wire _zz_116_; + wire _zz_117_; + wire _zz_118_; + wire _zz_119_; + wire _zz_120_; + wire `AluCtrlEnum_defaultEncoding_type _zz_121_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_122_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_123_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_124_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_125_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_126_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_127_; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire _zz_128_; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire execute_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] execute_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] execute_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_129_; + reg [31:0] _zz_130_; + wire _zz_131_; + reg [19:0] _zz_132_; + wire _zz_133_; + reg [19:0] _zz_134_; + reg [31:0] _zz_135_; + wire [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + reg [31:0] execute_LightShifterPlugin_shiftReg; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_136_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_137_; + reg _zz_138_; + reg _zz_139_; + wire _zz_140_; + reg [19:0] _zz_141_; + wire _zz_142_; + reg [10:0] _zz_143_; + wire _zz_144_; + reg [18:0] _zz_145_; + reg _zz_146_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_147_; + reg [19:0] _zz_148_; + wire _zz_149_; + reg [10:0] _zz_150_; + wire _zz_151_; + reg [18:0] _zz_152_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire [31:0] CsrPlugin_medeleg; + wire [31:0] CsrPlugin_mideleg; + wire _zz_153_; + wire _zz_154_; + wire _zz_155_; + wire CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + wire CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire execute_exception_agregat_valid; + wire [3:0] execute_exception_agregat_payload_code; + wire [31:0] execute_exception_agregat_payload_badAddr; + wire [2:0] _zz_156_; + wire [2:0] _zz_157_; + wire _zz_158_; + wire _zz_159_; + wire [1:0] _zz_160_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + wire [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_161_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_162_; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipActive; + reg DebugPlugin_isPipActive_regNext; + wire DebugPlugin_isPipBusy; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_163_; + reg DebugPlugin_resetIt_regNext; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg decode_to_execute_CSR_READ_OPCODE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_FLUSH_ALL; + reg decode_to_execute_MEMORY_ENABLE; + reg [31:0] decode_to_execute_INSTRUCTION; + reg decode_to_execute_IS_CSR; + reg decode_to_execute_DO_EBREAK; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg [31:0] decode_to_execute_PC; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [2:0] _zz_164_; + reg [31:0] _zz_165_; + reg [2:0] _zz_166_; + reg _zz_167_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_168_; + `ifndef SYNTHESIS + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_1__string; + reg [47:0] _zz_2__string; + reg [47:0] _zz_3__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_4__string; + reg [39:0] _zz_5__string; + reg [39:0] _zz_6__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_7__string; + reg [63:0] _zz_8__string; + reg [63:0] _zz_9__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_10__string; + reg [71:0] _zz_11__string; + reg [71:0] _zz_12__string; + reg [31:0] _zz_13__string; + reg [31:0] _zz_14__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_15__string; + reg [95:0] _zz_16__string; + reg [95:0] _zz_17__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18__string; + reg [23:0] _zz_19__string; + reg [23:0] _zz_20__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_24__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_27__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_30__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_34__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_36__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_40__string; + reg [39:0] _zz_45__string; + reg [31:0] _zz_48__string; + reg [95:0] _zz_49__string; + reg [47:0] _zz_50__string; + reg [71:0] _zz_51__string; + reg [23:0] _zz_52__string; + reg [63:0] _zz_53__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_62__string; + reg [63:0] _zz_121__string; + reg [23:0] _zz_122__string; + reg [71:0] _zz_123__string; + reg [47:0] _zz_124__string; + reg [95:0] _zz_125__string; + reg [31:0] _zz_126__string; + reg [39:0] _zz_127__string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_190_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_191_ = (! execute_arbitration_isStuckByOthers); + assign _zz_192_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_193_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_194_ = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_195_ = (1'b0 == 1'b0); + assign _zz_196_ = (DebugPlugin_stepIt && _zz_69_); + assign _zz_197_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_198_ = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_199_ = (iBus_cmd_valid || (_zz_166_ != (3'b000))); + assign _zz_200_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_201_ = execute_INSTRUCTION[13 : 12]; + assign _zz_202_ = execute_INSTRUCTION[29 : 28]; + assign _zz_203_ = execute_INSTRUCTION[13]; + assign _zz_204_ = (_zz_87_ - (4'b0001)); + assign _zz_205_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_206_ = {29'd0, _zz_205_}; + assign _zz_207_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_208_ = {{_zz_104_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_209_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_210_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_211_ = _zz_115_[0 : 0]; + assign _zz_212_ = _zz_115_[1 : 1]; + assign _zz_213_ = _zz_115_[2 : 2]; + assign _zz_214_ = _zz_115_[3 : 3]; + assign _zz_215_ = _zz_115_[19 : 19]; + assign _zz_216_ = _zz_115_[21 : 21]; + assign _zz_217_ = _zz_115_[25 : 25]; + assign _zz_218_ = execute_SRC_LESS; + assign _zz_219_ = (3'b100); + assign _zz_220_ = execute_INSTRUCTION[19 : 15]; + assign _zz_221_ = execute_INSTRUCTION[31 : 20]; + assign _zz_222_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_223_ = ($signed(_zz_224_) + $signed(_zz_228_)); + assign _zz_224_ = ($signed(_zz_225_) + $signed(_zz_226_)); + assign _zz_225_ = execute_SRC1; + assign _zz_226_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_227_ = (execute_SRC_USE_SUB_LESS ? _zz_229_ : _zz_230_); + assign _zz_228_ = {{30{_zz_227_[1]}}, _zz_227_}; + assign _zz_229_ = (2'b01); + assign _zz_230_ = (2'b00); + assign _zz_231_ = (_zz_232_ >>> 1); + assign _zz_232_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_233_ = execute_INSTRUCTION[31 : 20]; + assign _zz_234_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_235_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_236_ = {_zz_141_,execute_INSTRUCTION[31 : 20]}; + assign _zz_237_ = {{_zz_143_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_238_ = {{_zz_145_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_239_ = execute_INSTRUCTION[31 : 20]; + assign _zz_240_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_241_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_242_ = (3'b100); + assign _zz_243_ = (_zz_156_ - (3'b001)); + assign _zz_244_ = (execute_INSTRUCTION[5] ? (3'b110) : (3'b100)); + assign _zz_245_ = {1'd0, _zz_244_}; + assign _zz_246_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_247_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_248_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_249_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_250_ = (decode_PC >>> 1); + assign _zz_251_ = (decode_PC >>> 1); + assign _zz_252_ = (decode_PC >>> 1); + assign _zz_253_ = (decode_PC >>> 1); + assign _zz_254_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_255_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_256_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_257_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_258_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_259_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_260_ = (iBus_cmd_payload_address >>> 5); + assign _zz_261_ = ({3'd0,_zz_168_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_262_ = {_zz_91_,_zz_90_}; + assign _zz_263_ = decode_INSTRUCTION[31]; + assign _zz_264_ = decode_INSTRUCTION[19 : 12]; + assign _zz_265_ = decode_INSTRUCTION[20]; + assign _zz_266_ = decode_INSTRUCTION[31]; + assign _zz_267_ = decode_INSTRUCTION[7]; + assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_269_ = (32'b00000000000000000001000001010000); + assign _zz_270_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_271_ = (32'b00000000000000000010000001010000); + assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000001000000000000)); + assign _zz_273_ = _zz_117_; + assign _zz_274_ = {_zz_117_,{_zz_280_,_zz_281_}}; + assign _zz_275_ = (3'b000); + assign _zz_276_ = ({_zz_119_,{_zz_282_,_zz_283_}} != (6'b000000)); + assign _zz_277_ = (_zz_284_ != (1'b0)); + assign _zz_278_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}}; + assign _zz_279_ = (32'b00000000000000000001000000000000); + assign _zz_280_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000001000000000000)); + assign _zz_281_ = ((decode_INSTRUCTION & _zz_291_) == (32'b00000000000000000010000000000000)); + assign _zz_282_ = (_zz_292_ == _zz_293_); + assign _zz_283_ = {_zz_294_,{_zz_295_,_zz_296_}}; + assign _zz_284_ = ((decode_INSTRUCTION & _zz_297_) == (32'b00000000000000000000000000010000)); + assign _zz_285_ = {_zz_298_,{_zz_299_,_zz_300_}}; + assign _zz_286_ = (3'b000); + assign _zz_287_ = ({_zz_301_,_zz_302_} != (2'b00)); + assign _zz_288_ = (_zz_303_ != _zz_304_); + assign _zz_289_ = {_zz_305_,{_zz_306_,_zz_307_}}; + assign _zz_290_ = (32'b00000000000000000011000000000000); + assign _zz_291_ = (32'b00000000000000000011000000000000); + assign _zz_292_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_293_ = (32'b00000000000000000001000000010000); + assign _zz_294_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000000010000)); + assign _zz_295_ = _zz_120_; + assign _zz_296_ = {_zz_309_,_zz_310_}; + assign _zz_297_ = (32'b00000000000000000000000000010000); + assign _zz_298_ = ((decode_INSTRUCTION & _zz_311_) == (32'b00000000000000000000000001000000)); + assign _zz_299_ = (_zz_312_ == _zz_313_); + assign _zz_300_ = (_zz_314_ == _zz_315_); + assign _zz_301_ = _zz_119_; + assign _zz_302_ = (_zz_316_ == _zz_317_); + assign _zz_303_ = (_zz_318_ == _zz_319_); + assign _zz_304_ = (1'b0); + assign _zz_305_ = ({_zz_320_,_zz_321_} != (2'b00)); + assign _zz_306_ = (_zz_322_ != _zz_323_); + assign _zz_307_ = {_zz_324_,{_zz_325_,_zz_326_}}; + assign _zz_308_ = (32'b00000000000000000010000000010000); + assign _zz_309_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000)); + assign _zz_310_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_311_ = (32'b00000000000000000000000001000100); + assign _zz_312_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110000)); + assign _zz_313_ = (32'b01000000000000000000000000110000); + assign _zz_314_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); + assign _zz_315_ = (32'b00000000000000000010000000010000); + assign _zz_316_ = (decode_INSTRUCTION & (32'b00000000000000000101000000010100)); + assign _zz_317_ = (32'b00000000000000000000000000000100); + assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_319_ = (32'b00000000000000000000000001000000); + assign _zz_320_ = ((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000000000000000100)); + assign _zz_321_ = _zz_118_; + assign _zz_322_ = {(_zz_328_ == _zz_329_),_zz_118_}; + assign _zz_323_ = (2'b00); + assign _zz_324_ = ((_zz_330_ == _zz_331_) != (1'b0)); + assign _zz_325_ = ({_zz_332_,_zz_333_} != (2'b00)); + assign _zz_326_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}; + assign _zz_327_ = (32'b00000000000000000000000000010100); + assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_329_ = (32'b00000000000000000000000000000100); + assign _zz_330_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); + assign _zz_331_ = (32'b00000000000000000000000001010000); + assign _zz_332_ = _zz_116_; + assign _zz_333_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_334_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_335_ = (1'b0); + assign _zz_336_ = (((decode_INSTRUCTION & _zz_339_) == (32'b00000000000000000101000000010000)) != (1'b0)); + assign _zz_337_ = ({_zz_340_,_zz_341_} != (2'b00)); + assign _zz_338_ = {({_zz_342_,_zz_343_} != (2'b00)),{(_zz_344_ != _zz_345_),{_zz_346_,{_zz_347_,_zz_348_}}}}; + assign _zz_339_ = (32'b00000000000000000111000001010100); + assign _zz_340_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); + assign _zz_341_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_342_ = ((decode_INSTRUCTION & _zz_349_) == (32'b00000000000000000000000000100000)); + assign _zz_343_ = ((decode_INSTRUCTION & _zz_350_) == (32'b00000000000000000000000000100000)); + assign _zz_344_ = {(_zz_351_ == _zz_352_),{_zz_353_,{_zz_354_,_zz_355_}}}; + assign _zz_345_ = (4'b0000); + assign _zz_346_ = ({_zz_117_,_zz_356_} != (2'b00)); + assign _zz_347_ = ({_zz_357_,_zz_358_} != (2'b00)); + assign _zz_348_ = {(_zz_359_ != _zz_360_),{_zz_361_,{_zz_362_,_zz_363_}}}; + assign _zz_349_ = (32'b00000000000000000000000000110100); + assign _zz_350_ = (32'b00000000000000000000000001100100); + assign _zz_351_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_352_ = (32'b00000000000000000000000000000000); + assign _zz_353_ = ((decode_INSTRUCTION & _zz_364_) == (32'b00000000000000000000000000000000)); + assign _zz_354_ = (_zz_365_ == _zz_366_); + assign _zz_355_ = (_zz_367_ == _zz_368_); + assign _zz_356_ = ((decode_INSTRUCTION & _zz_369_) == (32'b00000000000000000000000000100000)); + assign _zz_357_ = _zz_117_; + assign _zz_358_ = (_zz_370_ == _zz_371_); + assign _zz_359_ = {_zz_372_,{_zz_373_,_zz_374_}}; + assign _zz_360_ = (3'b000); + assign _zz_361_ = (_zz_375_ != (1'b0)); + assign _zz_362_ = (_zz_376_ != _zz_377_); + assign _zz_363_ = {_zz_378_,{_zz_379_,_zz_380_}}; + assign _zz_364_ = (32'b00000000000000000000000000011000); + assign _zz_365_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); + assign _zz_366_ = (32'b00000000000000000010000000000000); + assign _zz_367_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_368_ = (32'b00000000000000000001000000000000); + assign _zz_369_ = (32'b00000000000000000000000001110000); + assign _zz_370_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); + assign _zz_371_ = (32'b00000000000000000000000000000000); + assign _zz_372_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); + assign _zz_373_ = ((decode_INSTRUCTION & _zz_381_) == (32'b00000000000000000100000000010000)); + assign _zz_374_ = ((decode_INSTRUCTION & _zz_382_) == (32'b00000000000000000001000000010000)); + assign _zz_375_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); + assign _zz_376_ = {(_zz_383_ == _zz_384_),(_zz_385_ == _zz_386_)}; + assign _zz_377_ = (2'b00); + assign _zz_378_ = ((_zz_387_ == _zz_388_) != (1'b0)); + assign _zz_379_ = (_zz_116_ != (1'b0)); + assign _zz_380_ = (_zz_389_ != (1'b0)); + assign _zz_381_ = (32'b00000000000000000100000000010100); + assign _zz_382_ = (32'b00000000000000000011000000010100); + assign _zz_383_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_384_ = (32'b00000000000000000010000000000000); + assign _zz_385_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); + assign _zz_386_ = (32'b00000000000000000001000000000000); + assign _zz_387_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_388_ = (32'b00000000000000000000000000000000); + assign _zz_389_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000000000000001000)); + assign _zz_390_ = execute_INSTRUCTION[31]; + assign _zz_391_ = execute_INSTRUCTION[31]; + assign _zz_392_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_41_) begin + RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_128_) begin + _zz_185_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_128_) begin + _zz_186_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush_cmd_valid(_zz_169_), + .io_flush_cmd_ready(IBusCachedPlugin_cache_io_flush_cmd_ready), + .io_flush_rsp(IBusCachedPlugin_cache_io_flush_rsp), + .io_cpu_prefetch_isValid(_zz_170_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_171_), + .io_cpu_fetch_isStuck(_zz_172_), + .io_cpu_fetch_isRemoved(_zz_173_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_174_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(_zz_75_), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_175_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_176_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_177_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_178_), + .io_cpu_fetch_mmuBus_rsp_allowUser(_zz_179_), + .io_cpu_fetch_mmuBus_rsp_miss(_zz_180_), + .io_cpu_fetch_mmuBus_rsp_hit(_zz_181_), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_decode_isValid(_zz_182_), + .io_cpu_decode_isStuck(_zz_183_), + .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), + .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), + .io_cpu_decode_mmuMiss(IBusCachedPlugin_cache_io_cpu_decode_mmuMiss), + .io_cpu_decode_illegalAccess(IBusCachedPlugin_cache_io_cpu_decode_illegalAccess), + .io_cpu_decode_isUser(_zz_184_), + .io_cpu_fill_valid(IBusCachedPlugin_rsp_redoFetch), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_262_) + 2'b00 : begin + _zz_187_ = execute_BRANCH_CALC; + end + 2'b01 : begin + _zz_187_ = _zz_80_; + end + 2'b10 : begin + _zz_187_ = _zz_74_; + end + default : begin + _zz_187_ = _zz_71_; + end + endcase + end + + always @(*) begin + case(_zz_160_) + 2'b00 : begin + _zz_188_ = _zz_245_; + _zz_189_ = execute_REGFILE_WRITE_DATA; + end + 2'b01 : begin + _zz_188_ = (4'b0000); + _zz_189_ = execute_BRANCH_CALC; + end + default : begin + _zz_188_ = _zz_82_; + _zz_189_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_1_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_1__string = "EBREAK"; + default : _zz_1__string = "??????"; + endcase + end + always @(*) begin + case(_zz_2_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_2__string = "EBREAK"; + default : _zz_2__string = "??????"; + endcase + end + always @(*) begin + case(_zz_3_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_3__string = "EBREAK"; + default : _zz_3__string = "??????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_4__string = "SRC1 "; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_5__string = "SRC1 "; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_6__string = "SRC1 "; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_7_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_7__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_7__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_7__string = "BITWISE "; + default : _zz_7__string = "????????"; + endcase + end + always @(*) begin + case(_zz_8_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE "; + default : _zz_8__string = "????????"; + endcase + end + always @(*) begin + case(_zz_9_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; + default : _zz_9__string = "????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_10_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10__string = "SRA_1 "; + default : _zz_10__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11__string = "SRA_1 "; + default : _zz_11__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12__string = "SRA_1 "; + default : _zz_12__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR"; + default : _zz_13__string = "????"; + endcase + end + always @(*) begin + case(_zz_14_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; + default : _zz_14__string = "????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_15__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_15__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_15__string = "URS1 "; + default : _zz_15__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_16_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_16__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_16__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_16__string = "URS1 "; + default : _zz_16__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_17__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_17__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_17__string = "URS1 "; + default : _zz_17__string = "????????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_18_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18__string = "PC "; + default : _zz_18__string = "???"; + endcase + end + always @(*) begin + case(_zz_19_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19__string = "PC "; + default : _zz_19__string = "???"; + endcase + end + always @(*) begin + case(_zz_20_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20__string = "PC "; + default : _zz_20__string = "???"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_24_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_24__string = "EBREAK"; + default : _zz_24__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_27_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_27__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_27__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_27__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_27__string = "JALR"; + default : _zz_27__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_30_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_30__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_30__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_30__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_30__string = "SRA_1 "; + default : _zz_30__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_34_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_34__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_34__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_34__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_34__string = "PC "; + default : _zz_34__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_36_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_36__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_36__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_36__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_36__string = "URS1 "; + default : _zz_36__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_38_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38__string = "BITWISE "; + default : _zz_38__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_40_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_40__string = "SRC1 "; + default : _zz_40__string = "?????"; + endcase + end + always @(*) begin + case(_zz_45_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_45__string = "SRC1 "; + default : _zz_45__string = "?????"; + endcase + end + always @(*) begin + case(_zz_48_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_48__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_48__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_48__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_48__string = "JALR"; + default : _zz_48__string = "????"; + endcase + end + always @(*) begin + case(_zz_49_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49__string = "URS1 "; + default : _zz_49__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_50_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_50__string = "EBREAK"; + default : _zz_50__string = "??????"; + endcase + end + always @(*) begin + case(_zz_51_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_51__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_51__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_51__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_51__string = "SRA_1 "; + default : _zz_51__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_52_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_52__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_52__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_52__string = "PC "; + default : _zz_52__string = "???"; + endcase + end + always @(*) begin + case(_zz_53_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53__string = "BITWISE "; + default : _zz_53__string = "????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_62_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_62__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_62__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_62__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_62__string = "JALR"; + default : _zz_62__string = "????"; + endcase + end + always @(*) begin + case(_zz_121_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE "; + default : _zz_121__string = "????????"; + endcase + end + always @(*) begin + case(_zz_122_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_122__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_122__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_122__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_122__string = "PC "; + default : _zz_122__string = "???"; + endcase + end + always @(*) begin + case(_zz_123_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_123__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_123__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_123__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_123__string = "SRA_1 "; + default : _zz_123__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_124_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_124__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_124__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_124__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_124__string = "EBREAK"; + default : _zz_124__string = "??????"; + endcase + end + always @(*) begin + case(_zz_125_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_125__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_125__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_125__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_125__string = "URS1 "; + default : _zz_125__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_126_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_126__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_126__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_126__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_126__string = "JALR"; + default : _zz_126__string = "????"; + endcase + end + always @(*) begin + case(_zz_127_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_127__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_127__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_127__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_127__string = "SRC1 "; + default : _zz_127__string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_to_execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + `endif + + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_64_; + assign decode_SRC_LESS_UNSIGNED = _zz_54_; + assign decode_ENV_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_ALU_BITWISE_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_29_; + assign decode_CSR_WRITE_OPCODE = _zz_23_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign decode_DO_EBREAK = _zz_21_; + assign decode_IS_CSR = _zz_44_; + assign decode_MEMORY_ENABLE = _zz_55_; + assign decode_FLUSH_ALL = _zz_57_; + assign decode_ALU_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_CSR_READ_OPCODE = _zz_22_; + assign decode_SHIFT_CTRL = _zz_10_; + assign _zz_11_ = _zz_12_; + assign _zz_13_ = _zz_14_; + assign decode_SRC1_CTRL = _zz_15_; + assign _zz_16_ = _zz_17_; + assign decode_SRC2_CTRL = _zz_18_; + assign _zz_19_ = _zz_20_; + assign decode_SRC_USE_SUB_LESS = _zz_47_; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_56_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign execute_ENV_CTRL = _zz_24_; + assign execute_BRANCH_CALC = _zz_25_; + assign execute_BRANCH_DO = _zz_26_; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = _zz_43_; + assign execute_BRANCH_COND_RESULT = _zz_28_; + assign execute_BRANCH_CTRL = _zz_27_; + assign execute_SHIFT_CTRL = _zz_30_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign execute_SRC2_CTRL = _zz_34_; + assign execute_SRC1_CTRL = _zz_36_; + assign execute_SRC_ADD_SUB = _zz_33_; + assign execute_SRC_LESS = _zz_31_; + assign execute_ALU_CTRL = _zz_38_; + assign execute_SRC2 = _zz_35_; + assign execute_SRC1 = _zz_37_; + assign execute_ALU_BITWISE_CTRL = _zz_40_; + always @ (*) begin + _zz_41_ = 1'b0; + if(execute_RegFilePlugin_regFileWrite_valid)begin + _zz_41_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_46_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_58_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + _zz_169_ = 1'b0; + if((execute_arbitration_isValid && execute_FLUSH_ALL))begin + _zz_169_ = 1'b1; + if((! IBusCachedPlugin_cache_io_flush_cmd_ready))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin + _zz_58_ = execute_DBusSimplePlugin_rspFormated; + end + if(_zz_190_)begin + _zz_58_ = _zz_136_; + if(_zz_191_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_58_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_MEMORY_ADDRESS_LOW = _zz_60_; + assign execute_MEMORY_READ_DATA = _zz_59_; + assign execute_REGFILE_WRITE_DATA = _zz_39_; + assign execute_RS2 = _zz_42_; + assign execute_SRC_ADD = _zz_32_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_ALIGNEMENT_FAULT = _zz_61_; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_FLUSH_ALL = decode_to_execute_FLUSH_ALL; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(((_zz_182_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! 1'b0)))begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_redoFetch = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + assign decode_BRANCH_CTRL = _zz_62_; + always @ (*) begin + _zz_63_ = decode_FORMAL_PC_NEXT; + if(_zz_70_)begin + _zz_63_ = _zz_71_; + end + if(_zz_73_)begin + _zz_63_ = _zz_74_; + end + end + + assign decode_PC = _zz_66_; + always @ (*) begin + decode_INSTRUCTION = _zz_65_; + if((_zz_164_ != (3'b000)))begin + decode_INSTRUCTION = _zz_165_; + end + end + + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + _zz_86_ = 1'b0; + case(_zz_164_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + _zz_86_ = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((CsrPlugin_interrupt && decode_arbitration_isValid))begin + decode_arbitration_haltByOther = 1'b1; + end + if(1'b0)begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_removeIt = 1'b0; + _zz_79_ = 1'b0; + _zz_80_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_77_)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_exception_agregat_valid)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(_zz_192_)begin + _zz_79_ = 1'b1; + _zz_80_ = {CsrPlugin_mtvec_base,(2'b00)}; + decode_arbitration_flushAll = 1'b1; + end + if(_zz_193_)begin + _zz_80_ = CsrPlugin_mepc; + _zz_79_ = 1'b1; + decode_arbitration_flushAll = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_redoIt = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + _zz_67_ = 1'b0; + _zz_68_ = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin + _zz_67_ = 1'b1; + end + if(_zz_194_)begin + execute_arbitration_haltByOther = 1'b1; + if(_zz_195_)begin + _zz_68_ = 1'b1; + _zz_67_ = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + _zz_67_ = 1'b1; + end + if(_zz_196_)begin + _zz_67_ = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(_zz_194_)begin + if(_zz_195_)begin + execute_arbitration_flushAll = 1'b1; + end + end + end + + assign execute_arbitration_redoIt = 1'b0; + always @ (*) begin + _zz_69_ = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + _zz_69_ = 1'b1; + end + end + + always @ (*) begin + _zz_83_ = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + _zz_83_ = 1'b0; + end + end + + always @ (*) begin + _zz_84_ = 1'b1; + if(DebugPlugin_haltIt)begin + _zz_84_ = 1'b0; + end + end + + assign IBusCachedPlugin_jump_pcLoad_valid = ({_zz_79_,{_zz_77_,{_zz_73_,_zz_70_}}} != (4'b0000)); + assign _zz_87_ = {_zz_70_,{_zz_73_,{_zz_79_,_zz_77_}}}; + assign _zz_88_ = (_zz_87_ & (~ _zz_204_)); + assign _zz_89_ = _zz_88_[3]; + assign _zz_90_ = (_zz_88_[1] || _zz_89_); + assign _zz_91_ = (_zz_88_[2] || _zz_89_); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_187_; + assign _zz_92_ = (! _zz_67_); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_92_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_92_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid && IBusCachedPlugin_iBusRsp_stages_1_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_206_); + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + if(_zz_197_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_93_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_94_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_94_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_94_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(((IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid && (! 1'b1)) && (! 1'b0)))begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_95_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_95_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_95_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_96_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_96_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_96_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_97_; + assign _zz_97_ = ((1'b0 && (! _zz_98_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_98_ = _zz_99_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_98_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_100_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_100_ = _zz_101_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_100_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_102_; + assign IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign _zz_66_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_65_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_64_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_103_ = _zz_207_[11]; + always @ (*) begin + _zz_104_[18] = _zz_103_; + _zz_104_[17] = _zz_103_; + _zz_104_[16] = _zz_103_; + _zz_104_[15] = _zz_103_; + _zz_104_[14] = _zz_103_; + _zz_104_[13] = _zz_103_; + _zz_104_[12] = _zz_103_; + _zz_104_[11] = _zz_103_; + _zz_104_[10] = _zz_103_; + _zz_104_[9] = _zz_103_; + _zz_104_[8] = _zz_103_; + _zz_104_[7] = _zz_103_; + _zz_104_[6] = _zz_103_; + _zz_104_[5] = _zz_103_; + _zz_104_[4] = _zz_103_; + _zz_104_[3] = _zz_103_; + _zz_104_[2] = _zz_103_; + _zz_104_[1] = _zz_103_; + _zz_104_[0] = _zz_103_; + end + + assign _zz_72_ = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_208_[31])); + assign _zz_70_ = (_zz_72_ && decode_arbitration_isFiring); + assign _zz_105_ = _zz_209_[19]; + always @ (*) begin + _zz_106_[10] = _zz_105_; + _zz_106_[9] = _zz_105_; + _zz_106_[8] = _zz_105_; + _zz_106_[7] = _zz_105_; + _zz_106_[6] = _zz_105_; + _zz_106_[5] = _zz_105_; + _zz_106_[4] = _zz_105_; + _zz_106_[3] = _zz_105_; + _zz_106_[2] = _zz_105_; + _zz_106_[1] = _zz_105_; + _zz_106_[0] = _zz_105_; + end + + assign _zz_107_ = _zz_210_[11]; + always @ (*) begin + _zz_108_[18] = _zz_107_; + _zz_108_[17] = _zz_107_; + _zz_108_[16] = _zz_107_; + _zz_108_[15] = _zz_107_; + _zz_108_[14] = _zz_107_; + _zz_108_[13] = _zz_107_; + _zz_108_[12] = _zz_107_; + _zz_108_[11] = _zz_107_; + _zz_108_[10] = _zz_107_; + _zz_108_[9] = _zz_107_; + _zz_108_[8] = _zz_107_; + _zz_108_[7] = _zz_107_; + _zz_108_[6] = _zz_107_; + _zz_108_[5] = _zz_107_; + _zz_108_[4] = _zz_107_; + _zz_108_[3] = _zz_107_; + _zz_108_[2] = _zz_107_; + _zz_108_[1] = _zz_107_; + _zz_108_[0] = _zz_107_; + end + + assign _zz_71_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_106_,{{{_zz_263_,_zz_264_},_zz_265_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_108_,{{{_zz_266_,_zz_267_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_170_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_173_ = (IBusCachedPlugin_jump_pcLoad_valid || _zz_68_); + assign _zz_174_ = (32'b00000000000000000000000000000000); + assign _zz_171_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_172_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_182_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_183_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_184_ = (CsrPlugin_privilege == (2'b00)); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign _zz_73_ = IBusCachedPlugin_rsp_redoFetch; + assign _zz_74_ = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign _zz_175_ = _zz_75_[31]; + assign _zz_176_ = 1'b1; + assign _zz_177_ = 1'b1; + assign _zz_178_ = 1'b1; + assign _zz_179_ = 1'b1; + assign _zz_180_ = 1'b0; + assign _zz_181_ = 1'b1; + assign _zz_61_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_INSTRUCTION[5]; + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_109_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_109_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_109_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_109_; + assign _zz_60_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_110_ = (4'b0001); + end + 2'b01 : begin + _zz_110_ = (4'b0011); + end + default : begin + _zz_110_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_110_ <<< dBus_cmd_payload_address[1 : 0]); + assign _zz_59_ = dBus_rsp_data; + always @ (*) begin + _zz_76_ = execute_ALIGNEMENT_FAULT; + if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers))))begin + _zz_76_ = 1'b0; + end + end + + always @ (*) begin + execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; + case(execute_MEMORY_ADDRESS_LOW) + 2'b01 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_111_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_112_[31] = _zz_111_; + _zz_112_[30] = _zz_111_; + _zz_112_[29] = _zz_111_; + _zz_112_[28] = _zz_111_; + _zz_112_[27] = _zz_111_; + _zz_112_[26] = _zz_111_; + _zz_112_[25] = _zz_111_; + _zz_112_[24] = _zz_111_; + _zz_112_[23] = _zz_111_; + _zz_112_[22] = _zz_111_; + _zz_112_[21] = _zz_111_; + _zz_112_[20] = _zz_111_; + _zz_112_[19] = _zz_111_; + _zz_112_[18] = _zz_111_; + _zz_112_[17] = _zz_111_; + _zz_112_[16] = _zz_111_; + _zz_112_[15] = _zz_111_; + _zz_112_[14] = _zz_111_; + _zz_112_[13] = _zz_111_; + _zz_112_[12] = _zz_111_; + _zz_112_[11] = _zz_111_; + _zz_112_[10] = _zz_111_; + _zz_112_[9] = _zz_111_; + _zz_112_[8] = _zz_111_; + _zz_112_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_113_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_114_[31] = _zz_113_; + _zz_114_[30] = _zz_113_; + _zz_114_[29] = _zz_113_; + _zz_114_[28] = _zz_113_; + _zz_114_[27] = _zz_113_; + _zz_114_[26] = _zz_113_; + _zz_114_[25] = _zz_113_; + _zz_114_[24] = _zz_113_; + _zz_114_[23] = _zz_113_; + _zz_114_[22] = _zz_113_; + _zz_114_[21] = _zz_113_; + _zz_114_[20] = _zz_113_; + _zz_114_[19] = _zz_113_; + _zz_114_[18] = _zz_113_; + _zz_114_[17] = _zz_113_; + _zz_114_[16] = _zz_113_; + _zz_114_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_201_) + 2'b00 : begin + execute_DBusSimplePlugin_rspFormated = _zz_112_; + end + 2'b01 : begin + execute_DBusSimplePlugin_rspFormated = _zz_114_; + end + default : begin + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_75_ = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign _zz_116_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_118_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_119_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_120_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_115_ = {({(_zz_268_ == _zz_269_),(_zz_270_ == _zz_271_)} != (2'b00)),{(_zz_120_ != (1'b0)),{({_zz_272_,_zz_273_} != (2'b00)),{(_zz_274_ != _zz_275_),{_zz_276_,{_zz_277_,_zz_278_}}}}}}; + assign _zz_57_ = _zz_211_[0]; + assign _zz_56_ = _zz_212_[0]; + assign _zz_55_ = _zz_213_[0]; + assign _zz_54_ = _zz_214_[0]; + assign _zz_121_ = _zz_115_[5 : 4]; + assign _zz_53_ = _zz_121_; + assign _zz_122_ = _zz_115_[7 : 6]; + assign _zz_52_ = _zz_122_; + assign _zz_123_ = _zz_115_[11 : 10]; + assign _zz_51_ = _zz_123_; + assign _zz_124_ = _zz_115_[14 : 13]; + assign _zz_50_ = _zz_124_; + assign _zz_125_ = _zz_115_[16 : 15]; + assign _zz_49_ = _zz_125_; + assign _zz_126_ = _zz_115_[18 : 17]; + assign _zz_48_ = _zz_126_; + assign _zz_47_ = _zz_215_[0]; + assign _zz_46_ = _zz_216_[0]; + assign _zz_127_ = _zz_115_[23 : 22]; + assign _zz_45_ = _zz_127_; + assign _zz_44_ = _zz_217_[0]; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_128_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_185_; + assign execute_RegFilePlugin_rs2Data = _zz_186_; + assign _zz_43_ = execute_RegFilePlugin_rs1Data; + assign _zz_42_ = execute_RegFilePlugin_rs2Data; + assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); + assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; + assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_58_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = execute_SRC1; + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_129_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_129_ = {31'd0, _zz_218_}; + end + default : begin + _zz_129_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_39_ = _zz_129_; + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_130_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_130_ = {29'd0, _zz_219_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_130_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_130_ = {27'd0, _zz_220_}; + end + endcase + end + + assign _zz_37_ = _zz_130_; + assign _zz_131_ = _zz_221_[11]; + always @ (*) begin + _zz_132_[19] = _zz_131_; + _zz_132_[18] = _zz_131_; + _zz_132_[17] = _zz_131_; + _zz_132_[16] = _zz_131_; + _zz_132_[15] = _zz_131_; + _zz_132_[14] = _zz_131_; + _zz_132_[13] = _zz_131_; + _zz_132_[12] = _zz_131_; + _zz_132_[11] = _zz_131_; + _zz_132_[10] = _zz_131_; + _zz_132_[9] = _zz_131_; + _zz_132_[8] = _zz_131_; + _zz_132_[7] = _zz_131_; + _zz_132_[6] = _zz_131_; + _zz_132_[5] = _zz_131_; + _zz_132_[4] = _zz_131_; + _zz_132_[3] = _zz_131_; + _zz_132_[2] = _zz_131_; + _zz_132_[1] = _zz_131_; + _zz_132_[0] = _zz_131_; + end + + assign _zz_133_ = _zz_222_[11]; + always @ (*) begin + _zz_134_[19] = _zz_133_; + _zz_134_[18] = _zz_133_; + _zz_134_[17] = _zz_133_; + _zz_134_[16] = _zz_133_; + _zz_134_[15] = _zz_133_; + _zz_134_[14] = _zz_133_; + _zz_134_[13] = _zz_133_; + _zz_134_[12] = _zz_133_; + _zz_134_[11] = _zz_133_; + _zz_134_[10] = _zz_133_; + _zz_134_[9] = _zz_133_; + _zz_134_[8] = _zz_133_; + _zz_134_[7] = _zz_133_; + _zz_134_[6] = _zz_133_; + _zz_134_[5] = _zz_133_; + _zz_134_[4] = _zz_133_; + _zz_134_[3] = _zz_133_; + _zz_134_[2] = _zz_133_; + _zz_134_[1] = _zz_133_; + _zz_134_[0] = _zz_133_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_135_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_135_ = {_zz_132_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_135_ = {_zz_134_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_135_ = execute_PC; + end + endcase + end + + assign _zz_35_ = _zz_135_; + assign execute_SrcPlugin_addSub = _zz_223_; + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_33_ = execute_SrcPlugin_addSub; + assign _zz_32_ = execute_SrcPlugin_addSub; + assign _zz_31_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_136_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_136_ = _zz_231_; + end + endcase + end + + assign _zz_29_ = _zz_72_; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_137_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_137_ == (3'b000))) begin + _zz_138_ = execute_BranchPlugin_eq; + end else if((_zz_137_ == (3'b001))) begin + _zz_138_ = (! execute_BranchPlugin_eq); + end else if((((_zz_137_ & (3'b101)) == (3'b101)))) begin + _zz_138_ = (! execute_SRC_LESS); + end else begin + _zz_138_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_139_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_139_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_139_ = 1'b1; + end + default : begin + _zz_139_ = _zz_138_; + end + endcase + end + + assign _zz_28_ = _zz_139_; + assign _zz_140_ = _zz_233_[11]; + always @ (*) begin + _zz_141_[19] = _zz_140_; + _zz_141_[18] = _zz_140_; + _zz_141_[17] = _zz_140_; + _zz_141_[16] = _zz_140_; + _zz_141_[15] = _zz_140_; + _zz_141_[14] = _zz_140_; + _zz_141_[13] = _zz_140_; + _zz_141_[12] = _zz_140_; + _zz_141_[11] = _zz_140_; + _zz_141_[10] = _zz_140_; + _zz_141_[9] = _zz_140_; + _zz_141_[8] = _zz_140_; + _zz_141_[7] = _zz_140_; + _zz_141_[6] = _zz_140_; + _zz_141_[5] = _zz_140_; + _zz_141_[4] = _zz_140_; + _zz_141_[3] = _zz_140_; + _zz_141_[2] = _zz_140_; + _zz_141_[1] = _zz_140_; + _zz_141_[0] = _zz_140_; + end + + assign _zz_142_ = _zz_234_[19]; + always @ (*) begin + _zz_143_[10] = _zz_142_; + _zz_143_[9] = _zz_142_; + _zz_143_[8] = _zz_142_; + _zz_143_[7] = _zz_142_; + _zz_143_[6] = _zz_142_; + _zz_143_[5] = _zz_142_; + _zz_143_[4] = _zz_142_; + _zz_143_[3] = _zz_142_; + _zz_143_[2] = _zz_142_; + _zz_143_[1] = _zz_142_; + _zz_143_[0] = _zz_142_; + end + + assign _zz_144_ = _zz_235_[11]; + always @ (*) begin + _zz_145_[18] = _zz_144_; + _zz_145_[17] = _zz_144_; + _zz_145_[16] = _zz_144_; + _zz_145_[15] = _zz_144_; + _zz_145_[14] = _zz_144_; + _zz_145_[13] = _zz_144_; + _zz_145_[12] = _zz_144_; + _zz_145_[11] = _zz_144_; + _zz_145_[10] = _zz_144_; + _zz_145_[9] = _zz_144_; + _zz_145_[8] = _zz_144_; + _zz_145_[7] = _zz_144_; + _zz_145_[6] = _zz_144_; + _zz_145_[5] = _zz_144_; + _zz_145_[4] = _zz_144_; + _zz_145_[3] = _zz_144_; + _zz_145_[2] = _zz_144_; + _zz_145_[1] = _zz_144_; + _zz_145_[0] = _zz_144_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_146_ = (_zz_236_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_146_ = _zz_237_[1]; + end + default : begin + _zz_146_ = _zz_238_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_146_); + assign _zz_26_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + execute_BranchPlugin_branch_src2 = {_zz_148_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_150_,{{{_zz_390_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_152_,{{{_zz_391_,_zz_392_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if((execute_PREDICTION_HAD_BRANCHED2 && (! execute_BranchPlugin_missAlignedTarget)))begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_242_}; + end + end + endcase + end + + assign _zz_147_ = _zz_239_[11]; + always @ (*) begin + _zz_148_[19] = _zz_147_; + _zz_148_[18] = _zz_147_; + _zz_148_[17] = _zz_147_; + _zz_148_[16] = _zz_147_; + _zz_148_[15] = _zz_147_; + _zz_148_[14] = _zz_147_; + _zz_148_[13] = _zz_147_; + _zz_148_[12] = _zz_147_; + _zz_148_[11] = _zz_147_; + _zz_148_[10] = _zz_147_; + _zz_148_[9] = _zz_147_; + _zz_148_[8] = _zz_147_; + _zz_148_[7] = _zz_147_; + _zz_148_[6] = _zz_147_; + _zz_148_[5] = _zz_147_; + _zz_148_[4] = _zz_147_; + _zz_148_[3] = _zz_147_; + _zz_148_[2] = _zz_147_; + _zz_148_[1] = _zz_147_; + _zz_148_[0] = _zz_147_; + end + + assign _zz_149_ = _zz_240_[19]; + always @ (*) begin + _zz_150_[10] = _zz_149_; + _zz_150_[9] = _zz_149_; + _zz_150_[8] = _zz_149_; + _zz_150_[7] = _zz_149_; + _zz_150_[6] = _zz_149_; + _zz_150_[5] = _zz_149_; + _zz_150_[4] = _zz_149_; + _zz_150_[3] = _zz_149_; + _zz_150_[2] = _zz_149_; + _zz_150_[1] = _zz_149_; + _zz_150_[0] = _zz_149_; + end + + assign _zz_151_ = _zz_241_[11]; + always @ (*) begin + _zz_152_[18] = _zz_151_; + _zz_152_[17] = _zz_151_; + _zz_152_[16] = _zz_151_; + _zz_152_[15] = _zz_151_; + _zz_152_[14] = _zz_151_; + _zz_152_[13] = _zz_151_; + _zz_152_[12] = _zz_151_; + _zz_152_[11] = _zz_151_; + _zz_152_[10] = _zz_151_; + _zz_152_[9] = _zz_151_; + _zz_152_[8] = _zz_151_; + _zz_152_[7] = _zz_151_; + _zz_152_[6] = _zz_151_; + _zz_152_[5] = _zz_151_; + _zz_152_[4] = _zz_151_; + _zz_152_[3] = _zz_151_; + _zz_152_[2] = _zz_151_; + _zz_152_[1] = _zz_151_; + _zz_152_[0] = _zz_151_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_25_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign _zz_77_ = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + always @ (*) begin + _zz_78_ = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + _zz_78_ = 1'b0; + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_medeleg = (32'b00000000000000000000000000000000); + assign CsrPlugin_mideleg = (32'b00000000000000000000000000000000); + assign _zz_153_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_154_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_155_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 1'b0; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = (2'b11); + assign execute_exception_agregat_valid = ({_zz_81_,{_zz_78_,_zz_76_}} != (3'b000)); + assign _zz_156_ = {_zz_81_,{_zz_78_,_zz_76_}}; + assign _zz_157_ = (_zz_156_ & (~ _zz_243_)); + assign _zz_158_ = _zz_157_[1]; + assign _zz_159_ = _zz_157_[2]; + assign _zz_160_ = {_zz_159_,_zz_158_}; + assign execute_exception_agregat_payload_code = _zz_188_; + assign execute_exception_agregat_payload_badAddr = _zz_189_; + assign CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + if(CsrPlugin_mstatus_MIE)begin + if(({_zz_155_,{_zz_154_,_zz_153_}} != (3'b000)))begin + CsrPlugin_interrupt = 1'b1; + end + if(_zz_153_)begin + CsrPlugin_interruptCode = (4'b0111); + end + if(_zz_154_)begin + CsrPlugin_interruptCode = (4'b0011); + end + if(_zz_155_)begin + CsrPlugin_interruptCode = (4'b1011); + end + end + if((! _zz_83_))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_interruptTargetPrivilege = (2'b11); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && _zz_84_); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_injector_nextPcCalc_valids_2); + if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + assign contextSwitching = _zz_79_; + assign _zz_23_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_22_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_blockedBySideEffects = 1'b0; + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_161_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_162_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((execute_INSTRUCTION[29 : 28] != CsrPlugin_privilege))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + _zz_81_ = 1'b0; + _zz_82_ = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + _zz_81_ = 1'b1; + _zz_82_ = (4'b1011); + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + _zz_81_ = 1'b1; + _zz_82_ = (4'b0011); + end + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + case(_zz_203_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readData & (~ execute_SRC1)) : (execute_CsrPlugin_readData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_162_ = (_zz_161_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_162_ != (32'b00000000000000000000000000000000)); + assign DebugPlugin_isPipBusy = (DebugPlugin_isPipActive || DebugPlugin_isPipActive_regNext); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + _zz_85_ = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_198_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + _zz_85_ = 1'b1; + debug_bus_cmd_ready = _zz_86_; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + 6'b010011 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_163_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign _zz_21_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_250_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_251_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_252_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_253_))))); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_20_ = decode_SRC2_CTRL; + assign _zz_18_ = _zz_52_; + assign _zz_34_ = decode_to_execute_SRC2_CTRL; + assign _zz_17_ = decode_SRC1_CTRL; + assign _zz_15_ = _zz_49_; + assign _zz_36_ = decode_to_execute_SRC1_CTRL; + assign _zz_14_ = decode_BRANCH_CTRL; + assign _zz_62_ = _zz_48_; + assign _zz_27_ = decode_to_execute_BRANCH_CTRL; + assign _zz_12_ = decode_SHIFT_CTRL; + assign _zz_10_ = _zz_51_; + assign _zz_30_ = decode_to_execute_SHIFT_CTRL; + assign _zz_9_ = decode_ALU_CTRL; + assign _zz_7_ = _zz_53_; + assign _zz_38_ = decode_to_execute_ALU_CTRL; + assign _zz_6_ = decode_ALU_BITWISE_CTRL; + assign _zz_4_ = _zz_45_; + assign _zz_40_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_3_ = decode_ENV_CTRL; + assign _zz_1_ = _zz_50_; + assign _zz_24_ = decode_to_execute_ENV_CTRL; + assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00)); + assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_260_,_zz_166_}; + assign iBusWishbone_CTI = ((_zz_166_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + iBusWishbone_STB = 1'b0; + if(_zz_199_)begin + iBusWishbone_CYC = 1'b1; + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_167_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_168_ = (4'b0001); + end + 2'b01 : begin + _zz_168_ = (4'b0011); + end + default : begin + _zz_168_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_261_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + CsrPlugin_privilege <= (2'b11); + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_93_ <= 1'b0; + _zz_99_ <= 1'b0; + _zz_101_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + execute_DBusSimplePlugin_cmdSent <= 1'b0; + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mip_MEIP <= 1'b0; + CsrPlugin_mip_MTIP <= 1'b0; + CsrPlugin_mip_MSIP <= 1'b0; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_161_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + _zz_164_ <= (3'b000); + _zz_166_ <= (3'b000); + _zz_167_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_197_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_93_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + _zz_99_ <= 1'b0; + end + if(_zz_97_)begin + _zz_99_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_101_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + _zz_101_ <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_68_))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if((dBus_cmd_valid && dBus_cmd_ready))begin + execute_DBusSimplePlugin_cmdSent <= 1'b1; + end + if((! execute_arbitration_isStuck))begin + execute_DBusSimplePlugin_cmdSent <= 1'b0; + end + if(_zz_190_)begin + if(_zz_191_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_192_)begin + CsrPlugin_privilege <= CsrPlugin_targetPrivilege; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_193_)begin + case(_zz_202_) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPIE <= 1'b1; + CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; + end + default : begin + end + endcase + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + case(_zz_164_) + 3'b000 : begin + if(_zz_85_)begin + _zz_164_ <= (3'b001); + end + end + 3'b001 : begin + _zz_164_ <= (3'b010); + end + 3'b010 : begin + _zz_164_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_164_ <= (3'b100); + end + end + 3'b100 : begin + _zz_164_ <= (3'b000); + end + default : begin + end + endcase + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_254_[0]; + CsrPlugin_mstatus_MIE <= _zz_255_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_256_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_257_[0]; + CsrPlugin_mie_MTIE <= _zz_258_[0]; + CsrPlugin_mie_MSIE <= _zz_259_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_199_)begin + if(iBusWishbone_ACK)begin + _zz_166_ <= (_zz_166_ + (3'b001)); + end + end + _zz_167_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_200_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_102_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_LightShifterPlugin_shiftReg <= _zz_58_; + end + if(_zz_190_)begin + if(_zz_191_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(execute_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(execute_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= execute_exception_agregat_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= execute_exception_agregat_payload_badAddr; + end + if((CsrPlugin_exception || CsrPlugin_interruptJump))begin + case(CsrPlugin_privilege) + 2'b11 : begin + CsrPlugin_mepc <= execute_PC; + end + default : begin + end + endcase + end + if(_zz_192_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_16_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_13_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_11_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FLUSH_ALL <= decode_FLUSH_ALL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_2_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_63_; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_200_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipActive <= ({execute_arbitration_isValid,decode_arbitration_isValid} != (2'b00)); + DebugPlugin_isPipActive_regNext <= DebugPlugin_isPipActive; + if(execute_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_58_; + end + _zz_163_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_198_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_194_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; + end else begin + if(debug_bus_cmd_valid)begin + case(_zz_198_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_246_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_247_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_248_[0]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_valid <= _zz_249_[0]; + end + end + default : begin + end + endcase + end + if(_zz_194_)begin + if(_zz_195_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_196_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + if((DebugPlugin_stepIt && ({execute_arbitration_redoIt,decode_arbitration_redoIt} != (2'b00))))begin + DebugPlugin_haltIt <= 1'b0; + end + end + end + + always @ (posedge clk) begin + _zz_165_ <= debug_bus_cmd_payload_data; + end + +endmodule + diff --git a/hw/2-stage-no-cache-debug.yaml b/hw/2-stage-no-cache-debug.yaml new file mode 100644 index 0000000..156f2e4 --- /dev/null +++ b/hw/2-stage-no-cache-debug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} +iBus: !!vexriscv.BusReport + flushInstructions: [16399, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} + kind: cached diff --git a/hw/4-stage-1024-cache-debug.v b/hw/4-stage-1024-cache-debug.v new file mode 100644 index 0000000..a25f10d --- /dev/null +++ b/hw/4-stage-1024-cache-debug.v @@ -0,0 +1,4099 @@ +// Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26 +// Date : 26/03/2019, 08:02:39 +// Component : VexRiscv + + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +module InstructionCache ( + input io_flush_cmd_valid, + output io_flush_cmd_ready, + output io_flush_rsp, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_allowUser, + input io_cpu_fetch_mmuBus_rsp_miss, + input io_cpu_fetch_mmuBus_rsp_hit, + output io_cpu_fetch_mmuBus_end, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuMiss, + output io_cpu_decode_illegalAccess, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [23:0] _zz_12_; + reg [31:0] _zz_13_; + wire _zz_14_; + wire [0:0] _zz_15_; + wire [0:0] _zz_16_; + wire [23:0] _zz_17_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg [5:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_flushFromInterface; + wire _zz_4_; + reg _zz_4__regNext; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [4:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [7:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_5_; + wire [4:0] _zz_6_; + wire _zz_7_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_8_; + wire [7:0] _zz_9_; + wire _zz_10_; + wire [31:0] fetchStage_read_waysValues_0_data; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_allowUser; + reg decodeStage_mmuRsp_miss; + reg decodeStage_mmuRsp_hit; + reg decodeStage_hit_tags_0_valid; + reg decodeStage_hit_tags_0_error; + reg [21:0] decodeStage_hit_tags_0_address; + wire decodeStage_hit_hits_0; + wire decodeStage_hit_valid; + wire decodeStage_hit_error; + reg [31:0] _zz_11_; + wire [31:0] decodeStage_hit_data; + reg [31:0] decodeStage_hit_word; + reg io_cpu_fetch_dataBypassValid_regNextWhen; + reg [31:0] io_cpu_fetch_dataBypass_regNextWhen; + reg [23:0] ways_0_tags [0:31]; + reg [31:0] ways_0_datas [0:255]; + assign _zz_14_ = (! lineLoader_flushCounter[5]); + assign _zz_15_ = _zz_8_[0 : 0]; + assign _zz_16_ = _zz_8_[1 : 1]; + assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_; + end + end + + always @ (posedge clk) begin + if(_zz_7_) begin + _zz_12_ <= ways_0_tags[_zz_6_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_10_) begin + _zz_13_ <= ways_0_datas[_zz_9_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = 1'b0; + if(lineLoader_valid)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(_zz_14_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush_cmd_valid)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid)); + assign _zz_4_ = lineLoader_flushCounter[5]; + assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_5_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_6_ = io_cpu_prefetch_pc[9 : 5]; + assign _zz_7_ = (! io_cpu_fetch_isStuck); + assign _zz_8_ = _zz_12_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2]; + assign _zz_9_ = io_cpu_prefetch_pc[9 : 2]; + assign _zz_10_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_13_; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]); + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10])); + assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); + assign decodeStage_hit_error = decodeStage_hit_tags_0_error; + assign decodeStage_hit_data = _zz_11_; + always @ (*) begin + decodeStage_hit_word = decodeStage_hit_data[31 : 0]; + if(io_cpu_fetch_dataBypassValid_regNextWhen)begin + decodeStage_hit_word = io_cpu_fetch_dataBypass_regNextWhen; + end + end + + assign io_cpu_decode_data = decodeStage_hit_word; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuMiss = decodeStage_mmuRsp_miss; + assign io_cpu_decode_illegalAccess = ((! decodeStage_mmuRsp_allowExecute) || (io_cpu_decode_isUser && (! decodeStage_mmuRsp_allowUser))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushCounter <= (6'b000000); + lineLoader_flushFromInterface <= 1'b0; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(_zz_14_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); + end + if(io_flush_cmd_valid)begin + if(io_flush_cmd_ready)begin + lineLoader_flushCounter <= (6'b000000); + lineLoader_flushFromInterface <= 1'b1; + end + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + _zz_3_ <= lineLoader_flushCounter[5]; + _zz_4__regNext <= _zz_4_; + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_allowUser <= io_cpu_fetch_mmuBus_rsp_allowUser; + decodeStage_mmuRsp_miss <= io_cpu_fetch_mmuBus_rsp_miss; + decodeStage_mmuRsp_hit <= io_cpu_fetch_mmuBus_rsp_hit; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; + decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; + decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; + end + if((! io_cpu_decode_isStuck))begin + _zz_11_ <= fetchStage_read_waysValues_0_data; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_dataBypassValid_regNextWhen <= io_cpu_fetch_dataBypassValid; + end + end + + always @ (posedge clk) begin + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_dataBypass_regNextWhen <= io_cpu_fetch_dataBypass; + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset, + input debugReset); + reg _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire [31:0] _zz_180_; + wire _zz_181_; + wire _zz_182_; + wire _zz_183_; + wire _zz_184_; + wire _zz_185_; + wire _zz_186_; + wire _zz_187_; + wire _zz_188_; + wire _zz_189_; + wire _zz_190_; + reg [31:0] _zz_191_; + reg [31:0] _zz_192_; + reg [31:0] _zz_193_; + wire IBusCachedPlugin_cache_io_flush_cmd_ready; + wire IBusCachedPlugin_cache_io_flush_rsp; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuMiss; + wire IBusCachedPlugin_cache_io_cpu_decode_illegalAccess; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_194_; + wire _zz_195_; + wire _zz_196_; + wire _zz_197_; + wire _zz_198_; + wire _zz_199_; + wire _zz_200_; + wire _zz_201_; + wire [5:0] _zz_202_; + wire _zz_203_; + wire _zz_204_; + wire [1:0] _zz_205_; + wire [1:0] _zz_206_; + wire _zz_207_; + wire [3:0] _zz_208_; + wire [2:0] _zz_209_; + wire [31:0] _zz_210_; + wire [11:0] _zz_211_; + wire [31:0] _zz_212_; + wire [19:0] _zz_213_; + wire [11:0] _zz_214_; + wire [2:0] _zz_215_; + wire [0:0] _zz_216_; + wire [0:0] _zz_217_; + wire [0:0] _zz_218_; + wire [0:0] _zz_219_; + wire [0:0] _zz_220_; + wire [0:0] _zz_221_; + wire [0:0] _zz_222_; + wire [0:0] _zz_223_; + wire [2:0] _zz_224_; + wire [4:0] _zz_225_; + wire [11:0] _zz_226_; + wire [11:0] _zz_227_; + wire [31:0] _zz_228_; + wire [31:0] _zz_229_; + wire [31:0] _zz_230_; + wire [31:0] _zz_231_; + wire [1:0] _zz_232_; + wire [31:0] _zz_233_; + wire [1:0] _zz_234_; + wire [1:0] _zz_235_; + wire [31:0] _zz_236_; + wire [32:0] _zz_237_; + wire [11:0] _zz_238_; + wire [19:0] _zz_239_; + wire [11:0] _zz_240_; + wire [31:0] _zz_241_; + wire [31:0] _zz_242_; + wire [31:0] _zz_243_; + wire [11:0] _zz_244_; + wire [19:0] _zz_245_; + wire [11:0] _zz_246_; + wire [2:0] _zz_247_; + wire [1:0] _zz_248_; + wire [1:0] _zz_249_; + wire [0:0] _zz_250_; + wire [0:0] _zz_251_; + wire [0:0] _zz_252_; + wire [0:0] _zz_253_; + wire [30:0] _zz_254_; + wire [30:0] _zz_255_; + wire [30:0] _zz_256_; + wire [30:0] _zz_257_; + wire [0:0] _zz_258_; + wire [0:0] _zz_259_; + wire [0:0] _zz_260_; + wire [0:0] _zz_261_; + wire [0:0] _zz_262_; + wire [0:0] _zz_263_; + wire [26:0] _zz_264_; + wire [6:0] _zz_265_; + wire [1:0] _zz_266_; + wire [0:0] _zz_267_; + wire [7:0] _zz_268_; + wire _zz_269_; + wire [0:0] _zz_270_; + wire [0:0] _zz_271_; + wire [31:0] _zz_272_; + wire _zz_273_; + wire _zz_274_; + wire [1:0] _zz_275_; + wire [1:0] _zz_276_; + wire _zz_277_; + wire [0:0] _zz_278_; + wire [19:0] _zz_279_; + wire [31:0] _zz_280_; + wire [31:0] _zz_281_; + wire [0:0] _zz_282_; + wire [0:0] _zz_283_; + wire [0:0] _zz_284_; + wire [2:0] _zz_285_; + wire [0:0] _zz_286_; + wire [0:0] _zz_287_; + wire _zz_288_; + wire [0:0] _zz_289_; + wire [16:0] _zz_290_; + wire [31:0] _zz_291_; + wire [31:0] _zz_292_; + wire [31:0] _zz_293_; + wire [31:0] _zz_294_; + wire [31:0] _zz_295_; + wire _zz_296_; + wire _zz_297_; + wire [31:0] _zz_298_; + wire [0:0] _zz_299_; + wire [3:0] _zz_300_; + wire [0:0] _zz_301_; + wire [0:0] _zz_302_; + wire [0:0] _zz_303_; + wire [0:0] _zz_304_; + wire _zz_305_; + wire [0:0] _zz_306_; + wire [13:0] _zz_307_; + wire [31:0] _zz_308_; + wire [31:0] _zz_309_; + wire [31:0] _zz_310_; + wire [31:0] _zz_311_; + wire _zz_312_; + wire [0:0] _zz_313_; + wire [1:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire [31:0] _zz_317_; + wire [31:0] _zz_318_; + wire [0:0] _zz_319_; + wire [0:0] _zz_320_; + wire [1:0] _zz_321_; + wire [1:0] _zz_322_; + wire _zz_323_; + wire [0:0] _zz_324_; + wire [11:0] _zz_325_; + wire [31:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [31:0] _zz_329_; + wire [31:0] _zz_330_; + wire [31:0] _zz_331_; + wire [31:0] _zz_332_; + wire _zz_333_; + wire [1:0] _zz_334_; + wire [1:0] _zz_335_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [8:0] _zz_338_; + wire [31:0] _zz_339_; + wire [31:0] _zz_340_; + wire [31:0] _zz_341_; + wire [31:0] _zz_342_; + wire _zz_343_; + wire [0:0] _zz_344_; + wire [0:0] _zz_345_; + wire [2:0] _zz_346_; + wire [2:0] _zz_347_; + wire _zz_348_; + wire [0:0] _zz_349_; + wire [5:0] _zz_350_; + wire [31:0] _zz_351_; + wire [31:0] _zz_352_; + wire [31:0] _zz_353_; + wire _zz_354_; + wire _zz_355_; + wire [31:0] _zz_356_; + wire [31:0] _zz_357_; + wire _zz_358_; + wire [0:0] _zz_359_; + wire [0:0] _zz_360_; + wire _zz_361_; + wire [0:0] _zz_362_; + wire [2:0] _zz_363_; + wire [31:0] _zz_364_; + wire _zz_365_; + wire [0:0] _zz_366_; + wire [1:0] _zz_367_; + wire [0:0] _zz_368_; + wire [0:0] _zz_369_; + wire _zz_370_; + wire _zz_371_; + wire [31:0] _zz_372_; + wire [31:0] _zz_373_; + wire [31:0] _zz_374_; + wire [31:0] _zz_375_; + wire [31:0] _zz_376_; + wire [31:0] _zz_377_; + wire [31:0] _zz_378_; + wire [31:0] _zz_379_; + wire [31:0] _zz_380_; + wire [31:0] _zz_381_; + wire _zz_382_; + wire _zz_383_; + wire _zz_384_; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire decode_PREDICTION_HAD_BRANCHED2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_9_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_10_; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13_; + wire decode_DO_EBREAK; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_14_; + wire `AluCtrlEnum_defaultEncoding_type _zz_15_; + wire `AluCtrlEnum_defaultEncoding_type _zz_16_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_17_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_18_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_19_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_20_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_21_; + wire decode_CSR_READ_OPCODE; + wire decode_SRC_USE_SUB_LESS; + wire decode_CSR_WRITE_OPCODE; + wire execute_FLUSH_ALL; + wire decode_FLUSH_ALL; + wire decode_SRC_LESS_UNSIGNED; + wire writeBack_REGFILE_WRITE_VALID; + wire memory_REGFILE_WRITE_VALID; + wire execute_REGFILE_WRITE_VALID; + wire [31:0] memory_MEMORY_READ_DATA; + wire decode_IS_CSR; + wire decode_MEMORY_ENABLE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_24_; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire _zz_25_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; + wire _zz_28_; + wire _zz_29_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_31_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_32_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_33_; + wire _zz_34_; + wire _zz_35_; + reg [31:0] _zz_36_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_37_; + wire _zz_38_; + wire [31:0] _zz_39_; + wire [31:0] _zz_40_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42_; + wire [31:0] _zz_43_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_44_; + wire [31:0] _zz_45_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_46_; + wire [31:0] _zz_47_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_48_; + reg _zz_49_; + wire [31:0] _zz_50_; + wire [31:0] _zz_51_; + reg decode_REGFILE_WRITE_VALID; + wire `BranchCtrlEnum_defaultEncoding_type _zz_52_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53_; + wire _zz_54_; + wire _zz_55_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56_; + wire _zz_57_; + wire _zz_58_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_59_; + wire `AluCtrlEnum_defaultEncoding_type _zz_60_; + wire _zz_61_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_62_; + wire _zz_63_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_64_; + wire _zz_65_; + reg [31:0] _zz_66_; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_INSTRUCTION; + wire memory_MEMORY_ENABLE; + wire [31:0] _zz_67_; + wire [1:0] _zz_68_; + wire [31:0] execute_RS2; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_INSTRUCTION; + wire execute_ALIGNEMENT_FAULT; + wire execute_MEMORY_ENABLE; + wire _zz_69_; + wire memory_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_70_; + reg [31:0] _zz_71_; + reg [31:0] _zz_72_; + wire [31:0] _zz_73_; + wire [31:0] _zz_74_; + wire [31:0] _zz_75_; + wire [31:0] writeBack_PC /* verilator public */ ; + wire [31:0] writeBack_INSTRUCTION /* verilator public */ ; + wire [31:0] decode_PC /* verilator public */ ; + reg [31:0] decode_INSTRUCTION /* verilator public */ ; + reg decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + wire decode_arbitration_redoIt; + reg decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + wire execute_arbitration_redoIt; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushAll; + wire memory_arbitration_redoIt; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushAll; + wire writeBack_arbitration_redoIt; + reg writeBack_arbitration_isValid /* verilator public */ ; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring /* verilator public */ ; + reg _zz_76_; + reg _zz_77_; + reg _zz_78_; + wire _zz_79_; + wire [31:0] _zz_80_; + wire _zz_81_; + wire _zz_82_; + wire [31:0] _zz_83_; + wire [31:0] _zz_84_; + reg memory_exception_agregat_valid; + wire [3:0] memory_exception_agregat_payload_code; + wire [31:0] memory_exception_agregat_payload_badAddr; + wire _zz_85_; + wire [31:0] _zz_86_; + reg _zz_87_; + reg _zz_88_; + reg [31:0] _zz_89_; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg _zz_90_; + reg [3:0] _zz_91_; + reg _zz_92_; + reg _zz_93_; + reg _zz_94_; + reg _zz_95_; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_96_; + wire [3:0] _zz_97_; + wire _zz_98_; + wire _zz_99_; + wire _zz_100_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_101_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_102_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_103_; + wire _zz_104_; + wire _zz_105_; + wire _zz_106_; + wire _zz_107_; + reg _zz_108_; + wire _zz_109_; + reg _zz_110_; + reg [31:0] _zz_111_; + wire IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + reg IBusCachedPlugin_injector_decodeRemoved; + wire _zz_112_; + reg [18:0] _zz_113_; + wire _zz_114_; + reg [10:0] _zz_115_; + wire _zz_116_; + reg [18:0] _zz_117_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire execute_DBusSimplePlugin_cmdSent; + reg [31:0] _zz_118_; + reg [3:0] _zz_119_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_120_; + reg [31:0] _zz_121_; + wire _zz_122_; + reg [31:0] _zz_123_; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [25:0] _zz_124_; + wire _zz_125_; + wire _zz_126_; + wire _zz_127_; + wire _zz_128_; + wire _zz_129_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_130_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_131_; + wire `AluCtrlEnum_defaultEncoding_type _zz_132_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_133_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_134_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_135_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_136_; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire _zz_137_; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire writeBack_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_138_; + reg [31:0] _zz_139_; + wire _zz_140_; + reg [19:0] _zz_141_; + wire _zz_142_; + reg [19:0] _zz_143_; + reg [31:0] _zz_144_; + wire [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_145_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_146_; + reg _zz_147_; + reg _zz_148_; + wire _zz_149_; + reg [19:0] _zz_150_; + wire _zz_151_; + reg [10:0] _zz_152_; + wire _zz_153_; + reg [18:0] _zz_154_; + reg _zz_155_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_156_; + reg [19:0] _zz_157_; + wire _zz_158_; + reg [10:0] _zz_159_; + wire _zz_160_; + reg [18:0] _zz_161_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire [31:0] CsrPlugin_medeleg; + wire [31:0] CsrPlugin_mideleg; + wire _zz_162_; + wire _zz_163_; + wire _zz_164_; + wire CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + wire CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + wire CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire execute_exception_agregat_valid; + wire [3:0] execute_exception_agregat_payload_code; + wire [31:0] execute_exception_agregat_payload_badAddr; + wire [1:0] _zz_165_; + wire _zz_166_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + wire [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_167_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_168_; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipActive; + reg DebugPlugin_isPipActive_regNext; + wire DebugPlugin_isPipBusy; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_169_; + reg DebugPlugin_resetIt_regNext; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg decode_to_execute_IS_CSR; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg decode_to_execute_FLUSH_ALL; + reg execute_to_memory_FLUSH_ALL; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg decode_to_execute_CSR_READ_OPCODE; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_DO_EBREAK; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [2:0] _zz_170_; + reg [31:0] _zz_171_; + reg [2:0] _zz_172_; + reg _zz_173_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_174_; + `ifndef SYNTHESIS + reg [47:0] _zz_1__string; + reg [47:0] _zz_2__string; + reg [47:0] _zz_3__string; + reg [47:0] _zz_4__string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_5__string; + reg [47:0] _zz_6__string; + reg [47:0] _zz_7__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_8__string; + reg [39:0] _zz_9__string; + reg [39:0] _zz_10__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_11__string; + reg [71:0] _zz_12__string; + reg [71:0] _zz_13__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_14__string; + reg [63:0] _zz_15__string; + reg [63:0] _zz_16__string; + reg [31:0] _zz_17__string; + reg [31:0] _zz_18__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_19__string; + reg [95:0] _zz_20__string; + reg [95:0] _zz_21__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_22__string; + reg [23:0] _zz_23__string; + reg [23:0] _zz_24__string; + reg [47:0] memory_ENV_CTRL_string; + reg [47:0] _zz_26__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_27__string; + reg [47:0] writeBack_ENV_CTRL_string; + reg [47:0] _zz_30__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_33__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_37__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_44__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_46__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_48__string; + reg [31:0] _zz_52__string; + reg [39:0] _zz_53__string; + reg [95:0] _zz_56__string; + reg [23:0] _zz_59__string; + reg [63:0] _zz_60__string; + reg [47:0] _zz_62__string; + reg [71:0] _zz_64__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_70__string; + reg [71:0] _zz_130__string; + reg [47:0] _zz_131__string; + reg [63:0] _zz_132__string; + reg [23:0] _zz_133__string; + reg [95:0] _zz_134__string; + reg [39:0] _zz_135__string; + reg [31:0] _zz_136__string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [47:0] execute_to_memory_ENV_CTRL_string; + reg [47:0] memory_to_writeBack_ENV_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_194_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_195_ = (! execute_arbitration_isStuckByOthers); + assign _zz_196_ = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_197_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); + assign _zz_198_ = (DebugPlugin_stepIt && _zz_78_); + assign _zz_199_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_200_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_201_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_202_ = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_203_ = (iBus_cmd_valid || (_zz_172_ != (3'b000))); + assign _zz_204_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_205_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_206_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_207_ = execute_INSTRUCTION[13]; + assign _zz_208_ = (_zz_96_ - (4'b0001)); + assign _zz_209_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_210_ = {29'd0, _zz_209_}; + assign _zz_211_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_212_ = {{_zz_113_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_213_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_214_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_215_ = (memory_INSTRUCTION[5] ? (3'b110) : (3'b100)); + assign _zz_216_ = _zz_124_[0 : 0]; + assign _zz_217_ = _zz_124_[3 : 3]; + assign _zz_218_ = _zz_124_[6 : 6]; + assign _zz_219_ = _zz_124_[12 : 12]; + assign _zz_220_ = _zz_124_[13 : 13]; + assign _zz_221_ = _zz_124_[17 : 17]; + assign _zz_222_ = _zz_124_[18 : 18]; + assign _zz_223_ = execute_SRC_LESS; + assign _zz_224_ = (3'b100); + assign _zz_225_ = execute_INSTRUCTION[19 : 15]; + assign _zz_226_ = execute_INSTRUCTION[31 : 20]; + assign _zz_227_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_228_ = ($signed(_zz_229_) + $signed(_zz_233_)); + assign _zz_229_ = ($signed(_zz_230_) + $signed(_zz_231_)); + assign _zz_230_ = execute_SRC1; + assign _zz_231_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_232_ = (execute_SRC_USE_SUB_LESS ? _zz_234_ : _zz_235_); + assign _zz_233_ = {{30{_zz_232_[1]}}, _zz_232_}; + assign _zz_234_ = (2'b01); + assign _zz_235_ = (2'b00); + assign _zz_236_ = (_zz_237_ >>> 1); + assign _zz_237_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_238_ = execute_INSTRUCTION[31 : 20]; + assign _zz_239_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_240_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_241_ = {_zz_150_,execute_INSTRUCTION[31 : 20]}; + assign _zz_242_ = {{_zz_152_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_243_ = {{_zz_154_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_244_ = execute_INSTRUCTION[31 : 20]; + assign _zz_245_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_246_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_247_ = (3'b100); + assign _zz_248_ = (_zz_165_ & (~ _zz_249_)); + assign _zz_249_ = (_zz_165_ - (2'b01)); + assign _zz_250_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_251_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_252_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_253_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_254_ = (decode_PC >>> 1); + assign _zz_255_ = (decode_PC >>> 1); + assign _zz_256_ = (decode_PC >>> 1); + assign _zz_257_ = (decode_PC >>> 1); + assign _zz_258_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_259_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_260_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_261_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_262_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_263_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_264_ = (iBus_cmd_payload_address >>> 5); + assign _zz_265_ = ({3'd0,_zz_174_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_266_ = {_zz_100_,_zz_99_}; + assign _zz_267_ = decode_INSTRUCTION[31]; + assign _zz_268_ = decode_INSTRUCTION[19 : 12]; + assign _zz_269_ = decode_INSTRUCTION[20]; + assign _zz_270_ = decode_INSTRUCTION[31]; + assign _zz_271_ = decode_INSTRUCTION[7]; + assign _zz_272_ = (32'b00000000000000000000000000010000); + assign _zz_273_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000000000000000100)); + assign _zz_274_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); + assign _zz_275_ = {(_zz_280_ == _zz_281_),_zz_126_}; + assign _zz_276_ = (2'b00); + assign _zz_277_ = ({_zz_126_,{_zz_282_,_zz_283_}} != (3'b000)); + assign _zz_278_ = ({_zz_284_,_zz_285_} != (4'b0000)); + assign _zz_279_ = {(_zz_286_ != _zz_287_),{_zz_288_,{_zz_289_,_zz_290_}}}; + assign _zz_280_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); + assign _zz_281_ = (32'b00000000000000000001000000000000); + assign _zz_282_ = ((decode_INSTRUCTION & _zz_291_) == (32'b00000000000000000001000000000000)); + assign _zz_283_ = ((decode_INSTRUCTION & _zz_292_) == (32'b00000000000000000010000000000000)); + assign _zz_284_ = ((decode_INSTRUCTION & _zz_293_) == (32'b00000000000000000000000000000000)); + assign _zz_285_ = {(_zz_294_ == _zz_295_),{_zz_296_,_zz_297_}}; + assign _zz_286_ = ((decode_INSTRUCTION & _zz_298_) == (32'b00000000000000000000000000000000)); + assign _zz_287_ = (1'b0); + assign _zz_288_ = ({_zz_129_,{_zz_299_,_zz_300_}} != (6'b000000)); + assign _zz_289_ = ({_zz_301_,_zz_302_} != (2'b00)); + assign _zz_290_ = {(_zz_303_ != _zz_304_),{_zz_305_,{_zz_306_,_zz_307_}}}; + assign _zz_291_ = (32'b00000000000000000011000000000000); + assign _zz_292_ = (32'b00000000000000000011000000000000); + assign _zz_293_ = (32'b00000000000000000000000001000100); + assign _zz_294_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); + assign _zz_295_ = (32'b00000000000000000000000000000000); + assign _zz_296_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000000000000)); + assign _zz_297_ = ((decode_INSTRUCTION & _zz_309_) == (32'b00000000000000000001000000000000)); + assign _zz_298_ = (32'b00000000000000000000000000000000); + assign _zz_299_ = (_zz_310_ == _zz_311_); + assign _zz_300_ = {_zz_312_,{_zz_313_,_zz_314_}}; + assign _zz_301_ = (_zz_315_ == _zz_316_); + assign _zz_302_ = (_zz_317_ == _zz_318_); + assign _zz_303_ = _zz_128_; + assign _zz_304_ = (1'b0); + assign _zz_305_ = ({_zz_319_,_zz_320_} != (2'b00)); + assign _zz_306_ = (_zz_321_ != _zz_322_); + assign _zz_307_ = {_zz_323_,{_zz_324_,_zz_325_}}; + assign _zz_308_ = (32'b00000000000000000110000000000100); + assign _zz_309_ = (32'b00000000000000000101000000000100); + assign _zz_310_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_311_ = (32'b00000000000000000001000000010000); + assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); + assign _zz_313_ = _zz_128_; + assign _zz_314_ = {(_zz_326_ == _zz_327_),(_zz_328_ == _zz_329_)}; + assign _zz_315_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_316_ = (32'b00000000000000000001000001010000); + assign _zz_317_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_318_ = (32'b00000000000000000010000001010000); + assign _zz_319_ = ((decode_INSTRUCTION & _zz_330_) == (32'b00000000000000000000000000000100)); + assign _zz_320_ = _zz_127_; + assign _zz_321_ = {(_zz_331_ == _zz_332_),_zz_127_}; + assign _zz_322_ = (2'b00); + assign _zz_323_ = (_zz_125_ != (1'b0)); + assign _zz_324_ = (_zz_333_ != (1'b0)); + assign _zz_325_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}; + assign _zz_326_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_327_ = (32'b00000000000000000000000000000000); + assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_329_ = (32'b00000000000000000000000000000100); + assign _zz_330_ = (32'b00000000000000000000000000010100); + assign _zz_331_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_332_ = (32'b00000000000000000000000000000100); + assign _zz_333_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); + assign _zz_334_ = {(_zz_339_ == _zz_340_),(_zz_341_ == _zz_342_)}; + assign _zz_335_ = (2'b00); + assign _zz_336_ = ({_zz_126_,_zz_343_} != (2'b00)); + assign _zz_337_ = ({_zz_344_,_zz_345_} != (2'b00)); + assign _zz_338_ = {(_zz_346_ != _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}; + assign _zz_339_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_340_ = (32'b00000000000000000000000000100000); + assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_342_ = (32'b00000000000000000000000000100000); + assign _zz_343_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); + assign _zz_344_ = _zz_126_; + assign _zz_345_ = ((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000000)); + assign _zz_346_ = {(_zz_352_ == _zz_353_),{_zz_354_,_zz_355_}}; + assign _zz_347_ = (3'b000); + assign _zz_348_ = ((_zz_356_ == _zz_357_) != (1'b0)); + assign _zz_349_ = (_zz_358_ != (1'b0)); + assign _zz_350_ = {(_zz_359_ != _zz_360_),{_zz_361_,{_zz_362_,_zz_363_}}}; + assign _zz_351_ = (32'b00000000000000000000000000100000); + assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_353_ = (32'b00000000000000000000000000100100); + assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000)); + assign _zz_355_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000010100)) == (32'b00000000000000000001000000010000)); + assign _zz_356_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); + assign _zz_357_ = (32'b00000000000000000010000000010000); + assign _zz_358_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000000000000001000)); + assign _zz_359_ = ((decode_INSTRUCTION & _zz_364_) == (32'b00000000000000000000000001010000)); + assign _zz_360_ = (1'b0); + assign _zz_361_ = ({_zz_125_,_zz_365_} != (2'b00)); + assign _zz_362_ = ({_zz_366_,_zz_367_} != (3'b000)); + assign _zz_363_ = {(_zz_368_ != _zz_369_),{_zz_370_,_zz_371_}}; + assign _zz_364_ = (32'b00010000000000000011000001010000); + assign _zz_365_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_366_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); + assign _zz_367_ = {((decode_INSTRUCTION & _zz_372_) == (32'b01000000000000000000000000110000)),((decode_INSTRUCTION & _zz_373_) == (32'b00000000000000000010000000010000))}; + assign _zz_368_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000101000000010000)); + assign _zz_369_ = (1'b0); + assign _zz_370_ = ({(_zz_374_ == _zz_375_),(_zz_376_ == _zz_377_)} != (2'b00)); + assign _zz_371_ = ({(_zz_378_ == _zz_379_),(_zz_380_ == _zz_381_)} != (2'b00)); + assign _zz_372_ = (32'b01000000000000000000000000110000); + assign _zz_373_ = (32'b00000000000000000010000000010100); + assign _zz_374_ = (decode_INSTRUCTION & (32'b01000000000000000011000001010100)); + assign _zz_375_ = (32'b01000000000000000001000000010000); + assign _zz_376_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); + assign _zz_377_ = (32'b00000000000000000001000000010000); + assign _zz_378_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_379_ = (32'b00000000000000000010000000000000); + assign _zz_380_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); + assign _zz_381_ = (32'b00000000000000000001000000000000); + assign _zz_382_ = execute_INSTRUCTION[31]; + assign _zz_383_ = execute_INSTRUCTION[31]; + assign _zz_384_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_49_) begin + RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_137_) begin + _zz_191_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_137_) begin + _zz_192_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush_cmd_valid(_zz_175_), + .io_flush_cmd_ready(IBusCachedPlugin_cache_io_flush_cmd_ready), + .io_flush_rsp(IBusCachedPlugin_cache_io_flush_rsp), + .io_cpu_prefetch_isValid(_zz_176_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_177_), + .io_cpu_fetch_isStuck(_zz_178_), + .io_cpu_fetch_isRemoved(_zz_179_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_180_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(_zz_84_), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_181_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_182_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_183_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_184_), + .io_cpu_fetch_mmuBus_rsp_allowUser(_zz_185_), + .io_cpu_fetch_mmuBus_rsp_miss(_zz_186_), + .io_cpu_fetch_mmuBus_rsp_hit(_zz_187_), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_decode_isValid(_zz_188_), + .io_cpu_decode_isStuck(_zz_189_), + .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), + .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), + .io_cpu_decode_mmuMiss(IBusCachedPlugin_cache_io_cpu_decode_mmuMiss), + .io_cpu_decode_illegalAccess(IBusCachedPlugin_cache_io_cpu_decode_illegalAccess), + .io_cpu_decode_isUser(_zz_190_), + .io_cpu_fill_valid(IBusCachedPlugin_rsp_redoFetch), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_266_) + 2'b00 : begin + _zz_193_ = _zz_89_; + end + 2'b01 : begin + _zz_193_ = _zz_86_; + end + 2'b10 : begin + _zz_193_ = _zz_83_; + end + default : begin + _zz_193_ = _zz_80_; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_1__string = "EBREAK"; + default : _zz_1__string = "??????"; + endcase + end + always @(*) begin + case(_zz_2_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_2__string = "EBREAK"; + default : _zz_2__string = "??????"; + endcase + end + always @(*) begin + case(_zz_3_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_3__string = "EBREAK"; + default : _zz_3__string = "??????"; + endcase + end + always @(*) begin + case(_zz_4_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_4__string = "EBREAK"; + default : _zz_4__string = "??????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_5_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_5__string = "EBREAK"; + default : _zz_5__string = "??????"; + endcase + end + always @(*) begin + case(_zz_6_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_6__string = "EBREAK"; + default : _zz_6__string = "??????"; + endcase + end + always @(*) begin + case(_zz_7_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_7__string = "EBREAK"; + default : _zz_7__string = "??????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_8__string = "SRC1 "; + default : _zz_8__string = "?????"; + endcase + end + always @(*) begin + case(_zz_9_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_9__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_9__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_9__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_9__string = "SRC1 "; + default : _zz_9__string = "?????"; + endcase + end + always @(*) begin + case(_zz_10_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_10__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_10__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_10__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_10__string = "SRC1 "; + default : _zz_10__string = "?????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11__string = "SRA_1 "; + default : _zz_11__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12__string = "SRA_1 "; + default : _zz_12__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13__string = "SRA_1 "; + default : _zz_13__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_14_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_14__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_14__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_14__string = "BITWISE "; + default : _zz_14__string = "????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_15__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_15__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_15__string = "BITWISE "; + default : _zz_15__string = "????????"; + endcase + end + always @(*) begin + case(_zz_16_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_16__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_16__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_16__string = "BITWISE "; + default : _zz_16__string = "????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_17__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_17__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_17__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_17__string = "JALR"; + default : _zz_17__string = "????"; + endcase + end + always @(*) begin + case(_zz_18_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_18__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_18__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_18__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_18__string = "JALR"; + default : _zz_18__string = "????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_19_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_19__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_19__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_19__string = "URS1 "; + default : _zz_19__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_20_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_20__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_20__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_20__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_20__string = "URS1 "; + default : _zz_20__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_21_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_21__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_21__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_21__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_21__string = "URS1 "; + default : _zz_21__string = "????????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_22_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22__string = "PC "; + default : _zz_22__string = "???"; + endcase + end + always @(*) begin + case(_zz_23_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23__string = "PC "; + default : _zz_23__string = "???"; + endcase + end + always @(*) begin + case(_zz_24_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_24__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_24__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_24__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_24__string = "PC "; + default : _zz_24__string = "???"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : memory_ENV_CTRL_string = "EBREAK"; + default : memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_26_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_26__string = "EBREAK"; + default : _zz_26__string = "??????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_27_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_27__string = "EBREAK"; + default : _zz_27__string = "??????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; + default : writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_30_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_30__string = "EBREAK"; + default : _zz_30__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_33_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_33__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_33__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_33__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_33__string = "JALR"; + default : _zz_33__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_37_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37__string = "SRA_1 "; + default : _zz_37__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42__string = "PC "; + default : _zz_42__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_44_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_44__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_44__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_44__string = "URS1 "; + default : _zz_44__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_46_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_46__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_46__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_46__string = "BITWISE "; + default : _zz_46__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_48_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_48__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_48__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_48__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_48__string = "SRC1 "; + default : _zz_48__string = "?????"; + endcase + end + always @(*) begin + case(_zz_52_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_52__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_52__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_52__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_52__string = "JALR"; + default : _zz_52__string = "????"; + endcase + end + always @(*) begin + case(_zz_53_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_53__string = "SRC1 "; + default : _zz_53__string = "?????"; + endcase + end + always @(*) begin + case(_zz_56_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56__string = "URS1 "; + default : _zz_56__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_59_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_59__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_59__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_59__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_59__string = "PC "; + default : _zz_59__string = "???"; + endcase + end + always @(*) begin + case(_zz_60_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE "; + default : _zz_60__string = "????????"; + endcase + end + always @(*) begin + case(_zz_62_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_62__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_62__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_62__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_62__string = "EBREAK"; + default : _zz_62__string = "??????"; + endcase + end + always @(*) begin + case(_zz_64_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_64__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_64__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_64__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_64__string = "SRA_1 "; + default : _zz_64__string = "?????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_70_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_70__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_70__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_70__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_70__string = "JALR"; + default : _zz_70__string = "????"; + endcase + end + always @(*) begin + case(_zz_130_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_130__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_130__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_130__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_130__string = "SRA_1 "; + default : _zz_130__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_131_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_131__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_131__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_131__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_131__string = "EBREAK"; + default : _zz_131__string = "??????"; + endcase + end + always @(*) begin + case(_zz_132_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_132__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_132__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_132__string = "BITWISE "; + default : _zz_132__string = "????????"; + endcase + end + always @(*) begin + case(_zz_133_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_133__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_133__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_133__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_133__string = "PC "; + default : _zz_133__string = "???"; + endcase + end + always @(*) begin + case(_zz_134_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_134__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_134__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_134__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_134__string = "URS1 "; + default : _zz_134__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_135_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_135__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_135__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_135__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_135__string = "SRC1 "; + default : _zz_135__string = "?????"; + endcase + end + always @(*) begin + case(_zz_136_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_136__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_136__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_136__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_136__string = "JALR"; + default : _zz_136__string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_to_execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + `endif + + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_73_; + assign memory_PC = execute_to_memory_PC; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_35_; + assign _zz_1_ = _zz_2_; + assign _zz_3_ = _zz_4_; + assign decode_ENV_CTRL = _zz_5_; + assign _zz_6_ = _zz_7_; + assign decode_ALU_BITWISE_CTRL = _zz_8_; + assign _zz_9_ = _zz_10_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_68_; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_47_; + assign decode_SHIFT_CTRL = _zz_11_; + assign _zz_12_ = _zz_13_; + assign decode_DO_EBREAK = _zz_25_; + assign decode_ALU_CTRL = _zz_14_; + assign _zz_15_ = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_SRC1_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign decode_CSR_READ_OPCODE = _zz_28_; + assign decode_SRC_USE_SUB_LESS = _zz_63_; + assign decode_CSR_WRITE_OPCODE = _zz_29_; + assign execute_FLUSH_ALL = decode_to_execute_FLUSH_ALL; + assign decode_FLUSH_ALL = _zz_61_; + assign decode_SRC_LESS_UNSIGNED = _zz_65_; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign memory_MEMORY_READ_DATA = _zz_67_; + assign decode_IS_CSR = _zz_55_; + assign decode_MEMORY_ENABLE = _zz_58_; + assign decode_SRC2_CTRL = _zz_22_; + assign _zz_23_ = _zz_24_; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_57_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_26_; + assign execute_ENV_CTRL = _zz_27_; + assign writeBack_ENV_CTRL = _zz_30_; + assign execute_BRANCH_CALC = _zz_31_; + assign execute_BRANCH_DO = _zz_32_; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = _zz_51_; + assign execute_BRANCH_COND_RESULT = _zz_34_; + assign execute_BRANCH_CTRL = _zz_33_; + always @ (*) begin + _zz_36_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_194_)begin + _zz_36_ = _zz_145_; + if(_zz_195_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_36_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_SHIFT_CTRL = _zz_37_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41_ = execute_PC; + assign execute_SRC2_CTRL = _zz_42_; + assign execute_SRC1_CTRL = _zz_44_; + assign execute_SRC_ADD_SUB = _zz_40_; + assign execute_SRC_LESS = _zz_38_; + assign execute_ALU_CTRL = _zz_46_; + assign execute_SRC2 = _zz_43_; + assign execute_SRC1 = _zz_45_; + assign execute_ALU_BITWISE_CTRL = _zz_48_; + always @ (*) begin + _zz_49_ = 1'b0; + if(writeBack_RegFilePlugin_regFileWrite_valid)begin + _zz_49_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_54_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_66_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_66_ = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_RS2 = _zz_50_; + assign execute_SRC_ADD = _zz_39_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_ALIGNEMENT_FAULT = _zz_69_; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign memory_FLUSH_ALL = execute_to_memory_FLUSH_ALL; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(((_zz_188_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! 1'b0)))begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_redoFetch = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + assign decode_BRANCH_CTRL = _zz_70_; + always @ (*) begin + _zz_71_ = execute_FORMAL_PC_NEXT; + if(_zz_85_)begin + _zz_71_ = _zz_86_; + end + end + + always @ (*) begin + _zz_72_ = decode_FORMAL_PC_NEXT; + if(_zz_79_)begin + _zz_72_ = _zz_80_; + end + if(_zz_82_)begin + _zz_72_ = _zz_83_; + end + end + + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + assign decode_PC = _zz_75_; + always @ (*) begin + decode_INSTRUCTION = _zz_74_; + if((_zz_170_ != (3'b000)))begin + decode_INSTRUCTION = _zz_171_; + end + end + + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + _zz_95_ = 1'b0; + case(_zz_170_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + _zz_95_ = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((CsrPlugin_interrupt && decode_arbitration_isValid))begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))} != (2'b00)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_removeIt = 1'b0; + if(_zz_85_)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_exception_agregat_valid)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_redoIt = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + _zz_76_ = 1'b0; + _zz_77_ = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode}}} != (4'b0000)))begin + _zz_76_ = 1'b1; + end + if(_zz_196_)begin + execute_arbitration_haltByOther = 1'b1; + if(_zz_197_)begin + _zz_77_ = 1'b1; + _zz_76_ = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + _zz_76_ = 1'b1; + end + if(_zz_198_)begin + _zz_76_ = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(memory_exception_agregat_valid)begin + execute_arbitration_flushAll = 1'b1; + end + if(_zz_196_)begin + if(_zz_197_)begin + execute_arbitration_flushAll = 1'b1; + end + end + end + + assign execute_arbitration_redoIt = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + _zz_175_ = 1'b0; + if((memory_arbitration_isValid && memory_FLUSH_ALL))begin + _zz_175_ = 1'b1; + if((! IBusCachedPlugin_cache_io_flush_cmd_ready))begin + memory_arbitration_haltItself = 1'b1; + end + end + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin + memory_arbitration_haltItself = 1'b1; + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_exception_agregat_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushAll = 1'b0; + _zz_88_ = 1'b0; + _zz_89_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_199_)begin + _zz_88_ = 1'b1; + _zz_89_ = {CsrPlugin_mtvec_base,(2'b00)}; + memory_arbitration_flushAll = 1'b1; + end + if(_zz_200_)begin + _zz_89_ = CsrPlugin_mepc; + _zz_88_ = 1'b1; + memory_arbitration_flushAll = 1'b1; + end + end + + assign memory_arbitration_redoIt = 1'b0; + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushAll = 1'b0; + assign writeBack_arbitration_redoIt = 1'b0; + always @ (*) begin + _zz_78_ = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + _zz_78_ = 1'b1; + end + end + + always @ (*) begin + _zz_92_ = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + _zz_92_ = 1'b0; + end + end + + always @ (*) begin + _zz_93_ = 1'b1; + if(DebugPlugin_haltIt)begin + _zz_93_ = 1'b0; + end + end + + assign IBusCachedPlugin_jump_pcLoad_valid = ({_zz_88_,{_zz_85_,{_zz_82_,_zz_79_}}} != (4'b0000)); + assign _zz_96_ = {_zz_79_,{_zz_82_,{_zz_85_,_zz_88_}}}; + assign _zz_97_ = (_zz_96_ & (~ _zz_208_)); + assign _zz_98_ = _zz_97_[3]; + assign _zz_99_ = (_zz_97_[1] || _zz_98_); + assign _zz_100_ = (_zz_97_[2] || _zz_98_); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_193_; + assign _zz_101_ = (! _zz_76_); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_101_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_101_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid && IBusCachedPlugin_iBusRsp_stages_1_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_210_); + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + if(_zz_201_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_102_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_103_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_103_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_103_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(((IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid && (! 1'b1)) && (! 1'b0)))begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_104_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_104_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_104_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_105_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_105_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_105_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_106_; + assign _zz_106_ = ((1'b0 && (! _zz_107_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_107_ = _zz_108_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_107_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_109_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_109_ = _zz_110_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_109_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_111_; + assign IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign _zz_75_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_74_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_73_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_112_ = _zz_211_[11]; + always @ (*) begin + _zz_113_[18] = _zz_112_; + _zz_113_[17] = _zz_112_; + _zz_113_[16] = _zz_112_; + _zz_113_[15] = _zz_112_; + _zz_113_[14] = _zz_112_; + _zz_113_[13] = _zz_112_; + _zz_113_[12] = _zz_112_; + _zz_113_[11] = _zz_112_; + _zz_113_[10] = _zz_112_; + _zz_113_[9] = _zz_112_; + _zz_113_[8] = _zz_112_; + _zz_113_[7] = _zz_112_; + _zz_113_[6] = _zz_112_; + _zz_113_[5] = _zz_112_; + _zz_113_[4] = _zz_112_; + _zz_113_[3] = _zz_112_; + _zz_113_[2] = _zz_112_; + _zz_113_[1] = _zz_112_; + _zz_113_[0] = _zz_112_; + end + + assign _zz_81_ = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_212_[31])); + assign _zz_79_ = (_zz_81_ && decode_arbitration_isFiring); + assign _zz_114_ = _zz_213_[19]; + always @ (*) begin + _zz_115_[10] = _zz_114_; + _zz_115_[9] = _zz_114_; + _zz_115_[8] = _zz_114_; + _zz_115_[7] = _zz_114_; + _zz_115_[6] = _zz_114_; + _zz_115_[5] = _zz_114_; + _zz_115_[4] = _zz_114_; + _zz_115_[3] = _zz_114_; + _zz_115_[2] = _zz_114_; + _zz_115_[1] = _zz_114_; + _zz_115_[0] = _zz_114_; + end + + assign _zz_116_ = _zz_214_[11]; + always @ (*) begin + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + assign _zz_80_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_115_,{{{_zz_267_,_zz_268_},_zz_269_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_117_,{{{_zz_270_,_zz_271_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_176_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_179_ = (IBusCachedPlugin_jump_pcLoad_valid || _zz_77_); + assign _zz_180_ = (32'b00000000000000000000000000000000); + assign _zz_177_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_178_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_188_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_189_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_190_ = (CsrPlugin_privilege == (2'b00)); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign _zz_82_ = IBusCachedPlugin_rsp_redoFetch; + assign _zz_83_ = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign _zz_181_ = _zz_84_[31]; + assign _zz_182_ = 1'b1; + assign _zz_183_ = 1'b1; + assign _zz_184_ = 1'b1; + assign _zz_185_ = 1'b1; + assign _zz_186_ = 1'b0; + assign _zz_187_ = 1'b1; + assign execute_DBusSimplePlugin_cmdSent = 1'b0; + assign _zz_69_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_INSTRUCTION[5]; + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_118_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_118_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_118_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_118_; + assign _zz_68_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_119_ = (4'b0001); + end + 2'b01 : begin + _zz_119_ = (4'b0011); + end + default : begin + _zz_119_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_119_ <<< dBus_cmd_payload_address[1 : 0]); + assign _zz_67_ = dBus_rsp_data; + assign memory_exception_agregat_payload_code = {1'd0, _zz_215_}; + always @ (*) begin + memory_exception_agregat_valid = memory_ALIGNEMENT_FAULT; + if((! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && 1'b1)))begin + memory_exception_agregat_valid = 1'b0; + end + end + + assign memory_exception_agregat_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_120_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_121_[31] = _zz_120_; + _zz_121_[30] = _zz_120_; + _zz_121_[29] = _zz_120_; + _zz_121_[28] = _zz_120_; + _zz_121_[27] = _zz_120_; + _zz_121_[26] = _zz_120_; + _zz_121_[25] = _zz_120_; + _zz_121_[24] = _zz_120_; + _zz_121_[23] = _zz_120_; + _zz_121_[22] = _zz_120_; + _zz_121_[21] = _zz_120_; + _zz_121_[20] = _zz_120_; + _zz_121_[19] = _zz_120_; + _zz_121_[18] = _zz_120_; + _zz_121_[17] = _zz_120_; + _zz_121_[16] = _zz_120_; + _zz_121_[15] = _zz_120_; + _zz_121_[14] = _zz_120_; + _zz_121_[13] = _zz_120_; + _zz_121_[12] = _zz_120_; + _zz_121_[11] = _zz_120_; + _zz_121_[10] = _zz_120_; + _zz_121_[9] = _zz_120_; + _zz_121_[8] = _zz_120_; + _zz_121_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_122_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_123_[31] = _zz_122_; + _zz_123_[30] = _zz_122_; + _zz_123_[29] = _zz_122_; + _zz_123_[28] = _zz_122_; + _zz_123_[27] = _zz_122_; + _zz_123_[26] = _zz_122_; + _zz_123_[25] = _zz_122_; + _zz_123_[24] = _zz_122_; + _zz_123_[23] = _zz_122_; + _zz_123_[22] = _zz_122_; + _zz_123_[21] = _zz_122_; + _zz_123_[20] = _zz_122_; + _zz_123_[19] = _zz_122_; + _zz_123_[18] = _zz_122_; + _zz_123_[17] = _zz_122_; + _zz_123_[16] = _zz_122_; + _zz_123_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_205_) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_121_; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_123_; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_84_ = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign _zz_125_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_126_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_127_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_128_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_129_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_124_ = {(((decode_INSTRUCTION & _zz_272_) == (32'b00000000000000000000000000010000)) != (1'b0)),{({_zz_129_,_zz_273_} != (2'b00)),{(_zz_274_ != (1'b0)),{(_zz_275_ != _zz_276_),{_zz_277_,{_zz_278_,_zz_279_}}}}}}; + assign _zz_65_ = _zz_216_[0]; + assign _zz_130_ = _zz_124_[2 : 1]; + assign _zz_64_ = _zz_130_; + assign _zz_63_ = _zz_217_[0]; + assign _zz_131_ = _zz_124_[5 : 4]; + assign _zz_62_ = _zz_131_; + assign _zz_61_ = _zz_218_[0]; + assign _zz_132_ = _zz_124_[8 : 7]; + assign _zz_60_ = _zz_132_; + assign _zz_133_ = _zz_124_[10 : 9]; + assign _zz_59_ = _zz_133_; + assign _zz_58_ = _zz_219_[0]; + assign _zz_57_ = _zz_220_[0]; + assign _zz_134_ = _zz_124_[15 : 14]; + assign _zz_56_ = _zz_134_; + assign _zz_55_ = _zz_221_[0]; + assign _zz_54_ = _zz_222_[0]; + assign _zz_135_ = _zz_124_[22 : 21]; + assign _zz_53_ = _zz_135_; + assign _zz_136_ = _zz_124_[24 : 23]; + assign _zz_52_ = _zz_136_; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_137_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_191_; + assign execute_RegFilePlugin_rs2Data = _zz_192_; + assign _zz_51_ = execute_RegFilePlugin_rs1Data; + assign _zz_50_ = execute_RegFilePlugin_rs2Data; + assign writeBack_RegFilePlugin_regFileWrite_valid = (writeBack_REGFILE_WRITE_VALID && writeBack_arbitration_isFiring); + assign writeBack_RegFilePlugin_regFileWrite_payload_address = writeBack_INSTRUCTION[11 : 7]; + assign writeBack_RegFilePlugin_regFileWrite_payload_data = _zz_66_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = execute_SRC1; + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_138_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_138_ = {31'd0, _zz_223_}; + end + default : begin + _zz_138_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_47_ = _zz_138_; + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_139_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_139_ = {29'd0, _zz_224_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_139_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_139_ = {27'd0, _zz_225_}; + end + endcase + end + + assign _zz_45_ = _zz_139_; + assign _zz_140_ = _zz_226_[11]; + always @ (*) begin + _zz_141_[19] = _zz_140_; + _zz_141_[18] = _zz_140_; + _zz_141_[17] = _zz_140_; + _zz_141_[16] = _zz_140_; + _zz_141_[15] = _zz_140_; + _zz_141_[14] = _zz_140_; + _zz_141_[13] = _zz_140_; + _zz_141_[12] = _zz_140_; + _zz_141_[11] = _zz_140_; + _zz_141_[10] = _zz_140_; + _zz_141_[9] = _zz_140_; + _zz_141_[8] = _zz_140_; + _zz_141_[7] = _zz_140_; + _zz_141_[6] = _zz_140_; + _zz_141_[5] = _zz_140_; + _zz_141_[4] = _zz_140_; + _zz_141_[3] = _zz_140_; + _zz_141_[2] = _zz_140_; + _zz_141_[1] = _zz_140_; + _zz_141_[0] = _zz_140_; + end + + assign _zz_142_ = _zz_227_[11]; + always @ (*) begin + _zz_143_[19] = _zz_142_; + _zz_143_[18] = _zz_142_; + _zz_143_[17] = _zz_142_; + _zz_143_[16] = _zz_142_; + _zz_143_[15] = _zz_142_; + _zz_143_[14] = _zz_142_; + _zz_143_[13] = _zz_142_; + _zz_143_[12] = _zz_142_; + _zz_143_[11] = _zz_142_; + _zz_143_[10] = _zz_142_; + _zz_143_[9] = _zz_142_; + _zz_143_[8] = _zz_142_; + _zz_143_[7] = _zz_142_; + _zz_143_[6] = _zz_142_; + _zz_143_[5] = _zz_142_; + _zz_143_[4] = _zz_142_; + _zz_143_[3] = _zz_142_; + _zz_143_[2] = _zz_142_; + _zz_143_[1] = _zz_142_; + _zz_143_[0] = _zz_142_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_144_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_144_ = {_zz_141_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_144_ = {_zz_143_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_144_ = _zz_41_; + end + endcase + end + + assign _zz_43_ = _zz_144_; + assign execute_SrcPlugin_addSub = _zz_228_; + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_40_ = execute_SrcPlugin_addSub; + assign _zz_39_ = execute_SrcPlugin_addSub; + assign _zz_38_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_145_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_145_ = _zz_236_; + end + endcase + end + + assign _zz_35_ = _zz_81_; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_146_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_146_ == (3'b000))) begin + _zz_147_ = execute_BranchPlugin_eq; + end else if((_zz_146_ == (3'b001))) begin + _zz_147_ = (! execute_BranchPlugin_eq); + end else if((((_zz_146_ & (3'b101)) == (3'b101)))) begin + _zz_147_ = (! execute_SRC_LESS); + end else begin + _zz_147_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_148_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_148_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_148_ = 1'b1; + end + default : begin + _zz_148_ = _zz_147_; + end + endcase + end + + assign _zz_34_ = _zz_148_; + assign _zz_149_ = _zz_238_[11]; + always @ (*) begin + _zz_150_[19] = _zz_149_; + _zz_150_[18] = _zz_149_; + _zz_150_[17] = _zz_149_; + _zz_150_[16] = _zz_149_; + _zz_150_[15] = _zz_149_; + _zz_150_[14] = _zz_149_; + _zz_150_[13] = _zz_149_; + _zz_150_[12] = _zz_149_; + _zz_150_[11] = _zz_149_; + _zz_150_[10] = _zz_149_; + _zz_150_[9] = _zz_149_; + _zz_150_[8] = _zz_149_; + _zz_150_[7] = _zz_149_; + _zz_150_[6] = _zz_149_; + _zz_150_[5] = _zz_149_; + _zz_150_[4] = _zz_149_; + _zz_150_[3] = _zz_149_; + _zz_150_[2] = _zz_149_; + _zz_150_[1] = _zz_149_; + _zz_150_[0] = _zz_149_; + end + + assign _zz_151_ = _zz_239_[19]; + always @ (*) begin + _zz_152_[10] = _zz_151_; + _zz_152_[9] = _zz_151_; + _zz_152_[8] = _zz_151_; + _zz_152_[7] = _zz_151_; + _zz_152_[6] = _zz_151_; + _zz_152_[5] = _zz_151_; + _zz_152_[4] = _zz_151_; + _zz_152_[3] = _zz_151_; + _zz_152_[2] = _zz_151_; + _zz_152_[1] = _zz_151_; + _zz_152_[0] = _zz_151_; + end + + assign _zz_153_ = _zz_240_[11]; + always @ (*) begin + _zz_154_[18] = _zz_153_; + _zz_154_[17] = _zz_153_; + _zz_154_[16] = _zz_153_; + _zz_154_[15] = _zz_153_; + _zz_154_[14] = _zz_153_; + _zz_154_[13] = _zz_153_; + _zz_154_[12] = _zz_153_; + _zz_154_[11] = _zz_153_; + _zz_154_[10] = _zz_153_; + _zz_154_[9] = _zz_153_; + _zz_154_[8] = _zz_153_; + _zz_154_[7] = _zz_153_; + _zz_154_[6] = _zz_153_; + _zz_154_[5] = _zz_153_; + _zz_154_[4] = _zz_153_; + _zz_154_[3] = _zz_153_; + _zz_154_[2] = _zz_153_; + _zz_154_[1] = _zz_153_; + _zz_154_[0] = _zz_153_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_155_ = (_zz_241_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_155_ = _zz_242_[1]; + end + default : begin + _zz_155_ = _zz_243_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_155_); + assign _zz_32_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + execute_BranchPlugin_branch_src2 = {_zz_157_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_159_,{{{_zz_382_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_161_,{{{_zz_383_,_zz_384_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if((execute_PREDICTION_HAD_BRANCHED2 && (! execute_BranchPlugin_missAlignedTarget)))begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_247_}; + end + end + endcase + end + + assign _zz_156_ = _zz_244_[11]; + always @ (*) begin + _zz_157_[19] = _zz_156_; + _zz_157_[18] = _zz_156_; + _zz_157_[17] = _zz_156_; + _zz_157_[16] = _zz_156_; + _zz_157_[15] = _zz_156_; + _zz_157_[14] = _zz_156_; + _zz_157_[13] = _zz_156_; + _zz_157_[12] = _zz_156_; + _zz_157_[11] = _zz_156_; + _zz_157_[10] = _zz_156_; + _zz_157_[9] = _zz_156_; + _zz_157_[8] = _zz_156_; + _zz_157_[7] = _zz_156_; + _zz_157_[6] = _zz_156_; + _zz_157_[5] = _zz_156_; + _zz_157_[4] = _zz_156_; + _zz_157_[3] = _zz_156_; + _zz_157_[2] = _zz_156_; + _zz_157_[1] = _zz_156_; + _zz_157_[0] = _zz_156_; + end + + assign _zz_158_ = _zz_245_[19]; + always @ (*) begin + _zz_159_[10] = _zz_158_; + _zz_159_[9] = _zz_158_; + _zz_159_[8] = _zz_158_; + _zz_159_[7] = _zz_158_; + _zz_159_[6] = _zz_158_; + _zz_159_[5] = _zz_158_; + _zz_159_[4] = _zz_158_; + _zz_159_[3] = _zz_158_; + _zz_159_[2] = _zz_158_; + _zz_159_[1] = _zz_158_; + _zz_159_[0] = _zz_158_; + end + + assign _zz_160_ = _zz_246_[11]; + always @ (*) begin + _zz_161_[18] = _zz_160_; + _zz_161_[17] = _zz_160_; + _zz_161_[16] = _zz_160_; + _zz_161_[15] = _zz_160_; + _zz_161_[14] = _zz_160_; + _zz_161_[13] = _zz_160_; + _zz_161_[12] = _zz_160_; + _zz_161_[11] = _zz_160_; + _zz_161_[10] = _zz_160_; + _zz_161_[9] = _zz_160_; + _zz_161_[8] = _zz_160_; + _zz_161_[7] = _zz_160_; + _zz_161_[6] = _zz_160_; + _zz_161_[5] = _zz_160_; + _zz_161_[4] = _zz_160_; + _zz_161_[3] = _zz_160_; + _zz_161_[2] = _zz_160_; + _zz_161_[1] = _zz_160_; + _zz_161_[0] = _zz_160_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign _zz_85_ = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign _zz_86_ = execute_BRANCH_CALC; + always @ (*) begin + _zz_87_ = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + _zz_87_ = 1'b0; + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_medeleg = (32'b00000000000000000000000000000000); + assign CsrPlugin_mideleg = (32'b00000000000000000000000000000000); + assign _zz_162_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_163_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_164_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 1'b0; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = (2'b11); + assign execute_exception_agregat_valid = ({_zz_90_,_zz_87_} != (2'b00)); + assign _zz_165_ = {_zz_90_,_zz_87_}; + assign _zz_166_ = _zz_248_[0]; + assign execute_exception_agregat_payload_code = (_zz_166_ ? (4'b0000) : _zz_91_); + assign execute_exception_agregat_payload_badAddr = (_zz_166_ ? execute_BRANCH_CALC : (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)); + assign CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(memory_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + assign CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + if(CsrPlugin_mstatus_MIE)begin + if(({_zz_164_,{_zz_163_,_zz_162_}} != (3'b000)))begin + CsrPlugin_interrupt = 1'b1; + end + if(_zz_162_)begin + CsrPlugin_interruptCode = (4'b0111); + end + if(_zz_163_)begin + CsrPlugin_interruptCode = (4'b0011); + end + if(_zz_164_)begin + CsrPlugin_interruptCode = (4'b1011); + end + end + if((! _zz_92_))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_interruptTargetPrivilege = (2'b11); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && _zz_93_); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_injector_nextPcCalc_valids_4); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + assign contextSwitching = _zz_88_; + assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_167_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_168_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((execute_INSTRUCTION[29 : 28] != CsrPlugin_privilege))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + _zz_90_ = 1'b0; + _zz_91_ = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + _zz_90_ = 1'b1; + _zz_91_ = (4'b1011); + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + _zz_90_ = 1'b1; + _zz_91_ = (4'b0011); + end + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + case(_zz_207_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readData & (~ execute_SRC1)) : (execute_CsrPlugin_readData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_168_ = (_zz_167_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_168_ != (32'b00000000000000000000000000000000)); + assign DebugPlugin_isPipBusy = (DebugPlugin_isPipActive || DebugPlugin_isPipActive_regNext); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + _zz_94_ = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_202_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + _zz_94_ = 1'b1; + debug_bus_cmd_ready = _zz_95_; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + 6'b010011 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_169_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign _zz_25_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_254_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_255_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_256_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_257_))))); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_24_ = decode_SRC2_CTRL; + assign _zz_22_ = _zz_59_; + assign _zz_42_ = decode_to_execute_SRC2_CTRL; + assign _zz_21_ = decode_SRC1_CTRL; + assign _zz_19_ = _zz_56_; + assign _zz_44_ = decode_to_execute_SRC1_CTRL; + assign _zz_18_ = decode_BRANCH_CTRL; + assign _zz_70_ = _zz_52_; + assign _zz_33_ = decode_to_execute_BRANCH_CTRL; + assign _zz_16_ = decode_ALU_CTRL; + assign _zz_14_ = _zz_60_; + assign _zz_46_ = decode_to_execute_ALU_CTRL; + assign _zz_13_ = decode_SHIFT_CTRL; + assign _zz_11_ = _zz_64_; + assign _zz_37_ = decode_to_execute_SHIFT_CTRL; + assign _zz_10_ = decode_ALU_BITWISE_CTRL; + assign _zz_8_ = _zz_53_; + assign _zz_48_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_7_ = decode_ENV_CTRL; + assign _zz_4_ = execute_ENV_CTRL; + assign _zz_2_ = memory_ENV_CTRL; + assign _zz_5_ = _zz_62_; + assign _zz_27_ = decode_to_execute_ENV_CTRL; + assign _zz_26_ = execute_to_memory_ENV_CTRL; + assign _zz_30_ = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,{execute_arbitration_flushAll,decode_arbitration_flushAll}}} != (4'b0000)); + assign execute_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,execute_arbitration_flushAll}} != (3'b000)); + assign memory_arbitration_isFlushed = ({writeBack_arbitration_flushAll,memory_arbitration_flushAll} != (2'b00)); + assign writeBack_arbitration_isFlushed = (writeBack_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_264_,_zz_172_}; + assign iBusWishbone_CTI = ((_zz_172_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + iBusWishbone_STB = 1'b0; + if(_zz_203_)begin + iBusWishbone_CYC = 1'b1; + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_173_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_174_ = (4'b0001); + end + 2'b01 : begin + _zz_174_ = (4'b0011); + end + default : begin + _zz_174_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_265_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + CsrPlugin_privilege <= (2'b11); + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_102_ <= 1'b0; + _zz_108_ <= 1'b0; + _zz_110_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mip_MEIP <= 1'b0; + CsrPlugin_mip_MTIP <= 1'b0; + CsrPlugin_mip_MSIP <= 1'b0; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_167_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_170_ <= (3'b000); + _zz_172_ <= (3'b000); + _zz_173_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_201_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_102_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + _zz_108_ <= 1'b0; + end + if(_zz_106_)begin + _zz_108_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_110_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + _zz_110_ <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if(_zz_194_)begin + if(_zz_195_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_199_)begin + CsrPlugin_privilege <= CsrPlugin_targetPrivilege; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_200_)begin + case(_zz_206_) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPIE <= 1'b1; + CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; + end + default : begin + end + endcase + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_170_) + 3'b000 : begin + if(_zz_94_)begin + _zz_170_ <= (3'b001); + end + end + 3'b001 : begin + _zz_170_ <= (3'b010); + end + 3'b010 : begin + _zz_170_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_170_ <= (3'b100); + end + end + 3'b100 : begin + _zz_170_ <= (3'b000); + end + default : begin + end + endcase + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_167_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_258_[0]; + CsrPlugin_mstatus_MIE <= _zz_259_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_260_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_261_[0]; + CsrPlugin_mie_MTIE <= _zz_262_[0]; + CsrPlugin_mie_MSIE <= _zz_263_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_203_)begin + if(iBusWishbone_ACK)begin + _zz_172_ <= (_zz_172_ + (3'b001)); + end + end + _zz_173_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_204_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_111_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); + end + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + end + if(_zz_194_)begin + if(_zz_195_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(execute_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= execute_exception_agregat_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= execute_exception_agregat_payload_badAddr; + end + if(memory_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= memory_exception_agregat_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= memory_exception_agregat_payload_badAddr; + end + if((CsrPlugin_exception || CsrPlugin_interruptJump))begin + case(CsrPlugin_privilege) + 2'b11 : begin + CsrPlugin_mepc <= writeBack_PC; + end + default : begin + end + endcase + end + if(_zz_199_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_23_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FLUSH_ALL <= decode_FLUSH_ALL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FLUSH_ALL <= execute_FLUSH_ALL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_20_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_15_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_12_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_9_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_72_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_71_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_204_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipActive <= ({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)); + DebugPlugin_isPipActive_regNext <= DebugPlugin_isPipActive; + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_66_; + end + _zz_169_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_202_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_196_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; + end else begin + if(debug_bus_cmd_valid)begin + case(_zz_202_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_250_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_251_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_252_[0]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_valid <= _zz_253_[0]; + end + end + default : begin + end + endcase + end + if(_zz_196_)begin + if(_zz_197_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_198_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + if((DebugPlugin_stepIt && ({writeBack_arbitration_redoIt,{memory_arbitration_redoIt,{execute_arbitration_redoIt,decode_arbitration_redoIt}}} != (4'b0000))))begin + DebugPlugin_haltIt <= 1'b0; + end + end + end + + always @ (posedge clk) begin + _zz_171_ <= debug_bus_cmd_payload_data; + end + +endmodule + diff --git a/hw/4-stage-1024-cache-debug.yaml b/hw/4-stage-1024-cache-debug.yaml new file mode 100644 index 0000000..156f2e4 --- /dev/null +++ b/hw/4-stage-1024-cache-debug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} +iBus: !!vexriscv.BusReport + flushInstructions: [16399, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} + kind: cached diff --git a/hw/4-stage-no-cache-debug.v b/hw/4-stage-no-cache-debug.v new file mode 100644 index 0000000..3336aff --- /dev/null +++ b/hw/4-stage-no-cache-debug.v @@ -0,0 +1,4099 @@ +// Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26 +// Date : 26/03/2019, 08:00:39 +// Component : VexRiscv + + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +module InstructionCache ( + input io_flush_cmd_valid, + output io_flush_cmd_ready, + output io_flush_rsp, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_allowUser, + input io_cpu_fetch_mmuBus_rsp_miss, + input io_cpu_fetch_mmuBus_rsp_hit, + output io_cpu_fetch_mmuBus_end, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuMiss, + output io_cpu_decode_illegalAccess, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [23:0] _zz_12_; + reg [31:0] _zz_13_; + wire _zz_14_; + wire [0:0] _zz_15_; + wire [0:0] _zz_16_; + wire [23:0] _zz_17_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg [5:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_flushFromInterface; + wire _zz_4_; + reg _zz_4__regNext; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [4:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [7:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_5_; + wire [4:0] _zz_6_; + wire _zz_7_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_8_; + wire [7:0] _zz_9_; + wire _zz_10_; + wire [31:0] fetchStage_read_waysValues_0_data; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_allowUser; + reg decodeStage_mmuRsp_miss; + reg decodeStage_mmuRsp_hit; + reg decodeStage_hit_tags_0_valid; + reg decodeStage_hit_tags_0_error; + reg [21:0] decodeStage_hit_tags_0_address; + wire decodeStage_hit_hits_0; + wire decodeStage_hit_valid; + wire decodeStage_hit_error; + reg [31:0] _zz_11_; + wire [31:0] decodeStage_hit_data; + reg [31:0] decodeStage_hit_word; + reg io_cpu_fetch_dataBypassValid_regNextWhen; + reg [31:0] io_cpu_fetch_dataBypass_regNextWhen; + reg [23:0] ways_0_tags [0:31]; + reg [31:0] ways_0_datas [0:255]; + assign _zz_14_ = (! lineLoader_flushCounter[5]); + assign _zz_15_ = _zz_8_[0 : 0]; + assign _zz_16_ = _zz_8_[1 : 1]; + assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_; + end + end + + always @ (posedge clk) begin + if(_zz_7_) begin + _zz_12_ <= ways_0_tags[_zz_6_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_10_) begin + _zz_13_ <= ways_0_datas[_zz_9_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = 1'b0; + if(lineLoader_valid)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(_zz_14_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush_cmd_valid)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid)); + assign _zz_4_ = lineLoader_flushCounter[5]; + assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_5_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_6_ = io_cpu_prefetch_pc[9 : 5]; + assign _zz_7_ = (! io_cpu_fetch_isStuck); + assign _zz_8_ = _zz_12_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2]; + assign _zz_9_ = io_cpu_prefetch_pc[9 : 2]; + assign _zz_10_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_13_; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]); + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10])); + assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); + assign decodeStage_hit_error = decodeStage_hit_tags_0_error; + assign decodeStage_hit_data = _zz_11_; + always @ (*) begin + decodeStage_hit_word = decodeStage_hit_data[31 : 0]; + if(io_cpu_fetch_dataBypassValid_regNextWhen)begin + decodeStage_hit_word = io_cpu_fetch_dataBypass_regNextWhen; + end + end + + assign io_cpu_decode_data = decodeStage_hit_word; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuMiss = decodeStage_mmuRsp_miss; + assign io_cpu_decode_illegalAccess = ((! decodeStage_mmuRsp_allowExecute) || (io_cpu_decode_isUser && (! decodeStage_mmuRsp_allowUser))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushCounter <= (6'b000000); + lineLoader_flushFromInterface <= 1'b0; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(_zz_14_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); + end + if(io_flush_cmd_valid)begin + if(io_flush_cmd_ready)begin + lineLoader_flushCounter <= (6'b000000); + lineLoader_flushFromInterface <= 1'b1; + end + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + _zz_3_ <= lineLoader_flushCounter[5]; + _zz_4__regNext <= _zz_4_; + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_allowUser <= io_cpu_fetch_mmuBus_rsp_allowUser; + decodeStage_mmuRsp_miss <= io_cpu_fetch_mmuBus_rsp_miss; + decodeStage_mmuRsp_hit <= io_cpu_fetch_mmuBus_rsp_hit; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; + decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; + decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; + end + if((! io_cpu_decode_isStuck))begin + _zz_11_ <= fetchStage_read_waysValues_0_data; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_dataBypassValid_regNextWhen <= io_cpu_fetch_dataBypassValid; + end + end + + always @ (posedge clk) begin + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_dataBypass_regNextWhen <= io_cpu_fetch_dataBypass; + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset, + input debugReset); + reg _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire [31:0] _zz_180_; + wire _zz_181_; + wire _zz_182_; + wire _zz_183_; + wire _zz_184_; + wire _zz_185_; + wire _zz_186_; + wire _zz_187_; + wire _zz_188_; + wire _zz_189_; + wire _zz_190_; + reg [31:0] _zz_191_; + reg [31:0] _zz_192_; + reg [31:0] _zz_193_; + wire IBusCachedPlugin_cache_io_flush_cmd_ready; + wire IBusCachedPlugin_cache_io_flush_rsp; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuMiss; + wire IBusCachedPlugin_cache_io_cpu_decode_illegalAccess; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_194_; + wire _zz_195_; + wire _zz_196_; + wire _zz_197_; + wire _zz_198_; + wire _zz_199_; + wire _zz_200_; + wire _zz_201_; + wire [5:0] _zz_202_; + wire _zz_203_; + wire _zz_204_; + wire [1:0] _zz_205_; + wire [1:0] _zz_206_; + wire _zz_207_; + wire [3:0] _zz_208_; + wire [2:0] _zz_209_; + wire [31:0] _zz_210_; + wire [11:0] _zz_211_; + wire [31:0] _zz_212_; + wire [19:0] _zz_213_; + wire [11:0] _zz_214_; + wire [2:0] _zz_215_; + wire [0:0] _zz_216_; + wire [0:0] _zz_217_; + wire [0:0] _zz_218_; + wire [0:0] _zz_219_; + wire [0:0] _zz_220_; + wire [0:0] _zz_221_; + wire [0:0] _zz_222_; + wire [0:0] _zz_223_; + wire [2:0] _zz_224_; + wire [4:0] _zz_225_; + wire [11:0] _zz_226_; + wire [11:0] _zz_227_; + wire [31:0] _zz_228_; + wire [31:0] _zz_229_; + wire [31:0] _zz_230_; + wire [31:0] _zz_231_; + wire [1:0] _zz_232_; + wire [31:0] _zz_233_; + wire [1:0] _zz_234_; + wire [1:0] _zz_235_; + wire [31:0] _zz_236_; + wire [32:0] _zz_237_; + wire [11:0] _zz_238_; + wire [19:0] _zz_239_; + wire [11:0] _zz_240_; + wire [31:0] _zz_241_; + wire [31:0] _zz_242_; + wire [31:0] _zz_243_; + wire [11:0] _zz_244_; + wire [19:0] _zz_245_; + wire [11:0] _zz_246_; + wire [2:0] _zz_247_; + wire [1:0] _zz_248_; + wire [1:0] _zz_249_; + wire [0:0] _zz_250_; + wire [0:0] _zz_251_; + wire [0:0] _zz_252_; + wire [0:0] _zz_253_; + wire [30:0] _zz_254_; + wire [30:0] _zz_255_; + wire [30:0] _zz_256_; + wire [30:0] _zz_257_; + wire [0:0] _zz_258_; + wire [0:0] _zz_259_; + wire [0:0] _zz_260_; + wire [0:0] _zz_261_; + wire [0:0] _zz_262_; + wire [0:0] _zz_263_; + wire [26:0] _zz_264_; + wire [6:0] _zz_265_; + wire [1:0] _zz_266_; + wire [0:0] _zz_267_; + wire [7:0] _zz_268_; + wire _zz_269_; + wire [0:0] _zz_270_; + wire [0:0] _zz_271_; + wire [31:0] _zz_272_; + wire _zz_273_; + wire _zz_274_; + wire [1:0] _zz_275_; + wire [1:0] _zz_276_; + wire _zz_277_; + wire [0:0] _zz_278_; + wire [19:0] _zz_279_; + wire [31:0] _zz_280_; + wire [31:0] _zz_281_; + wire [0:0] _zz_282_; + wire [0:0] _zz_283_; + wire [0:0] _zz_284_; + wire [2:0] _zz_285_; + wire [0:0] _zz_286_; + wire [0:0] _zz_287_; + wire _zz_288_; + wire [0:0] _zz_289_; + wire [16:0] _zz_290_; + wire [31:0] _zz_291_; + wire [31:0] _zz_292_; + wire [31:0] _zz_293_; + wire [31:0] _zz_294_; + wire [31:0] _zz_295_; + wire _zz_296_; + wire _zz_297_; + wire [31:0] _zz_298_; + wire [0:0] _zz_299_; + wire [3:0] _zz_300_; + wire [0:0] _zz_301_; + wire [0:0] _zz_302_; + wire [0:0] _zz_303_; + wire [0:0] _zz_304_; + wire _zz_305_; + wire [0:0] _zz_306_; + wire [13:0] _zz_307_; + wire [31:0] _zz_308_; + wire [31:0] _zz_309_; + wire [31:0] _zz_310_; + wire [31:0] _zz_311_; + wire _zz_312_; + wire [0:0] _zz_313_; + wire [1:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire [31:0] _zz_317_; + wire [31:0] _zz_318_; + wire [0:0] _zz_319_; + wire [0:0] _zz_320_; + wire [1:0] _zz_321_; + wire [1:0] _zz_322_; + wire _zz_323_; + wire [0:0] _zz_324_; + wire [11:0] _zz_325_; + wire [31:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [31:0] _zz_329_; + wire [31:0] _zz_330_; + wire [31:0] _zz_331_; + wire [31:0] _zz_332_; + wire _zz_333_; + wire [1:0] _zz_334_; + wire [1:0] _zz_335_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [8:0] _zz_338_; + wire [31:0] _zz_339_; + wire [31:0] _zz_340_; + wire [31:0] _zz_341_; + wire [31:0] _zz_342_; + wire _zz_343_; + wire [0:0] _zz_344_; + wire [0:0] _zz_345_; + wire [2:0] _zz_346_; + wire [2:0] _zz_347_; + wire _zz_348_; + wire [0:0] _zz_349_; + wire [5:0] _zz_350_; + wire [31:0] _zz_351_; + wire [31:0] _zz_352_; + wire [31:0] _zz_353_; + wire _zz_354_; + wire _zz_355_; + wire [31:0] _zz_356_; + wire [31:0] _zz_357_; + wire _zz_358_; + wire [0:0] _zz_359_; + wire [0:0] _zz_360_; + wire _zz_361_; + wire [0:0] _zz_362_; + wire [2:0] _zz_363_; + wire [31:0] _zz_364_; + wire _zz_365_; + wire [0:0] _zz_366_; + wire [1:0] _zz_367_; + wire [0:0] _zz_368_; + wire [0:0] _zz_369_; + wire _zz_370_; + wire _zz_371_; + wire [31:0] _zz_372_; + wire [31:0] _zz_373_; + wire [31:0] _zz_374_; + wire [31:0] _zz_375_; + wire [31:0] _zz_376_; + wire [31:0] _zz_377_; + wire [31:0] _zz_378_; + wire [31:0] _zz_379_; + wire [31:0] _zz_380_; + wire [31:0] _zz_381_; + wire _zz_382_; + wire _zz_383_; + wire _zz_384_; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire decode_PREDICTION_HAD_BRANCHED2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_9_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_10_; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13_; + wire decode_DO_EBREAK; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_14_; + wire `AluCtrlEnum_defaultEncoding_type _zz_15_; + wire `AluCtrlEnum_defaultEncoding_type _zz_16_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_17_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_18_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_19_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_20_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_21_; + wire decode_CSR_READ_OPCODE; + wire decode_SRC_USE_SUB_LESS; + wire decode_CSR_WRITE_OPCODE; + wire execute_FLUSH_ALL; + wire decode_FLUSH_ALL; + wire decode_SRC_LESS_UNSIGNED; + wire writeBack_REGFILE_WRITE_VALID; + wire memory_REGFILE_WRITE_VALID; + wire execute_REGFILE_WRITE_VALID; + wire [31:0] memory_MEMORY_READ_DATA; + wire decode_IS_CSR; + wire decode_MEMORY_ENABLE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_24_; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire _zz_25_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; + wire _zz_28_; + wire _zz_29_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_31_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_32_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_33_; + wire _zz_34_; + wire _zz_35_; + reg [31:0] _zz_36_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_37_; + wire _zz_38_; + wire [31:0] _zz_39_; + wire [31:0] _zz_40_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42_; + wire [31:0] _zz_43_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_44_; + wire [31:0] _zz_45_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_46_; + wire [31:0] _zz_47_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_48_; + reg _zz_49_; + wire [31:0] _zz_50_; + wire [31:0] _zz_51_; + reg decode_REGFILE_WRITE_VALID; + wire `BranchCtrlEnum_defaultEncoding_type _zz_52_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53_; + wire _zz_54_; + wire _zz_55_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56_; + wire _zz_57_; + wire _zz_58_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_59_; + wire `AluCtrlEnum_defaultEncoding_type _zz_60_; + wire _zz_61_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_62_; + wire _zz_63_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_64_; + wire _zz_65_; + reg [31:0] _zz_66_; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_INSTRUCTION; + wire memory_MEMORY_ENABLE; + wire [31:0] _zz_67_; + wire [1:0] _zz_68_; + wire [31:0] execute_RS2; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_INSTRUCTION; + wire execute_ALIGNEMENT_FAULT; + wire execute_MEMORY_ENABLE; + wire _zz_69_; + wire memory_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_70_; + reg [31:0] _zz_71_; + reg [31:0] _zz_72_; + wire [31:0] _zz_73_; + wire [31:0] _zz_74_; + wire [31:0] _zz_75_; + wire [31:0] writeBack_PC /* verilator public */ ; + wire [31:0] writeBack_INSTRUCTION /* verilator public */ ; + wire [31:0] decode_PC /* verilator public */ ; + reg [31:0] decode_INSTRUCTION /* verilator public */ ; + reg decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + wire decode_arbitration_redoIt; + reg decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + wire execute_arbitration_redoIt; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushAll; + wire memory_arbitration_redoIt; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushAll; + wire writeBack_arbitration_redoIt; + reg writeBack_arbitration_isValid /* verilator public */ ; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring /* verilator public */ ; + reg _zz_76_; + reg _zz_77_; + reg _zz_78_; + wire _zz_79_; + wire [31:0] _zz_80_; + wire _zz_81_; + wire _zz_82_; + wire [31:0] _zz_83_; + wire [31:0] _zz_84_; + reg memory_exception_agregat_valid; + wire [3:0] memory_exception_agregat_payload_code; + wire [31:0] memory_exception_agregat_payload_badAddr; + wire _zz_85_; + wire [31:0] _zz_86_; + reg _zz_87_; + reg _zz_88_; + reg [31:0] _zz_89_; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg _zz_90_; + reg [3:0] _zz_91_; + reg _zz_92_; + reg _zz_93_; + reg _zz_94_; + reg _zz_95_; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_96_; + wire [3:0] _zz_97_; + wire _zz_98_; + wire _zz_99_; + wire _zz_100_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_101_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_102_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_103_; + wire _zz_104_; + wire _zz_105_; + wire _zz_106_; + wire _zz_107_; + reg _zz_108_; + wire _zz_109_; + reg _zz_110_; + reg [31:0] _zz_111_; + wire IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + reg IBusCachedPlugin_injector_decodeRemoved; + wire _zz_112_; + reg [18:0] _zz_113_; + wire _zz_114_; + reg [10:0] _zz_115_; + wire _zz_116_; + reg [18:0] _zz_117_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire execute_DBusSimplePlugin_cmdSent; + reg [31:0] _zz_118_; + reg [3:0] _zz_119_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_120_; + reg [31:0] _zz_121_; + wire _zz_122_; + reg [31:0] _zz_123_; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [25:0] _zz_124_; + wire _zz_125_; + wire _zz_126_; + wire _zz_127_; + wire _zz_128_; + wire _zz_129_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_130_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_131_; + wire `AluCtrlEnum_defaultEncoding_type _zz_132_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_133_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_134_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_135_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_136_; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire _zz_137_; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire writeBack_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_138_; + reg [31:0] _zz_139_; + wire _zz_140_; + reg [19:0] _zz_141_; + wire _zz_142_; + reg [19:0] _zz_143_; + reg [31:0] _zz_144_; + wire [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_145_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_146_; + reg _zz_147_; + reg _zz_148_; + wire _zz_149_; + reg [19:0] _zz_150_; + wire _zz_151_; + reg [10:0] _zz_152_; + wire _zz_153_; + reg [18:0] _zz_154_; + reg _zz_155_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_156_; + reg [19:0] _zz_157_; + wire _zz_158_; + reg [10:0] _zz_159_; + wire _zz_160_; + reg [18:0] _zz_161_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire [31:0] CsrPlugin_medeleg; + wire [31:0] CsrPlugin_mideleg; + wire _zz_162_; + wire _zz_163_; + wire _zz_164_; + wire CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + wire CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + wire CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire execute_exception_agregat_valid; + wire [3:0] execute_exception_agregat_payload_code; + wire [31:0] execute_exception_agregat_payload_badAddr; + wire [1:0] _zz_165_; + wire _zz_166_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + wire [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_167_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_168_; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipActive; + reg DebugPlugin_isPipActive_regNext; + wire DebugPlugin_isPipBusy; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_169_; + reg DebugPlugin_resetIt_regNext; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg decode_to_execute_IS_CSR; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg decode_to_execute_FLUSH_ALL; + reg execute_to_memory_FLUSH_ALL; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg decode_to_execute_CSR_READ_OPCODE; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_DO_EBREAK; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [2:0] _zz_170_; + reg [31:0] _zz_171_; + reg [2:0] _zz_172_; + reg _zz_173_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_174_; + `ifndef SYNTHESIS + reg [47:0] _zz_1__string; + reg [47:0] _zz_2__string; + reg [47:0] _zz_3__string; + reg [47:0] _zz_4__string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_5__string; + reg [47:0] _zz_6__string; + reg [47:0] _zz_7__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_8__string; + reg [39:0] _zz_9__string; + reg [39:0] _zz_10__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_11__string; + reg [71:0] _zz_12__string; + reg [71:0] _zz_13__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_14__string; + reg [63:0] _zz_15__string; + reg [63:0] _zz_16__string; + reg [31:0] _zz_17__string; + reg [31:0] _zz_18__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_19__string; + reg [95:0] _zz_20__string; + reg [95:0] _zz_21__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_22__string; + reg [23:0] _zz_23__string; + reg [23:0] _zz_24__string; + reg [47:0] memory_ENV_CTRL_string; + reg [47:0] _zz_26__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_27__string; + reg [47:0] writeBack_ENV_CTRL_string; + reg [47:0] _zz_30__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_33__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_37__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_44__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_46__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_48__string; + reg [31:0] _zz_52__string; + reg [39:0] _zz_53__string; + reg [95:0] _zz_56__string; + reg [23:0] _zz_59__string; + reg [63:0] _zz_60__string; + reg [47:0] _zz_62__string; + reg [71:0] _zz_64__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_70__string; + reg [71:0] _zz_130__string; + reg [47:0] _zz_131__string; + reg [63:0] _zz_132__string; + reg [23:0] _zz_133__string; + reg [95:0] _zz_134__string; + reg [39:0] _zz_135__string; + reg [31:0] _zz_136__string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [47:0] execute_to_memory_ENV_CTRL_string; + reg [47:0] memory_to_writeBack_ENV_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_194_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_195_ = (! execute_arbitration_isStuckByOthers); + assign _zz_196_ = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_197_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); + assign _zz_198_ = (DebugPlugin_stepIt && _zz_78_); + assign _zz_199_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_200_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_201_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_202_ = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_203_ = (iBus_cmd_valid || (_zz_172_ != (3'b000))); + assign _zz_204_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_205_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_206_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_207_ = execute_INSTRUCTION[13]; + assign _zz_208_ = (_zz_96_ - (4'b0001)); + assign _zz_209_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_210_ = {29'd0, _zz_209_}; + assign _zz_211_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_212_ = {{_zz_113_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_213_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_214_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_215_ = (memory_INSTRUCTION[5] ? (3'b110) : (3'b100)); + assign _zz_216_ = _zz_124_[0 : 0]; + assign _zz_217_ = _zz_124_[3 : 3]; + assign _zz_218_ = _zz_124_[6 : 6]; + assign _zz_219_ = _zz_124_[12 : 12]; + assign _zz_220_ = _zz_124_[13 : 13]; + assign _zz_221_ = _zz_124_[17 : 17]; + assign _zz_222_ = _zz_124_[18 : 18]; + assign _zz_223_ = execute_SRC_LESS; + assign _zz_224_ = (3'b100); + assign _zz_225_ = execute_INSTRUCTION[19 : 15]; + assign _zz_226_ = execute_INSTRUCTION[31 : 20]; + assign _zz_227_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_228_ = ($signed(_zz_229_) + $signed(_zz_233_)); + assign _zz_229_ = ($signed(_zz_230_) + $signed(_zz_231_)); + assign _zz_230_ = execute_SRC1; + assign _zz_231_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_232_ = (execute_SRC_USE_SUB_LESS ? _zz_234_ : _zz_235_); + assign _zz_233_ = {{30{_zz_232_[1]}}, _zz_232_}; + assign _zz_234_ = (2'b01); + assign _zz_235_ = (2'b00); + assign _zz_236_ = (_zz_237_ >>> 1); + assign _zz_237_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_238_ = execute_INSTRUCTION[31 : 20]; + assign _zz_239_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_240_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_241_ = {_zz_150_,execute_INSTRUCTION[31 : 20]}; + assign _zz_242_ = {{_zz_152_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_243_ = {{_zz_154_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_244_ = execute_INSTRUCTION[31 : 20]; + assign _zz_245_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_246_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_247_ = (3'b100); + assign _zz_248_ = (_zz_165_ & (~ _zz_249_)); + assign _zz_249_ = (_zz_165_ - (2'b01)); + assign _zz_250_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_251_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_252_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_253_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_254_ = (decode_PC >>> 1); + assign _zz_255_ = (decode_PC >>> 1); + assign _zz_256_ = (decode_PC >>> 1); + assign _zz_257_ = (decode_PC >>> 1); + assign _zz_258_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_259_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_260_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_261_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_262_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_263_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_264_ = (iBus_cmd_payload_address >>> 5); + assign _zz_265_ = ({3'd0,_zz_174_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_266_ = {_zz_100_,_zz_99_}; + assign _zz_267_ = decode_INSTRUCTION[31]; + assign _zz_268_ = decode_INSTRUCTION[19 : 12]; + assign _zz_269_ = decode_INSTRUCTION[20]; + assign _zz_270_ = decode_INSTRUCTION[31]; + assign _zz_271_ = decode_INSTRUCTION[7]; + assign _zz_272_ = (32'b00000000000000000000000000010000); + assign _zz_273_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000000000000000100)); + assign _zz_274_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); + assign _zz_275_ = {(_zz_280_ == _zz_281_),_zz_126_}; + assign _zz_276_ = (2'b00); + assign _zz_277_ = ({_zz_126_,{_zz_282_,_zz_283_}} != (3'b000)); + assign _zz_278_ = ({_zz_284_,_zz_285_} != (4'b0000)); + assign _zz_279_ = {(_zz_286_ != _zz_287_),{_zz_288_,{_zz_289_,_zz_290_}}}; + assign _zz_280_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); + assign _zz_281_ = (32'b00000000000000000001000000000000); + assign _zz_282_ = ((decode_INSTRUCTION & _zz_291_) == (32'b00000000000000000001000000000000)); + assign _zz_283_ = ((decode_INSTRUCTION & _zz_292_) == (32'b00000000000000000010000000000000)); + assign _zz_284_ = ((decode_INSTRUCTION & _zz_293_) == (32'b00000000000000000000000000000000)); + assign _zz_285_ = {(_zz_294_ == _zz_295_),{_zz_296_,_zz_297_}}; + assign _zz_286_ = ((decode_INSTRUCTION & _zz_298_) == (32'b00000000000000000000000000000000)); + assign _zz_287_ = (1'b0); + assign _zz_288_ = ({_zz_129_,{_zz_299_,_zz_300_}} != (6'b000000)); + assign _zz_289_ = ({_zz_301_,_zz_302_} != (2'b00)); + assign _zz_290_ = {(_zz_303_ != _zz_304_),{_zz_305_,{_zz_306_,_zz_307_}}}; + assign _zz_291_ = (32'b00000000000000000011000000000000); + assign _zz_292_ = (32'b00000000000000000011000000000000); + assign _zz_293_ = (32'b00000000000000000000000001000100); + assign _zz_294_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); + assign _zz_295_ = (32'b00000000000000000000000000000000); + assign _zz_296_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000000000000)); + assign _zz_297_ = ((decode_INSTRUCTION & _zz_309_) == (32'b00000000000000000001000000000000)); + assign _zz_298_ = (32'b00000000000000000000000000000000); + assign _zz_299_ = (_zz_310_ == _zz_311_); + assign _zz_300_ = {_zz_312_,{_zz_313_,_zz_314_}}; + assign _zz_301_ = (_zz_315_ == _zz_316_); + assign _zz_302_ = (_zz_317_ == _zz_318_); + assign _zz_303_ = _zz_128_; + assign _zz_304_ = (1'b0); + assign _zz_305_ = ({_zz_319_,_zz_320_} != (2'b00)); + assign _zz_306_ = (_zz_321_ != _zz_322_); + assign _zz_307_ = {_zz_323_,{_zz_324_,_zz_325_}}; + assign _zz_308_ = (32'b00000000000000000110000000000100); + assign _zz_309_ = (32'b00000000000000000101000000000100); + assign _zz_310_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_311_ = (32'b00000000000000000001000000010000); + assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); + assign _zz_313_ = _zz_128_; + assign _zz_314_ = {(_zz_326_ == _zz_327_),(_zz_328_ == _zz_329_)}; + assign _zz_315_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_316_ = (32'b00000000000000000001000001010000); + assign _zz_317_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_318_ = (32'b00000000000000000010000001010000); + assign _zz_319_ = ((decode_INSTRUCTION & _zz_330_) == (32'b00000000000000000000000000000100)); + assign _zz_320_ = _zz_127_; + assign _zz_321_ = {(_zz_331_ == _zz_332_),_zz_127_}; + assign _zz_322_ = (2'b00); + assign _zz_323_ = (_zz_125_ != (1'b0)); + assign _zz_324_ = (_zz_333_ != (1'b0)); + assign _zz_325_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}; + assign _zz_326_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_327_ = (32'b00000000000000000000000000000000); + assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_329_ = (32'b00000000000000000000000000000100); + assign _zz_330_ = (32'b00000000000000000000000000010100); + assign _zz_331_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_332_ = (32'b00000000000000000000000000000100); + assign _zz_333_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); + assign _zz_334_ = {(_zz_339_ == _zz_340_),(_zz_341_ == _zz_342_)}; + assign _zz_335_ = (2'b00); + assign _zz_336_ = ({_zz_126_,_zz_343_} != (2'b00)); + assign _zz_337_ = ({_zz_344_,_zz_345_} != (2'b00)); + assign _zz_338_ = {(_zz_346_ != _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}; + assign _zz_339_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_340_ = (32'b00000000000000000000000000100000); + assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_342_ = (32'b00000000000000000000000000100000); + assign _zz_343_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); + assign _zz_344_ = _zz_126_; + assign _zz_345_ = ((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000000)); + assign _zz_346_ = {(_zz_352_ == _zz_353_),{_zz_354_,_zz_355_}}; + assign _zz_347_ = (3'b000); + assign _zz_348_ = ((_zz_356_ == _zz_357_) != (1'b0)); + assign _zz_349_ = (_zz_358_ != (1'b0)); + assign _zz_350_ = {(_zz_359_ != _zz_360_),{_zz_361_,{_zz_362_,_zz_363_}}}; + assign _zz_351_ = (32'b00000000000000000000000000100000); + assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_353_ = (32'b00000000000000000000000000100100); + assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000)); + assign _zz_355_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000010100)) == (32'b00000000000000000001000000010000)); + assign _zz_356_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); + assign _zz_357_ = (32'b00000000000000000010000000010000); + assign _zz_358_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001001000)) == (32'b00000000000000000000000000001000)); + assign _zz_359_ = ((decode_INSTRUCTION & _zz_364_) == (32'b00000000000000000000000001010000)); + assign _zz_360_ = (1'b0); + assign _zz_361_ = ({_zz_125_,_zz_365_} != (2'b00)); + assign _zz_362_ = ({_zz_366_,_zz_367_} != (3'b000)); + assign _zz_363_ = {(_zz_368_ != _zz_369_),{_zz_370_,_zz_371_}}; + assign _zz_364_ = (32'b00010000000000000011000001010000); + assign _zz_365_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_366_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); + assign _zz_367_ = {((decode_INSTRUCTION & _zz_372_) == (32'b01000000000000000000000000110000)),((decode_INSTRUCTION & _zz_373_) == (32'b00000000000000000010000000010000))}; + assign _zz_368_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000101000000010000)); + assign _zz_369_ = (1'b0); + assign _zz_370_ = ({(_zz_374_ == _zz_375_),(_zz_376_ == _zz_377_)} != (2'b00)); + assign _zz_371_ = ({(_zz_378_ == _zz_379_),(_zz_380_ == _zz_381_)} != (2'b00)); + assign _zz_372_ = (32'b01000000000000000000000000110000); + assign _zz_373_ = (32'b00000000000000000010000000010100); + assign _zz_374_ = (decode_INSTRUCTION & (32'b01000000000000000011000001010100)); + assign _zz_375_ = (32'b01000000000000000001000000010000); + assign _zz_376_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); + assign _zz_377_ = (32'b00000000000000000001000000010000); + assign _zz_378_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_379_ = (32'b00000000000000000010000000000000); + assign _zz_380_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); + assign _zz_381_ = (32'b00000000000000000001000000000000); + assign _zz_382_ = execute_INSTRUCTION[31]; + assign _zz_383_ = execute_INSTRUCTION[31]; + assign _zz_384_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_49_) begin + RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_137_) begin + _zz_191_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_137_) begin + _zz_192_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush_cmd_valid(_zz_175_), + .io_flush_cmd_ready(IBusCachedPlugin_cache_io_flush_cmd_ready), + .io_flush_rsp(IBusCachedPlugin_cache_io_flush_rsp), + .io_cpu_prefetch_isValid(_zz_176_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_177_), + .io_cpu_fetch_isStuck(_zz_178_), + .io_cpu_fetch_isRemoved(_zz_179_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_180_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(_zz_84_), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_181_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_182_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_183_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_184_), + .io_cpu_fetch_mmuBus_rsp_allowUser(_zz_185_), + .io_cpu_fetch_mmuBus_rsp_miss(_zz_186_), + .io_cpu_fetch_mmuBus_rsp_hit(_zz_187_), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_decode_isValid(_zz_188_), + .io_cpu_decode_isStuck(_zz_189_), + .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), + .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), + .io_cpu_decode_mmuMiss(IBusCachedPlugin_cache_io_cpu_decode_mmuMiss), + .io_cpu_decode_illegalAccess(IBusCachedPlugin_cache_io_cpu_decode_illegalAccess), + .io_cpu_decode_isUser(_zz_190_), + .io_cpu_fill_valid(IBusCachedPlugin_rsp_redoFetch), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_266_) + 2'b00 : begin + _zz_193_ = _zz_89_; + end + 2'b01 : begin + _zz_193_ = _zz_86_; + end + 2'b10 : begin + _zz_193_ = _zz_83_; + end + default : begin + _zz_193_ = _zz_80_; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_1__string = "EBREAK"; + default : _zz_1__string = "??????"; + endcase + end + always @(*) begin + case(_zz_2_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_2__string = "EBREAK"; + default : _zz_2__string = "??????"; + endcase + end + always @(*) begin + case(_zz_3_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_3__string = "EBREAK"; + default : _zz_3__string = "??????"; + endcase + end + always @(*) begin + case(_zz_4_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_4__string = "EBREAK"; + default : _zz_4__string = "??????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_5_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_5__string = "EBREAK"; + default : _zz_5__string = "??????"; + endcase + end + always @(*) begin + case(_zz_6_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_6__string = "EBREAK"; + default : _zz_6__string = "??????"; + endcase + end + always @(*) begin + case(_zz_7_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_7__string = "EBREAK"; + default : _zz_7__string = "??????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_8__string = "SRC1 "; + default : _zz_8__string = "?????"; + endcase + end + always @(*) begin + case(_zz_9_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_9__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_9__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_9__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_9__string = "SRC1 "; + default : _zz_9__string = "?????"; + endcase + end + always @(*) begin + case(_zz_10_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_10__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_10__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_10__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_10__string = "SRC1 "; + default : _zz_10__string = "?????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11__string = "SRA_1 "; + default : _zz_11__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12__string = "SRA_1 "; + default : _zz_12__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13__string = "SRA_1 "; + default : _zz_13__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_14_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_14__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_14__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_14__string = "BITWISE "; + default : _zz_14__string = "????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_15__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_15__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_15__string = "BITWISE "; + default : _zz_15__string = "????????"; + endcase + end + always @(*) begin + case(_zz_16_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_16__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_16__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_16__string = "BITWISE "; + default : _zz_16__string = "????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_17__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_17__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_17__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_17__string = "JALR"; + default : _zz_17__string = "????"; + endcase + end + always @(*) begin + case(_zz_18_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_18__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_18__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_18__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_18__string = "JALR"; + default : _zz_18__string = "????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_19_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_19__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_19__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_19__string = "URS1 "; + default : _zz_19__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_20_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_20__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_20__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_20__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_20__string = "URS1 "; + default : _zz_20__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_21_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_21__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_21__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_21__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_21__string = "URS1 "; + default : _zz_21__string = "????????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_22_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22__string = "PC "; + default : _zz_22__string = "???"; + endcase + end + always @(*) begin + case(_zz_23_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23__string = "PC "; + default : _zz_23__string = "???"; + endcase + end + always @(*) begin + case(_zz_24_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_24__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_24__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_24__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_24__string = "PC "; + default : _zz_24__string = "???"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : memory_ENV_CTRL_string = "EBREAK"; + default : memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_26_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_26__string = "EBREAK"; + default : _zz_26__string = "??????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_27_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_27__string = "EBREAK"; + default : _zz_27__string = "??????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; + default : writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_30_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_30__string = "EBREAK"; + default : _zz_30__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_33_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_33__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_33__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_33__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_33__string = "JALR"; + default : _zz_33__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_37_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37__string = "SRA_1 "; + default : _zz_37__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42__string = "PC "; + default : _zz_42__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_44_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_44__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_44__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_44__string = "URS1 "; + default : _zz_44__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_46_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_46__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_46__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_46__string = "BITWISE "; + default : _zz_46__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_48_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_48__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_48__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_48__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_48__string = "SRC1 "; + default : _zz_48__string = "?????"; + endcase + end + always @(*) begin + case(_zz_52_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_52__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_52__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_52__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_52__string = "JALR"; + default : _zz_52__string = "????"; + endcase + end + always @(*) begin + case(_zz_53_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_53__string = "SRC1 "; + default : _zz_53__string = "?????"; + endcase + end + always @(*) begin + case(_zz_56_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56__string = "URS1 "; + default : _zz_56__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_59_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_59__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_59__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_59__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_59__string = "PC "; + default : _zz_59__string = "???"; + endcase + end + always @(*) begin + case(_zz_60_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE "; + default : _zz_60__string = "????????"; + endcase + end + always @(*) begin + case(_zz_62_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_62__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_62__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_62__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_62__string = "EBREAK"; + default : _zz_62__string = "??????"; + endcase + end + always @(*) begin + case(_zz_64_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_64__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_64__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_64__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_64__string = "SRA_1 "; + default : _zz_64__string = "?????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_70_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_70__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_70__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_70__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_70__string = "JALR"; + default : _zz_70__string = "????"; + endcase + end + always @(*) begin + case(_zz_130_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_130__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_130__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_130__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_130__string = "SRA_1 "; + default : _zz_130__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_131_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_131__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_131__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_131__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_131__string = "EBREAK"; + default : _zz_131__string = "??????"; + endcase + end + always @(*) begin + case(_zz_132_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_132__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_132__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_132__string = "BITWISE "; + default : _zz_132__string = "????????"; + endcase + end + always @(*) begin + case(_zz_133_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_133__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_133__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_133__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_133__string = "PC "; + default : _zz_133__string = "???"; + endcase + end + always @(*) begin + case(_zz_134_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_134__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_134__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_134__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_134__string = "URS1 "; + default : _zz_134__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_135_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_135__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_135__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_135__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_135__string = "SRC1 "; + default : _zz_135__string = "?????"; + endcase + end + always @(*) begin + case(_zz_136_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_136__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_136__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_136__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_136__string = "JALR"; + default : _zz_136__string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_to_execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + `endif + + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_73_; + assign memory_PC = execute_to_memory_PC; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_35_; + assign _zz_1_ = _zz_2_; + assign _zz_3_ = _zz_4_; + assign decode_ENV_CTRL = _zz_5_; + assign _zz_6_ = _zz_7_; + assign decode_ALU_BITWISE_CTRL = _zz_8_; + assign _zz_9_ = _zz_10_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_68_; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_47_; + assign decode_SHIFT_CTRL = _zz_11_; + assign _zz_12_ = _zz_13_; + assign decode_DO_EBREAK = _zz_25_; + assign decode_ALU_CTRL = _zz_14_; + assign _zz_15_ = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_SRC1_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign decode_CSR_READ_OPCODE = _zz_28_; + assign decode_SRC_USE_SUB_LESS = _zz_63_; + assign decode_CSR_WRITE_OPCODE = _zz_29_; + assign execute_FLUSH_ALL = decode_to_execute_FLUSH_ALL; + assign decode_FLUSH_ALL = _zz_61_; + assign decode_SRC_LESS_UNSIGNED = _zz_65_; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign memory_MEMORY_READ_DATA = _zz_67_; + assign decode_IS_CSR = _zz_55_; + assign decode_MEMORY_ENABLE = _zz_58_; + assign decode_SRC2_CTRL = _zz_22_; + assign _zz_23_ = _zz_24_; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_57_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_26_; + assign execute_ENV_CTRL = _zz_27_; + assign writeBack_ENV_CTRL = _zz_30_; + assign execute_BRANCH_CALC = _zz_31_; + assign execute_BRANCH_DO = _zz_32_; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = _zz_51_; + assign execute_BRANCH_COND_RESULT = _zz_34_; + assign execute_BRANCH_CTRL = _zz_33_; + always @ (*) begin + _zz_36_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_194_)begin + _zz_36_ = _zz_145_; + if(_zz_195_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_36_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_SHIFT_CTRL = _zz_37_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41_ = execute_PC; + assign execute_SRC2_CTRL = _zz_42_; + assign execute_SRC1_CTRL = _zz_44_; + assign execute_SRC_ADD_SUB = _zz_40_; + assign execute_SRC_LESS = _zz_38_; + assign execute_ALU_CTRL = _zz_46_; + assign execute_SRC2 = _zz_43_; + assign execute_SRC1 = _zz_45_; + assign execute_ALU_BITWISE_CTRL = _zz_48_; + always @ (*) begin + _zz_49_ = 1'b0; + if(writeBack_RegFilePlugin_regFileWrite_valid)begin + _zz_49_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_54_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_66_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_66_ = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_RS2 = _zz_50_; + assign execute_SRC_ADD = _zz_39_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_ALIGNEMENT_FAULT = _zz_69_; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign memory_FLUSH_ALL = execute_to_memory_FLUSH_ALL; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(((_zz_188_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! 1'b0)))begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_redoFetch = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + assign decode_BRANCH_CTRL = _zz_70_; + always @ (*) begin + _zz_71_ = execute_FORMAL_PC_NEXT; + if(_zz_85_)begin + _zz_71_ = _zz_86_; + end + end + + always @ (*) begin + _zz_72_ = decode_FORMAL_PC_NEXT; + if(_zz_79_)begin + _zz_72_ = _zz_80_; + end + if(_zz_82_)begin + _zz_72_ = _zz_83_; + end + end + + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + assign decode_PC = _zz_75_; + always @ (*) begin + decode_INSTRUCTION = _zz_74_; + if((_zz_170_ != (3'b000)))begin + decode_INSTRUCTION = _zz_171_; + end + end + + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + _zz_95_ = 1'b0; + case(_zz_170_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + _zz_95_ = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((CsrPlugin_interrupt && decode_arbitration_isValid))begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))} != (2'b00)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_removeIt = 1'b0; + if(_zz_85_)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_exception_agregat_valid)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_redoIt = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + _zz_76_ = 1'b0; + _zz_77_ = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode}}} != (4'b0000)))begin + _zz_76_ = 1'b1; + end + if(_zz_196_)begin + execute_arbitration_haltByOther = 1'b1; + if(_zz_197_)begin + _zz_77_ = 1'b1; + _zz_76_ = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + _zz_76_ = 1'b1; + end + if(_zz_198_)begin + _zz_76_ = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(memory_exception_agregat_valid)begin + execute_arbitration_flushAll = 1'b1; + end + if(_zz_196_)begin + if(_zz_197_)begin + execute_arbitration_flushAll = 1'b1; + end + end + end + + assign execute_arbitration_redoIt = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + _zz_175_ = 1'b0; + if((memory_arbitration_isValid && memory_FLUSH_ALL))begin + _zz_175_ = 1'b1; + if((! IBusCachedPlugin_cache_io_flush_cmd_ready))begin + memory_arbitration_haltItself = 1'b1; + end + end + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin + memory_arbitration_haltItself = 1'b1; + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_exception_agregat_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushAll = 1'b0; + _zz_88_ = 1'b0; + _zz_89_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_199_)begin + _zz_88_ = 1'b1; + _zz_89_ = {CsrPlugin_mtvec_base,(2'b00)}; + memory_arbitration_flushAll = 1'b1; + end + if(_zz_200_)begin + _zz_89_ = CsrPlugin_mepc; + _zz_88_ = 1'b1; + memory_arbitration_flushAll = 1'b1; + end + end + + assign memory_arbitration_redoIt = 1'b0; + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushAll = 1'b0; + assign writeBack_arbitration_redoIt = 1'b0; + always @ (*) begin + _zz_78_ = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + _zz_78_ = 1'b1; + end + end + + always @ (*) begin + _zz_92_ = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + _zz_92_ = 1'b0; + end + end + + always @ (*) begin + _zz_93_ = 1'b1; + if(DebugPlugin_haltIt)begin + _zz_93_ = 1'b0; + end + end + + assign IBusCachedPlugin_jump_pcLoad_valid = ({_zz_88_,{_zz_85_,{_zz_82_,_zz_79_}}} != (4'b0000)); + assign _zz_96_ = {_zz_79_,{_zz_82_,{_zz_85_,_zz_88_}}}; + assign _zz_97_ = (_zz_96_ & (~ _zz_208_)); + assign _zz_98_ = _zz_97_[3]; + assign _zz_99_ = (_zz_97_[1] || _zz_98_); + assign _zz_100_ = (_zz_97_[2] || _zz_98_); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_193_; + assign _zz_101_ = (! _zz_76_); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_101_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_101_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid && IBusCachedPlugin_iBusRsp_stages_1_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_210_); + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + if(_zz_201_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_102_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_103_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_103_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_103_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(((IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid && (! 1'b1)) && (! 1'b0)))begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_104_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_104_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_104_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_105_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_105_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_105_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_106_; + assign _zz_106_ = ((1'b0 && (! _zz_107_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_107_ = _zz_108_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_107_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_109_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_109_ = _zz_110_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_109_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_111_; + assign IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign _zz_75_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_74_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_73_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_112_ = _zz_211_[11]; + always @ (*) begin + _zz_113_[18] = _zz_112_; + _zz_113_[17] = _zz_112_; + _zz_113_[16] = _zz_112_; + _zz_113_[15] = _zz_112_; + _zz_113_[14] = _zz_112_; + _zz_113_[13] = _zz_112_; + _zz_113_[12] = _zz_112_; + _zz_113_[11] = _zz_112_; + _zz_113_[10] = _zz_112_; + _zz_113_[9] = _zz_112_; + _zz_113_[8] = _zz_112_; + _zz_113_[7] = _zz_112_; + _zz_113_[6] = _zz_112_; + _zz_113_[5] = _zz_112_; + _zz_113_[4] = _zz_112_; + _zz_113_[3] = _zz_112_; + _zz_113_[2] = _zz_112_; + _zz_113_[1] = _zz_112_; + _zz_113_[0] = _zz_112_; + end + + assign _zz_81_ = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_212_[31])); + assign _zz_79_ = (_zz_81_ && decode_arbitration_isFiring); + assign _zz_114_ = _zz_213_[19]; + always @ (*) begin + _zz_115_[10] = _zz_114_; + _zz_115_[9] = _zz_114_; + _zz_115_[8] = _zz_114_; + _zz_115_[7] = _zz_114_; + _zz_115_[6] = _zz_114_; + _zz_115_[5] = _zz_114_; + _zz_115_[4] = _zz_114_; + _zz_115_[3] = _zz_114_; + _zz_115_[2] = _zz_114_; + _zz_115_[1] = _zz_114_; + _zz_115_[0] = _zz_114_; + end + + assign _zz_116_ = _zz_214_[11]; + always @ (*) begin + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + assign _zz_80_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_115_,{{{_zz_267_,_zz_268_},_zz_269_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_117_,{{{_zz_270_,_zz_271_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_176_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_179_ = (IBusCachedPlugin_jump_pcLoad_valid || _zz_77_); + assign _zz_180_ = (32'b00000000000000000000000000000000); + assign _zz_177_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_178_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_188_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_189_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_190_ = (CsrPlugin_privilege == (2'b00)); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign _zz_82_ = IBusCachedPlugin_rsp_redoFetch; + assign _zz_83_ = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign _zz_181_ = _zz_84_[31]; + assign _zz_182_ = 1'b1; + assign _zz_183_ = 1'b1; + assign _zz_184_ = 1'b1; + assign _zz_185_ = 1'b1; + assign _zz_186_ = 1'b0; + assign _zz_187_ = 1'b1; + assign execute_DBusSimplePlugin_cmdSent = 1'b0; + assign _zz_69_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_INSTRUCTION[5]; + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_118_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_118_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_118_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_118_; + assign _zz_68_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_119_ = (4'b0001); + end + 2'b01 : begin + _zz_119_ = (4'b0011); + end + default : begin + _zz_119_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_119_ <<< dBus_cmd_payload_address[1 : 0]); + assign _zz_67_ = dBus_rsp_data; + assign memory_exception_agregat_payload_code = {1'd0, _zz_215_}; + always @ (*) begin + memory_exception_agregat_valid = memory_ALIGNEMENT_FAULT; + if((! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && 1'b1)))begin + memory_exception_agregat_valid = 1'b0; + end + end + + assign memory_exception_agregat_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_120_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_121_[31] = _zz_120_; + _zz_121_[30] = _zz_120_; + _zz_121_[29] = _zz_120_; + _zz_121_[28] = _zz_120_; + _zz_121_[27] = _zz_120_; + _zz_121_[26] = _zz_120_; + _zz_121_[25] = _zz_120_; + _zz_121_[24] = _zz_120_; + _zz_121_[23] = _zz_120_; + _zz_121_[22] = _zz_120_; + _zz_121_[21] = _zz_120_; + _zz_121_[20] = _zz_120_; + _zz_121_[19] = _zz_120_; + _zz_121_[18] = _zz_120_; + _zz_121_[17] = _zz_120_; + _zz_121_[16] = _zz_120_; + _zz_121_[15] = _zz_120_; + _zz_121_[14] = _zz_120_; + _zz_121_[13] = _zz_120_; + _zz_121_[12] = _zz_120_; + _zz_121_[11] = _zz_120_; + _zz_121_[10] = _zz_120_; + _zz_121_[9] = _zz_120_; + _zz_121_[8] = _zz_120_; + _zz_121_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_122_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_123_[31] = _zz_122_; + _zz_123_[30] = _zz_122_; + _zz_123_[29] = _zz_122_; + _zz_123_[28] = _zz_122_; + _zz_123_[27] = _zz_122_; + _zz_123_[26] = _zz_122_; + _zz_123_[25] = _zz_122_; + _zz_123_[24] = _zz_122_; + _zz_123_[23] = _zz_122_; + _zz_123_[22] = _zz_122_; + _zz_123_[21] = _zz_122_; + _zz_123_[20] = _zz_122_; + _zz_123_[19] = _zz_122_; + _zz_123_[18] = _zz_122_; + _zz_123_[17] = _zz_122_; + _zz_123_[16] = _zz_122_; + _zz_123_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_205_) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_121_; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_123_; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_84_ = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign _zz_125_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_126_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_127_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_128_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_129_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_124_ = {(((decode_INSTRUCTION & _zz_272_) == (32'b00000000000000000000000000010000)) != (1'b0)),{({_zz_129_,_zz_273_} != (2'b00)),{(_zz_274_ != (1'b0)),{(_zz_275_ != _zz_276_),{_zz_277_,{_zz_278_,_zz_279_}}}}}}; + assign _zz_65_ = _zz_216_[0]; + assign _zz_130_ = _zz_124_[2 : 1]; + assign _zz_64_ = _zz_130_; + assign _zz_63_ = _zz_217_[0]; + assign _zz_131_ = _zz_124_[5 : 4]; + assign _zz_62_ = _zz_131_; + assign _zz_61_ = _zz_218_[0]; + assign _zz_132_ = _zz_124_[8 : 7]; + assign _zz_60_ = _zz_132_; + assign _zz_133_ = _zz_124_[10 : 9]; + assign _zz_59_ = _zz_133_; + assign _zz_58_ = _zz_219_[0]; + assign _zz_57_ = _zz_220_[0]; + assign _zz_134_ = _zz_124_[15 : 14]; + assign _zz_56_ = _zz_134_; + assign _zz_55_ = _zz_221_[0]; + assign _zz_54_ = _zz_222_[0]; + assign _zz_135_ = _zz_124_[22 : 21]; + assign _zz_53_ = _zz_135_; + assign _zz_136_ = _zz_124_[24 : 23]; + assign _zz_52_ = _zz_136_; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_137_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_191_; + assign execute_RegFilePlugin_rs2Data = _zz_192_; + assign _zz_51_ = execute_RegFilePlugin_rs1Data; + assign _zz_50_ = execute_RegFilePlugin_rs2Data; + assign writeBack_RegFilePlugin_regFileWrite_valid = (writeBack_REGFILE_WRITE_VALID && writeBack_arbitration_isFiring); + assign writeBack_RegFilePlugin_regFileWrite_payload_address = writeBack_INSTRUCTION[11 : 7]; + assign writeBack_RegFilePlugin_regFileWrite_payload_data = _zz_66_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = execute_SRC1; + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_138_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_138_ = {31'd0, _zz_223_}; + end + default : begin + _zz_138_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_47_ = _zz_138_; + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_139_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_139_ = {29'd0, _zz_224_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_139_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_139_ = {27'd0, _zz_225_}; + end + endcase + end + + assign _zz_45_ = _zz_139_; + assign _zz_140_ = _zz_226_[11]; + always @ (*) begin + _zz_141_[19] = _zz_140_; + _zz_141_[18] = _zz_140_; + _zz_141_[17] = _zz_140_; + _zz_141_[16] = _zz_140_; + _zz_141_[15] = _zz_140_; + _zz_141_[14] = _zz_140_; + _zz_141_[13] = _zz_140_; + _zz_141_[12] = _zz_140_; + _zz_141_[11] = _zz_140_; + _zz_141_[10] = _zz_140_; + _zz_141_[9] = _zz_140_; + _zz_141_[8] = _zz_140_; + _zz_141_[7] = _zz_140_; + _zz_141_[6] = _zz_140_; + _zz_141_[5] = _zz_140_; + _zz_141_[4] = _zz_140_; + _zz_141_[3] = _zz_140_; + _zz_141_[2] = _zz_140_; + _zz_141_[1] = _zz_140_; + _zz_141_[0] = _zz_140_; + end + + assign _zz_142_ = _zz_227_[11]; + always @ (*) begin + _zz_143_[19] = _zz_142_; + _zz_143_[18] = _zz_142_; + _zz_143_[17] = _zz_142_; + _zz_143_[16] = _zz_142_; + _zz_143_[15] = _zz_142_; + _zz_143_[14] = _zz_142_; + _zz_143_[13] = _zz_142_; + _zz_143_[12] = _zz_142_; + _zz_143_[11] = _zz_142_; + _zz_143_[10] = _zz_142_; + _zz_143_[9] = _zz_142_; + _zz_143_[8] = _zz_142_; + _zz_143_[7] = _zz_142_; + _zz_143_[6] = _zz_142_; + _zz_143_[5] = _zz_142_; + _zz_143_[4] = _zz_142_; + _zz_143_[3] = _zz_142_; + _zz_143_[2] = _zz_142_; + _zz_143_[1] = _zz_142_; + _zz_143_[0] = _zz_142_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_144_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_144_ = {_zz_141_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_144_ = {_zz_143_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_144_ = _zz_41_; + end + endcase + end + + assign _zz_43_ = _zz_144_; + assign execute_SrcPlugin_addSub = _zz_228_; + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_40_ = execute_SrcPlugin_addSub; + assign _zz_39_ = execute_SrcPlugin_addSub; + assign _zz_38_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_145_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_145_ = _zz_236_; + end + endcase + end + + assign _zz_35_ = _zz_81_; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_146_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_146_ == (3'b000))) begin + _zz_147_ = execute_BranchPlugin_eq; + end else if((_zz_146_ == (3'b001))) begin + _zz_147_ = (! execute_BranchPlugin_eq); + end else if((((_zz_146_ & (3'b101)) == (3'b101)))) begin + _zz_147_ = (! execute_SRC_LESS); + end else begin + _zz_147_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_148_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_148_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_148_ = 1'b1; + end + default : begin + _zz_148_ = _zz_147_; + end + endcase + end + + assign _zz_34_ = _zz_148_; + assign _zz_149_ = _zz_238_[11]; + always @ (*) begin + _zz_150_[19] = _zz_149_; + _zz_150_[18] = _zz_149_; + _zz_150_[17] = _zz_149_; + _zz_150_[16] = _zz_149_; + _zz_150_[15] = _zz_149_; + _zz_150_[14] = _zz_149_; + _zz_150_[13] = _zz_149_; + _zz_150_[12] = _zz_149_; + _zz_150_[11] = _zz_149_; + _zz_150_[10] = _zz_149_; + _zz_150_[9] = _zz_149_; + _zz_150_[8] = _zz_149_; + _zz_150_[7] = _zz_149_; + _zz_150_[6] = _zz_149_; + _zz_150_[5] = _zz_149_; + _zz_150_[4] = _zz_149_; + _zz_150_[3] = _zz_149_; + _zz_150_[2] = _zz_149_; + _zz_150_[1] = _zz_149_; + _zz_150_[0] = _zz_149_; + end + + assign _zz_151_ = _zz_239_[19]; + always @ (*) begin + _zz_152_[10] = _zz_151_; + _zz_152_[9] = _zz_151_; + _zz_152_[8] = _zz_151_; + _zz_152_[7] = _zz_151_; + _zz_152_[6] = _zz_151_; + _zz_152_[5] = _zz_151_; + _zz_152_[4] = _zz_151_; + _zz_152_[3] = _zz_151_; + _zz_152_[2] = _zz_151_; + _zz_152_[1] = _zz_151_; + _zz_152_[0] = _zz_151_; + end + + assign _zz_153_ = _zz_240_[11]; + always @ (*) begin + _zz_154_[18] = _zz_153_; + _zz_154_[17] = _zz_153_; + _zz_154_[16] = _zz_153_; + _zz_154_[15] = _zz_153_; + _zz_154_[14] = _zz_153_; + _zz_154_[13] = _zz_153_; + _zz_154_[12] = _zz_153_; + _zz_154_[11] = _zz_153_; + _zz_154_[10] = _zz_153_; + _zz_154_[9] = _zz_153_; + _zz_154_[8] = _zz_153_; + _zz_154_[7] = _zz_153_; + _zz_154_[6] = _zz_153_; + _zz_154_[5] = _zz_153_; + _zz_154_[4] = _zz_153_; + _zz_154_[3] = _zz_153_; + _zz_154_[2] = _zz_153_; + _zz_154_[1] = _zz_153_; + _zz_154_[0] = _zz_153_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_155_ = (_zz_241_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_155_ = _zz_242_[1]; + end + default : begin + _zz_155_ = _zz_243_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_155_); + assign _zz_32_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + execute_BranchPlugin_branch_src2 = {_zz_157_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_159_,{{{_zz_382_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_161_,{{{_zz_383_,_zz_384_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if((execute_PREDICTION_HAD_BRANCHED2 && (! execute_BranchPlugin_missAlignedTarget)))begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_247_}; + end + end + endcase + end + + assign _zz_156_ = _zz_244_[11]; + always @ (*) begin + _zz_157_[19] = _zz_156_; + _zz_157_[18] = _zz_156_; + _zz_157_[17] = _zz_156_; + _zz_157_[16] = _zz_156_; + _zz_157_[15] = _zz_156_; + _zz_157_[14] = _zz_156_; + _zz_157_[13] = _zz_156_; + _zz_157_[12] = _zz_156_; + _zz_157_[11] = _zz_156_; + _zz_157_[10] = _zz_156_; + _zz_157_[9] = _zz_156_; + _zz_157_[8] = _zz_156_; + _zz_157_[7] = _zz_156_; + _zz_157_[6] = _zz_156_; + _zz_157_[5] = _zz_156_; + _zz_157_[4] = _zz_156_; + _zz_157_[3] = _zz_156_; + _zz_157_[2] = _zz_156_; + _zz_157_[1] = _zz_156_; + _zz_157_[0] = _zz_156_; + end + + assign _zz_158_ = _zz_245_[19]; + always @ (*) begin + _zz_159_[10] = _zz_158_; + _zz_159_[9] = _zz_158_; + _zz_159_[8] = _zz_158_; + _zz_159_[7] = _zz_158_; + _zz_159_[6] = _zz_158_; + _zz_159_[5] = _zz_158_; + _zz_159_[4] = _zz_158_; + _zz_159_[3] = _zz_158_; + _zz_159_[2] = _zz_158_; + _zz_159_[1] = _zz_158_; + _zz_159_[0] = _zz_158_; + end + + assign _zz_160_ = _zz_246_[11]; + always @ (*) begin + _zz_161_[18] = _zz_160_; + _zz_161_[17] = _zz_160_; + _zz_161_[16] = _zz_160_; + _zz_161_[15] = _zz_160_; + _zz_161_[14] = _zz_160_; + _zz_161_[13] = _zz_160_; + _zz_161_[12] = _zz_160_; + _zz_161_[11] = _zz_160_; + _zz_161_[10] = _zz_160_; + _zz_161_[9] = _zz_160_; + _zz_161_[8] = _zz_160_; + _zz_161_[7] = _zz_160_; + _zz_161_[6] = _zz_160_; + _zz_161_[5] = _zz_160_; + _zz_161_[4] = _zz_160_; + _zz_161_[3] = _zz_160_; + _zz_161_[2] = _zz_160_; + _zz_161_[1] = _zz_160_; + _zz_161_[0] = _zz_160_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign _zz_85_ = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign _zz_86_ = execute_BRANCH_CALC; + always @ (*) begin + _zz_87_ = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + _zz_87_ = 1'b0; + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_medeleg = (32'b00000000000000000000000000000000); + assign CsrPlugin_mideleg = (32'b00000000000000000000000000000000); + assign _zz_162_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_163_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_164_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 1'b0; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = (2'b11); + assign execute_exception_agregat_valid = ({_zz_90_,_zz_87_} != (2'b00)); + assign _zz_165_ = {_zz_90_,_zz_87_}; + assign _zz_166_ = _zz_248_[0]; + assign execute_exception_agregat_payload_code = (_zz_166_ ? (4'b0000) : _zz_91_); + assign execute_exception_agregat_payload_badAddr = (_zz_166_ ? execute_BRANCH_CALC : (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)); + assign CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(memory_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + assign CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + if(CsrPlugin_mstatus_MIE)begin + if(({_zz_164_,{_zz_163_,_zz_162_}} != (3'b000)))begin + CsrPlugin_interrupt = 1'b1; + end + if(_zz_162_)begin + CsrPlugin_interruptCode = (4'b0111); + end + if(_zz_163_)begin + CsrPlugin_interruptCode = (4'b0011); + end + if(_zz_164_)begin + CsrPlugin_interruptCode = (4'b1011); + end + end + if((! _zz_92_))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_interruptTargetPrivilege = (2'b11); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && _zz_93_); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_injector_nextPcCalc_valids_4); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + assign contextSwitching = _zz_88_; + assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_167_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_168_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((execute_INSTRUCTION[29 : 28] != CsrPlugin_privilege))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + _zz_90_ = 1'b0; + _zz_91_ = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + _zz_90_ = 1'b1; + _zz_91_ = (4'b1011); + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + _zz_90_ = 1'b1; + _zz_91_ = (4'b0011); + end + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + case(_zz_207_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readData & (~ execute_SRC1)) : (execute_CsrPlugin_readData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_168_ = (_zz_167_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_168_ != (32'b00000000000000000000000000000000)); + assign DebugPlugin_isPipBusy = (DebugPlugin_isPipActive || DebugPlugin_isPipActive_regNext); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + _zz_94_ = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_202_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + _zz_94_ = 1'b1; + debug_bus_cmd_ready = _zz_95_; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + 6'b010011 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_169_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign _zz_25_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_254_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_255_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_256_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_257_))))); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_24_ = decode_SRC2_CTRL; + assign _zz_22_ = _zz_59_; + assign _zz_42_ = decode_to_execute_SRC2_CTRL; + assign _zz_21_ = decode_SRC1_CTRL; + assign _zz_19_ = _zz_56_; + assign _zz_44_ = decode_to_execute_SRC1_CTRL; + assign _zz_18_ = decode_BRANCH_CTRL; + assign _zz_70_ = _zz_52_; + assign _zz_33_ = decode_to_execute_BRANCH_CTRL; + assign _zz_16_ = decode_ALU_CTRL; + assign _zz_14_ = _zz_60_; + assign _zz_46_ = decode_to_execute_ALU_CTRL; + assign _zz_13_ = decode_SHIFT_CTRL; + assign _zz_11_ = _zz_64_; + assign _zz_37_ = decode_to_execute_SHIFT_CTRL; + assign _zz_10_ = decode_ALU_BITWISE_CTRL; + assign _zz_8_ = _zz_53_; + assign _zz_48_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_7_ = decode_ENV_CTRL; + assign _zz_4_ = execute_ENV_CTRL; + assign _zz_2_ = memory_ENV_CTRL; + assign _zz_5_ = _zz_62_; + assign _zz_27_ = decode_to_execute_ENV_CTRL; + assign _zz_26_ = execute_to_memory_ENV_CTRL; + assign _zz_30_ = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,{execute_arbitration_flushAll,decode_arbitration_flushAll}}} != (4'b0000)); + assign execute_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,execute_arbitration_flushAll}} != (3'b000)); + assign memory_arbitration_isFlushed = ({writeBack_arbitration_flushAll,memory_arbitration_flushAll} != (2'b00)); + assign writeBack_arbitration_isFlushed = (writeBack_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_264_,_zz_172_}; + assign iBusWishbone_CTI = ((_zz_172_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + iBusWishbone_STB = 1'b0; + if(_zz_203_)begin + iBusWishbone_CYC = 1'b1; + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_173_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_174_ = (4'b0001); + end + 2'b01 : begin + _zz_174_ = (4'b0011); + end + default : begin + _zz_174_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_265_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + CsrPlugin_privilege <= (2'b11); + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_102_ <= 1'b0; + _zz_108_ <= 1'b0; + _zz_110_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mip_MEIP <= 1'b0; + CsrPlugin_mip_MTIP <= 1'b0; + CsrPlugin_mip_MSIP <= 1'b0; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_167_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_170_ <= (3'b000); + _zz_172_ <= (3'b000); + _zz_173_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_201_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_102_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + _zz_108_ <= 1'b0; + end + if(_zz_106_)begin + _zz_108_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_110_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + _zz_110_ <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || _zz_77_))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if(_zz_194_)begin + if(_zz_195_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_199_)begin + CsrPlugin_privilege <= CsrPlugin_targetPrivilege; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_200_)begin + case(_zz_206_) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPIE <= 1'b1; + CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; + end + default : begin + end + endcase + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_170_) + 3'b000 : begin + if(_zz_94_)begin + _zz_170_ <= (3'b001); + end + end + 3'b001 : begin + _zz_170_ <= (3'b010); + end + 3'b010 : begin + _zz_170_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_170_ <= (3'b100); + end + end + 3'b100 : begin + _zz_170_ <= (3'b000); + end + default : begin + end + endcase + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_167_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_258_[0]; + CsrPlugin_mstatus_MIE <= _zz_259_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_260_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_261_[0]; + CsrPlugin_mie_MTIE <= _zz_262_[0]; + CsrPlugin_mie_MSIE <= _zz_263_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_203_)begin + if(iBusWishbone_ACK)begin + _zz_172_ <= (_zz_172_ + (3'b001)); + end + end + _zz_173_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_204_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_111_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); + end + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + end + if(_zz_194_)begin + if(_zz_195_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(execute_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= execute_exception_agregat_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= execute_exception_agregat_payload_badAddr; + end + if(memory_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= memory_exception_agregat_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= memory_exception_agregat_payload_badAddr; + end + if((CsrPlugin_exception || CsrPlugin_interruptJump))begin + case(CsrPlugin_privilege) + 2'b11 : begin + CsrPlugin_mepc <= writeBack_PC; + end + default : begin + end + endcase + end + if(_zz_199_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_23_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FLUSH_ALL <= decode_FLUSH_ALL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FLUSH_ALL <= execute_FLUSH_ALL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_20_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_15_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_12_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_9_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_72_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_71_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_204_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipActive <= ({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)); + DebugPlugin_isPipActive_regNext <= DebugPlugin_isPipActive; + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_66_; + end + _zz_169_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_202_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_196_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; + end else begin + if(debug_bus_cmd_valid)begin + case(_zz_202_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_250_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_251_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_252_[0]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_valid <= _zz_253_[0]; + end + end + default : begin + end + endcase + end + if(_zz_196_)begin + if(_zz_197_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_198_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + if((DebugPlugin_stepIt && ({writeBack_arbitration_redoIt,{memory_arbitration_redoIt,{execute_arbitration_redoIt,decode_arbitration_redoIt}}} != (4'b0000))))begin + DebugPlugin_haltIt <= 1'b0; + end + end + end + + always @ (posedge clk) begin + _zz_171_ <= debug_bus_cmd_payload_data; + end + +endmodule + diff --git a/hw/4-stage-no-cache-debug.yaml b/hw/4-stage-no-cache-debug.yaml new file mode 100644 index 0000000..156f2e4 --- /dev/null +++ b/hw/4-stage-no-cache-debug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} +iBus: !!vexriscv.BusReport + flushInstructions: [16399, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} + kind: cached diff --git a/hw/5-stage-pipelined-no-cache-debug.v b/hw/5-stage-pipelined-no-cache-debug.v new file mode 100644 index 0000000..f3736e8 --- /dev/null +++ b/hw/5-stage-pipelined-no-cache-debug.v @@ -0,0 +1,3902 @@ +// Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26 +// Date : 26/03/2019, 04:50:46 +// Component : VexRiscv + + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset); + wire [0:0] _zz_5_; + reg _zz_1_; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2_; + wire [32:0] _zz_3_; + reg [32:0] _zz_4_; + assign _zz_5_ = _zz_2_[0 : 0]; + always @ (*) begin + _zz_1_ = 1'b0; + pushPtr_willIncrement = 1'b0; + if(pushing)begin + _zz_1_ = 1'b1; + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + popPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + popPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if((! empty))begin + io_pop_valid = 1'b1; + io_pop_payload_error = _zz_5_[0]; + io_pop_payload_inst = _zz_2_[32 : 1]; + end else begin + io_pop_valid = io_push_valid; + io_pop_payload_error = io_push_payload_error; + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign _zz_2_ = _zz_3_; + assign io_occupancy = (risingOccupancy && ptrMatch); + assign _zz_3_ = _zz_4_; + always @ (posedge clk) begin + if(reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1_)begin + _zz_4_ <= {io_push_payload_inst,io_push_payload_error}; + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset, + input debugReset); + wire _zz_178_; + reg [31:0] _zz_179_; + reg [31:0] _zz_180_; + reg [31:0] _zz_181_; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_182_; + wire _zz_183_; + wire _zz_184_; + wire _zz_185_; + wire _zz_186_; + wire _zz_187_; + wire _zz_188_; + wire _zz_189_; + wire [5:0] _zz_190_; + wire _zz_191_; + wire [1:0] _zz_192_; + wire [1:0] _zz_193_; + wire _zz_194_; + wire [2:0] _zz_195_; + wire [2:0] _zz_196_; + wire [31:0] _zz_197_; + wire [11:0] _zz_198_; + wire [31:0] _zz_199_; + wire [19:0] _zz_200_; + wire [11:0] _zz_201_; + wire [1:0] _zz_202_; + wire [0:0] _zz_203_; + wire [1:0] _zz_204_; + wire [0:0] _zz_205_; + wire [1:0] _zz_206_; + wire [0:0] _zz_207_; + wire [1:0] _zz_208_; + wire [0:0] _zz_209_; + wire [1:0] _zz_210_; + wire [2:0] _zz_211_; + wire [0:0] _zz_212_; + wire [0:0] _zz_213_; + wire [0:0] _zz_214_; + wire [0:0] _zz_215_; + wire [0:0] _zz_216_; + wire [0:0] _zz_217_; + wire [0:0] _zz_218_; + wire [0:0] _zz_219_; + wire [0:0] _zz_220_; + wire [0:0] _zz_221_; + wire [0:0] _zz_222_; + wire [2:0] _zz_223_; + wire [4:0] _zz_224_; + wire [11:0] _zz_225_; + wire [11:0] _zz_226_; + wire [31:0] _zz_227_; + wire [31:0] _zz_228_; + wire [31:0] _zz_229_; + wire [31:0] _zz_230_; + wire [1:0] _zz_231_; + wire [31:0] _zz_232_; + wire [1:0] _zz_233_; + wire [1:0] _zz_234_; + wire [31:0] _zz_235_; + wire [32:0] _zz_236_; + wire [11:0] _zz_237_; + wire [19:0] _zz_238_; + wire [11:0] _zz_239_; + wire [31:0] _zz_240_; + wire [31:0] _zz_241_; + wire [31:0] _zz_242_; + wire [11:0] _zz_243_; + wire [19:0] _zz_244_; + wire [11:0] _zz_245_; + wire [2:0] _zz_246_; + wire [1:0] _zz_247_; + wire [1:0] _zz_248_; + wire [0:0] _zz_249_; + wire [0:0] _zz_250_; + wire [0:0] _zz_251_; + wire [0:0] _zz_252_; + wire [30:0] _zz_253_; + wire [30:0] _zz_254_; + wire [30:0] _zz_255_; + wire [30:0] _zz_256_; + wire [0:0] _zz_257_; + wire [0:0] _zz_258_; + wire [0:0] _zz_259_; + wire [0:0] _zz_260_; + wire [0:0] _zz_261_; + wire [0:0] _zz_262_; + wire [6:0] _zz_263_; + wire _zz_264_; + wire _zz_265_; + wire [1:0] _zz_266_; + wire [0:0] _zz_267_; + wire [7:0] _zz_268_; + wire _zz_269_; + wire [0:0] _zz_270_; + wire [0:0] _zz_271_; + wire [31:0] _zz_272_; + wire [31:0] _zz_273_; + wire [31:0] _zz_274_; + wire [31:0] _zz_275_; + wire _zz_276_; + wire [0:0] _zz_277_; + wire [0:0] _zz_278_; + wire _zz_279_; + wire [2:0] _zz_280_; + wire [2:0] _zz_281_; + wire _zz_282_; + wire [0:0] _zz_283_; + wire [19:0] _zz_284_; + wire [31:0] _zz_285_; + wire [31:0] _zz_286_; + wire [31:0] _zz_287_; + wire [31:0] _zz_288_; + wire _zz_289_; + wire _zz_290_; + wire _zz_291_; + wire [0:0] _zz_292_; + wire [3:0] _zz_293_; + wire _zz_294_; + wire [0:0] _zz_295_; + wire [0:0] _zz_296_; + wire _zz_297_; + wire [0:0] _zz_298_; + wire [16:0] _zz_299_; + wire [31:0] _zz_300_; + wire [31:0] _zz_301_; + wire [31:0] _zz_302_; + wire [31:0] _zz_303_; + wire [31:0] _zz_304_; + wire _zz_305_; + wire [0:0] _zz_306_; + wire [1:0] _zz_307_; + wire [31:0] _zz_308_; + wire [31:0] _zz_309_; + wire [31:0] _zz_310_; + wire [0:0] _zz_311_; + wire [0:0] _zz_312_; + wire [0:0] _zz_313_; + wire [0:0] _zz_314_; + wire _zz_315_; + wire [0:0] _zz_316_; + wire [14:0] _zz_317_; + wire [31:0] _zz_318_; + wire [31:0] _zz_319_; + wire [31:0] _zz_320_; + wire [31:0] _zz_321_; + wire [31:0] _zz_322_; + wire [31:0] _zz_323_; + wire [31:0] _zz_324_; + wire [0:0] _zz_325_; + wire [0:0] _zz_326_; + wire [1:0] _zz_327_; + wire [1:0] _zz_328_; + wire _zz_329_; + wire [0:0] _zz_330_; + wire [11:0] _zz_331_; + wire [31:0] _zz_332_; + wire [31:0] _zz_333_; + wire [31:0] _zz_334_; + wire [31:0] _zz_335_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [0:0] _zz_338_; + wire _zz_339_; + wire [0:0] _zz_340_; + wire [8:0] _zz_341_; + wire [31:0] _zz_342_; + wire [31:0] _zz_343_; + wire _zz_344_; + wire [0:0] _zz_345_; + wire [0:0] _zz_346_; + wire _zz_347_; + wire [0:0] _zz_348_; + wire [0:0] _zz_349_; + wire [0:0] _zz_350_; + wire [0:0] _zz_351_; + wire [2:0] _zz_352_; + wire [2:0] _zz_353_; + wire _zz_354_; + wire [0:0] _zz_355_; + wire [4:0] _zz_356_; + wire [31:0] _zz_357_; + wire [31:0] _zz_358_; + wire [31:0] _zz_359_; + wire [31:0] _zz_360_; + wire [31:0] _zz_361_; + wire [31:0] _zz_362_; + wire [31:0] _zz_363_; + wire [31:0] _zz_364_; + wire [31:0] _zz_365_; + wire [31:0] _zz_366_; + wire [31:0] _zz_367_; + wire [31:0] _zz_368_; + wire [0:0] _zz_369_; + wire [0:0] _zz_370_; + wire [0:0] _zz_371_; + wire [0:0] _zz_372_; + wire [0:0] _zz_373_; + wire [0:0] _zz_374_; + wire _zz_375_; + wire [0:0] _zz_376_; + wire [2:0] _zz_377_; + wire [31:0] _zz_378_; + wire [31:0] _zz_379_; + wire [31:0] _zz_380_; + wire [31:0] _zz_381_; + wire [31:0] _zz_382_; + wire _zz_383_; + wire [1:0] _zz_384_; + wire [1:0] _zz_385_; + wire _zz_386_; + wire _zz_387_; + wire _zz_388_; + wire _zz_389_; + wire _zz_390_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_1_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_2_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_3_; + wire decode_SRC_LESS_UNSIGNED; + wire decode_SRC_USE_SUB_LESS; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire [31:0] memory_PC; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_7_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_9_; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_CSR_WRITE_OPCODE; + wire decode_CSR_READ_OPCODE; + wire decode_DO_EBREAK; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_11_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_12_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_14_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_15_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16_; + wire decode_RS2_USE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_MEMORY_ENABLE; + wire decode_RS1_USE; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_17_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_18_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_19_; + wire execute_REGFILE_WRITE_VALID; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluCtrlEnum_defaultEncoding_type _zz_21_; + wire `AluCtrlEnum_defaultEncoding_type _zz_22_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_23_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_24_; + wire decode_IS_CSR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire _zz_25_; + wire execute_RS2_USE; + wire execute_RS1_USE; + wire memory_REGFILE_WRITE_VALID; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; + wire _zz_28_; + wire _zz_29_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; + wire execute_IS_FENCEI; + reg [31:0] _zz_31_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_32_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_33_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_34_; + wire _zz_35_; + wire decode_IS_FENCEI; + wire _zz_36_; + reg [31:0] _zz_37_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_38_; + wire _zz_39_; + wire [31:0] _zz_40_; + wire [31:0] _zz_41_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_42_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_43_; + wire [31:0] _zz_44_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_45_; + wire [31:0] _zz_46_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_47_; + wire [31:0] _zz_48_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_49_; + wire [31:0] _zz_50_; + wire _zz_51_; + reg _zz_52_; + wire [31:0] _zz_53_; + wire [31:0] _zz_54_; + reg decode_REGFILE_WRITE_VALID; + wire _zz_55_; + wire `AluCtrlEnum_defaultEncoding_type _zz_56_; + wire _zz_57_; + wire _zz_58_; + wire _zz_59_; + wire _zz_60_; + wire _zz_61_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_62_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_63_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_64_; + wire _zz_65_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_66_; + wire _zz_67_; + wire _zz_68_; + wire _zz_69_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_70_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_71_; + reg [31:0] _zz_72_; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_INSTRUCTION; + wire memory_MEMORY_ENABLE; + wire [31:0] _zz_73_; + wire [1:0] _zz_74_; + wire [31:0] execute_RS2; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_INSTRUCTION; + wire execute_ALIGNEMENT_FAULT; + wire execute_MEMORY_ENABLE; + wire _zz_75_; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_76_; + reg [31:0] _zz_77_; + reg [31:0] _zz_78_; + wire [31:0] _zz_79_; + wire [31:0] _zz_80_; + wire [31:0] _zz_81_; + wire [31:0] writeBack_PC /* verilator public */ ; + wire [31:0] writeBack_INSTRUCTION /* verilator public */ ; + wire [31:0] decode_PC /* verilator public */ ; + reg [31:0] decode_INSTRUCTION /* verilator public */ ; + reg decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + wire decode_arbitration_redoIt; + reg decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + wire execute_arbitration_redoIt; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushAll; + wire memory_arbitration_redoIt; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushAll; + wire writeBack_arbitration_redoIt; + reg writeBack_arbitration_isValid /* verilator public */ ; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring /* verilator public */ ; + reg _zz_82_; + reg _zz_83_; + reg _zz_84_; + wire _zz_85_; + wire [31:0] _zz_86_; + wire _zz_87_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + wire [31:0] iBus_cmd_payload_pc; + wire iBus_rsp_valid; + wire iBus_rsp_payload_error; + wire [31:0] iBus_rsp_payload_inst; + reg memory_exception_agregat_valid; + wire [3:0] memory_exception_agregat_payload_code; + wire [31:0] memory_exception_agregat_payload_badAddr; + wire _zz_88_; + wire [31:0] _zz_89_; + reg _zz_90_; + reg _zz_91_; + reg [31:0] _zz_92_; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg _zz_93_; + reg [3:0] _zz_94_; + reg _zz_95_; + reg _zz_96_; + reg _zz_97_; + reg _zz_98_; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [2:0] _zz_99_; + wire [2:0] _zz_100_; + wire _zz_101_; + wire _zz_102_; + wire IBusSimplePlugin_fetchPc_preOutput_valid; + wire IBusSimplePlugin_fetchPc_preOutput_ready; + wire [31:0] IBusSimplePlugin_fetchPc_preOutput_payload; + wire _zz_103_; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_inc; + reg IBusSimplePlugin_fetchPc_propagatePc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + reg IBusSimplePlugin_fetchPc_samplePcNext; + reg _zz_104_; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_0_inputSample; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_inputSample; + wire _zz_105_; + wire _zz_106_; + wire _zz_107_; + wire _zz_108_; + reg _zz_109_; + wire IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_decodeInput_valid; + wire IBusSimplePlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_decodeInput_payload_pc; + wire IBusSimplePlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_decodeRemoved; + wire _zz_110_; + reg [18:0] _zz_111_; + wire _zz_112_; + reg [10:0] _zz_113_; + wire _zz_114_; + reg [18:0] _zz_115_; + wire IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + reg [1:0] IBusSimplePlugin_pendingCmd; + wire [1:0] IBusSimplePlugin_pendingCmdNext; + reg [1:0] IBusSimplePlugin_rspJoin_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid; + wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready; + wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; + wire iBus_rsp_takeWhen_valid; + wire iBus_rsp_takeWhen_payload_error; + wire [31:0] iBus_rsp_takeWhen_payload_inst; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_issueDetected; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + wire _zz_116_; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire execute_DBusSimplePlugin_cmdSent; + reg [31:0] _zz_117_; + reg [3:0] _zz_118_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_119_; + reg [31:0] _zz_120_; + wire _zz_121_; + reg [31:0] _zz_122_; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [25:0] _zz_123_; + wire _zz_124_; + wire _zz_125_; + wire _zz_126_; + wire _zz_127_; + wire _zz_128_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_129_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_130_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_131_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_132_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_133_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_134_; + wire `AluCtrlEnum_defaultEncoding_type _zz_135_; + wire [31:0] execute_RegFilePlugin_srcInstruction; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire writeBack_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] writeBack_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] writeBack_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_136_; + reg [31:0] _zz_137_; + wire _zz_138_; + reg [19:0] _zz_139_; + wire _zz_140_; + reg [19:0] _zz_141_; + reg [31:0] _zz_142_; + wire [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_143_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_144_; + reg _zz_145_; + reg _zz_146_; + wire _zz_147_; + reg [19:0] _zz_148_; + wire _zz_149_; + reg [10:0] _zz_150_; + wire _zz_151_; + reg [18:0] _zz_152_; + reg _zz_153_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_154_; + reg [19:0] _zz_155_; + wire _zz_156_; + reg [10:0] _zz_157_; + wire _zz_158_; + reg [18:0] _zz_159_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire [31:0] CsrPlugin_medeleg; + wire [31:0] CsrPlugin_mideleg; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + wire CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + wire CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire execute_exception_agregat_valid; + wire [3:0] execute_exception_agregat_payload_code; + wire [31:0] execute_exception_agregat_payload_badAddr; + wire [1:0] _zz_163_; + wire _zz_164_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + wire [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg _zz_165_; + reg _zz_166_; + wire _zz_167_; + reg _zz_168_; + reg [4:0] _zz_169_; + reg [31:0] _zz_170_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_171_; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipActive; + reg DebugPlugin_isPipActive_regNext; + wire DebugPlugin_isPipBusy; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_hardwareBreakpoints_0_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_0_pc; + reg DebugPlugin_hardwareBreakpoints_1_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_1_pc; + reg DebugPlugin_hardwareBreakpoints_2_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_2_pc; + reg DebugPlugin_hardwareBreakpoints_3_valid; + reg [30:0] DebugPlugin_hardwareBreakpoints_3_pc; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_172_; + reg DebugPlugin_resetIt_regNext; + reg decode_to_execute_IS_FENCEI; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg decode_to_execute_IS_CSR; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg decode_to_execute_RS1_USE; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg decode_to_execute_RS2_USE; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_DO_EBREAK; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg [2:0] _zz_173_; + reg [31:0] _zz_174_; + wire iBus_cmd_m2sPipe_valid; + wire iBus_cmd_m2sPipe_ready; + wire [31:0] iBus_cmd_m2sPipe_payload_pc; + reg _zz_175_; + reg [31:0] _zz_176_; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_177_; + `ifndef SYNTHESIS + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_1__string; + reg [71:0] _zz_2__string; + reg [71:0] _zz_3__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_4__string; + reg [23:0] _zz_5__string; + reg [23:0] _zz_6__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_7__string; + reg [39:0] _zz_8__string; + reg [39:0] _zz_9__string; + reg [47:0] _zz_10__string; + reg [47:0] _zz_11__string; + reg [47:0] _zz_12__string; + reg [47:0] _zz_13__string; + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_14__string; + reg [47:0] _zz_15__string; + reg [47:0] _zz_16__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_17__string; + reg [95:0] _zz_18__string; + reg [95:0] _zz_19__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_20__string; + reg [63:0] _zz_21__string; + reg [63:0] _zz_22__string; + reg [31:0] _zz_23__string; + reg [31:0] _zz_24__string; + reg [47:0] memory_ENV_CTRL_string; + reg [47:0] _zz_26__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_27__string; + reg [47:0] writeBack_ENV_CTRL_string; + reg [47:0] _zz_30__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_34__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_38__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_43__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_45__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_47__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_49__string; + reg [63:0] _zz_56__string; + reg [71:0] _zz_62__string; + reg [23:0] _zz_63__string; + reg [31:0] _zz_64__string; + reg [39:0] _zz_66__string; + reg [47:0] _zz_70__string; + reg [95:0] _zz_71__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_76__string; + reg [95:0] _zz_129__string; + reg [47:0] _zz_130__string; + reg [39:0] _zz_131__string; + reg [31:0] _zz_132__string; + reg [23:0] _zz_133__string; + reg [71:0] _zz_134__string; + reg [63:0] _zz_135__string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + reg [47:0] execute_to_memory_ENV_CTRL_string; + reg [47:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_182_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_183_ = (! execute_arbitration_isStuckByOthers); + assign _zz_184_ = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_185_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); + assign _zz_186_ = (DebugPlugin_stepIt && _zz_84_); + assign _zz_187_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_188_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_189_ = (IBusSimplePlugin_fetchPc_preOutput_valid && IBusSimplePlugin_fetchPc_preOutput_ready); + assign _zz_190_ = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_191_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_192_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_193_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_194_ = execute_INSTRUCTION[13]; + assign _zz_195_ = (_zz_99_ - (3'b001)); + assign _zz_196_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; + assign _zz_197_ = {29'd0, _zz_196_}; + assign _zz_198_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_199_ = {{_zz_111_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_200_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_201_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_202_ = (IBusSimplePlugin_pendingCmd + _zz_204_); + assign _zz_203_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign _zz_204_ = {1'd0, _zz_203_}; + assign _zz_205_ = iBus_rsp_valid; + assign _zz_206_ = {1'd0, _zz_205_}; + assign _zz_207_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (2'b00))); + assign _zz_208_ = {1'd0, _zz_207_}; + assign _zz_209_ = iBus_rsp_valid; + assign _zz_210_ = {1'd0, _zz_209_}; + assign _zz_211_ = (memory_INSTRUCTION[5] ? (3'b110) : (3'b100)); + assign _zz_212_ = _zz_123_[4 : 4]; + assign _zz_213_ = _zz_123_[5 : 5]; + assign _zz_214_ = _zz_123_[6 : 6]; + assign _zz_215_ = _zz_123_[10 : 10]; + assign _zz_216_ = _zz_123_[18 : 18]; + assign _zz_217_ = _zz_123_[19 : 19]; + assign _zz_218_ = _zz_123_[20 : 20]; + assign _zz_219_ = _zz_123_[21 : 21]; + assign _zz_220_ = _zz_123_[22 : 22]; + assign _zz_221_ = _zz_123_[25 : 25]; + assign _zz_222_ = execute_SRC_LESS; + assign _zz_223_ = (3'b100); + assign _zz_224_ = execute_INSTRUCTION[19 : 15]; + assign _zz_225_ = execute_INSTRUCTION[31 : 20]; + assign _zz_226_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_227_ = ($signed(_zz_228_) + $signed(_zz_232_)); + assign _zz_228_ = ($signed(_zz_229_) + $signed(_zz_230_)); + assign _zz_229_ = execute_SRC1; + assign _zz_230_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_231_ = (execute_SRC_USE_SUB_LESS ? _zz_233_ : _zz_234_); + assign _zz_232_ = {{30{_zz_231_[1]}}, _zz_231_}; + assign _zz_233_ = (2'b01); + assign _zz_234_ = (2'b00); + assign _zz_235_ = (_zz_236_ >>> 1); + assign _zz_236_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_237_ = execute_INSTRUCTION[31 : 20]; + assign _zz_238_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_239_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_240_ = {_zz_148_,execute_INSTRUCTION[31 : 20]}; + assign _zz_241_ = {{_zz_150_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_242_ = {{_zz_152_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_243_ = execute_INSTRUCTION[31 : 20]; + assign _zz_244_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_245_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_246_ = (3'b100); + assign _zz_247_ = (_zz_163_ & (~ _zz_248_)); + assign _zz_248_ = (_zz_163_ - (2'b01)); + assign _zz_249_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_250_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_251_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_252_ = debug_bus_cmd_payload_data[0 : 0]; + assign _zz_253_ = (decode_PC >>> 1); + assign _zz_254_ = (decode_PC >>> 1); + assign _zz_255_ = (decode_PC >>> 1); + assign _zz_256_ = (decode_PC >>> 1); + assign _zz_257_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_258_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_259_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_260_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_261_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_262_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_263_ = ({3'd0,_zz_177_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_264_ = 1'b1; + assign _zz_265_ = 1'b1; + assign _zz_266_ = {_zz_102_,_zz_101_}; + assign _zz_267_ = decode_INSTRUCTION[31]; + assign _zz_268_ = decode_INSTRUCTION[19 : 12]; + assign _zz_269_ = decode_INSTRUCTION[20]; + assign _zz_270_ = decode_INSTRUCTION[31]; + assign _zz_271_ = decode_INSTRUCTION[7]; + assign _zz_272_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); + assign _zz_273_ = (32'b00000000000000000001000001010000); + assign _zz_274_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); + assign _zz_275_ = (32'b00000000000000000010000001010000); + assign _zz_276_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); + assign _zz_277_ = ((decode_INSTRUCTION & _zz_285_) == (32'b00000000000000000100000000010000)); + assign _zz_278_ = ((decode_INSTRUCTION & _zz_286_) == (32'b00000000000000000001000000010000)); + assign _zz_279_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); + assign _zz_280_ = {(_zz_287_ == _zz_288_),{_zz_289_,_zz_290_}}; + assign _zz_281_ = (3'b000); + assign _zz_282_ = ({_zz_291_,{_zz_292_,_zz_293_}} != (6'b000000)); + assign _zz_283_ = (_zz_294_ != (1'b0)); + assign _zz_284_ = {(_zz_295_ != _zz_296_),{_zz_297_,{_zz_298_,_zz_299_}}}; + assign _zz_285_ = (32'b00000000000000000100000000010100); + assign _zz_286_ = (32'b00000000000000000011000000010100); + assign _zz_287_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_288_ = (32'b00000000000000000000000001000000); + assign _zz_289_ = ((decode_INSTRUCTION & _zz_300_) == (32'b01000000000000000000000000110000)); + assign _zz_290_ = ((decode_INSTRUCTION & _zz_301_) == (32'b00000000000000000010000000010000)); + assign _zz_291_ = ((decode_INSTRUCTION & _zz_302_) == (32'b00000000000000000000000001001000)); + assign _zz_292_ = (_zz_303_ == _zz_304_); + assign _zz_293_ = {_zz_305_,{_zz_306_,_zz_307_}}; + assign _zz_294_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000000000000001000)); + assign _zz_295_ = (_zz_309_ == _zz_310_); + assign _zz_296_ = (1'b0); + assign _zz_297_ = ({_zz_311_,_zz_312_} != (2'b00)); + assign _zz_298_ = (_zz_313_ != _zz_314_); + assign _zz_299_ = {_zz_315_,{_zz_316_,_zz_317_}}; + assign _zz_300_ = (32'b01000000000000000000000000110000); + assign _zz_301_ = (32'b00000000000000000010000000010100); + assign _zz_302_ = (32'b00000000000000000000000001001000); + assign _zz_303_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_304_ = (32'b00000000000000000001000000010000); + assign _zz_305_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); + assign _zz_306_ = ((decode_INSTRUCTION & _zz_318_) == (32'b00000000000000000000000000000100)); + assign _zz_307_ = {_zz_128_,(_zz_319_ == _zz_320_)}; + assign _zz_308_ = (32'b00000000000000000000000001001000); + assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_310_ = (32'b00000000000000000000000000000000); + assign _zz_311_ = ((decode_INSTRUCTION & _zz_321_) == (32'b00000000000000000000000000100000)); + assign _zz_312_ = ((decode_INSTRUCTION & _zz_322_) == (32'b00000000000000000000000000100000)); + assign _zz_313_ = _zz_128_; + assign _zz_314_ = (1'b0); + assign _zz_315_ = ((_zz_323_ == _zz_324_) != (1'b0)); + assign _zz_316_ = ({_zz_325_,_zz_326_} != (2'b00)); + assign _zz_317_ = {(_zz_327_ != _zz_328_),{_zz_329_,{_zz_330_,_zz_331_}}}; + assign _zz_318_ = (32'b00000000000000000001000000000100); + assign _zz_319_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_320_ = (32'b00000000000000000000000000000000); + assign _zz_321_ = (32'b00000000000000000000000000110100); + assign _zz_322_ = (32'b00000000000000000000000001100100); + assign _zz_323_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); + assign _zz_324_ = (32'b00000000000000000101000000010000); + assign _zz_325_ = ((decode_INSTRUCTION & _zz_332_) == (32'b01000000000000000001000000010000)); + assign _zz_326_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000001000000010000)); + assign _zz_327_ = {_zz_127_,(_zz_334_ == _zz_335_)}; + assign _zz_328_ = (2'b00); + assign _zz_329_ = ({_zz_127_,_zz_336_} != (2'b00)); + assign _zz_330_ = (_zz_125_ != (1'b0)); + assign _zz_331_ = {(_zz_337_ != _zz_338_),{_zz_339_,{_zz_340_,_zz_341_}}}; + assign _zz_332_ = (32'b01000000000000000011000001010100); + assign _zz_333_ = (32'b00000000000000000111000001010100); + assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); + assign _zz_335_ = (32'b00000000000000000000000000100000); + assign _zz_336_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign _zz_337_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); + assign _zz_338_ = (1'b0); + assign _zz_339_ = ({(_zz_342_ == _zz_343_),{_zz_344_,{_zz_345_,_zz_346_}}} != (4'b0000)); + assign _zz_340_ = ({_zz_347_,{_zz_348_,_zz_349_}} != (3'b000)); + assign _zz_341_ = {({_zz_350_,_zz_351_} != (2'b00)),{(_zz_352_ != _zz_353_),{_zz_354_,{_zz_355_,_zz_356_}}}}; + assign _zz_342_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_343_ = (32'b00000000000000000000000000000000); + assign _zz_344_ = ((decode_INSTRUCTION & _zz_357_) == (32'b00000000000000000000000000000000)); + assign _zz_345_ = (_zz_358_ == _zz_359_); + assign _zz_346_ = (_zz_360_ == _zz_361_); + assign _zz_347_ = ((decode_INSTRUCTION & _zz_362_) == (32'b00000000000000000000000001000000)); + assign _zz_348_ = (_zz_363_ == _zz_364_); + assign _zz_349_ = (_zz_365_ == _zz_366_); + assign _zz_350_ = (_zz_367_ == _zz_368_); + assign _zz_351_ = _zz_127_; + assign _zz_352_ = {_zz_127_,{_zz_369_,_zz_370_}}; + assign _zz_353_ = (3'b000); + assign _zz_354_ = ({_zz_371_,_zz_372_} != (2'b00)); + assign _zz_355_ = (_zz_373_ != _zz_374_); + assign _zz_356_ = {_zz_375_,{_zz_376_,_zz_377_}}; + assign _zz_357_ = (32'b00000000000000000000000000011000); + assign _zz_358_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); + assign _zz_359_ = (32'b00000000000000000010000000000000); + assign _zz_360_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_361_ = (32'b00000000000000000001000000000000); + assign _zz_362_ = (32'b00000000000000000000000001010000); + assign _zz_363_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110000)); + assign _zz_364_ = (32'b00000000000000000000000000000000); + assign _zz_365_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000)); + assign _zz_366_ = (32'b00000000000000000000000001000000); + assign _zz_367_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); + assign _zz_368_ = (32'b00000000000000000001000000000000); + assign _zz_369_ = ((decode_INSTRUCTION & _zz_378_) == (32'b00000000000000000001000000000000)); + assign _zz_370_ = ((decode_INSTRUCTION & _zz_379_) == (32'b00000000000000000010000000000000)); + assign _zz_371_ = ((decode_INSTRUCTION & _zz_380_) == (32'b00000000000000000010000000000000)); + assign _zz_372_ = ((decode_INSTRUCTION & _zz_381_) == (32'b00000000000000000001000000000000)); + assign _zz_373_ = ((decode_INSTRUCTION & _zz_382_) == (32'b00000000000000000000000000010000)); + assign _zz_374_ = (1'b0); + assign _zz_375_ = (_zz_126_ != (1'b0)); + assign _zz_376_ = (_zz_383_ != (1'b0)); + assign _zz_377_ = {(_zz_384_ != _zz_385_),{_zz_386_,_zz_387_}}; + assign _zz_378_ = (32'b00000000000000000011000000000000); + assign _zz_379_ = (32'b00000000000000000011000000000000); + assign _zz_380_ = (32'b00000000000000000010000000010000); + assign _zz_381_ = (32'b00000000000000000101000000000000); + assign _zz_382_ = (32'b00000000000000000000000000010000); + assign _zz_383_ = ((decode_INSTRUCTION & (32'b00010000000000000011000001010000)) == (32'b00000000000000000000000001010000)); + assign _zz_384_ = {_zz_126_,((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000))}; + assign _zz_385_ = (2'b00); + assign _zz_386_ = ({_zz_125_,_zz_124_} != (2'b00)); + assign _zz_387_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)),_zz_124_} != (2'b00)); + assign _zz_388_ = execute_INSTRUCTION[31]; + assign _zz_389_ = execute_INSTRUCTION[31]; + assign _zz_390_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_52_) begin + RegFilePlugin_regFile[writeBack_RegFilePlugin_regFileWrite_payload_address] <= writeBack_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_264_) begin + _zz_179_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_265_) begin + _zz_180_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid(iBus_rsp_takeWhen_valid), + .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready), + .io_push_payload_error(iBus_rsp_takeWhen_payload_error), + .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst), + .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), + .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready), + .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error), + .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst), + .io_flush(_zz_178_), + .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_266_) + 2'b00 : begin + _zz_181_ = _zz_92_; + end + 2'b01 : begin + _zz_181_ = _zz_89_; + end + default : begin + _zz_181_ = _zz_86_; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_1__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_1__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_1__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_1__string = "SRA_1 "; + default : _zz_1__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_2__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_2__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_2__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_2__string = "SRA_1 "; + default : _zz_2__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_3__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_3__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_3__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_3__string = "SRA_1 "; + default : _zz_3__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_4_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; + default : _zz_4__string = "???"; + endcase + end + always @(*) begin + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; + default : _zz_5__string = "???"; + endcase + end + always @(*) begin + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC "; + default : _zz_6__string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_7__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_7__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_7__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_7__string = "SRC1 "; + default : _zz_7__string = "?????"; + endcase + end + always @(*) begin + case(_zz_8_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_8__string = "SRC1 "; + default : _zz_8__string = "?????"; + endcase + end + always @(*) begin + case(_zz_9_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_9__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_9__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_9__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_9__string = "SRC1 "; + default : _zz_9__string = "?????"; + endcase + end + always @(*) begin + case(_zz_10_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_10__string = "EBREAK"; + default : _zz_10__string = "??????"; + endcase + end + always @(*) begin + case(_zz_11_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_11__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_11__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_11__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_11__string = "EBREAK"; + default : _zz_11__string = "??????"; + endcase + end + always @(*) begin + case(_zz_12_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_12__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_12__string = "EBREAK"; + default : _zz_12__string = "??????"; + endcase + end + always @(*) begin + case(_zz_13_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_13__string = "EBREAK"; + default : _zz_13__string = "??????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_14_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_14__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_14__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_14__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_14__string = "EBREAK"; + default : _zz_14__string = "??????"; + endcase + end + always @(*) begin + case(_zz_15_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_15__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_15__string = "EBREAK"; + default : _zz_15__string = "??????"; + endcase + end + always @(*) begin + case(_zz_16_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_16__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_16__string = "EBREAK"; + default : _zz_16__string = "??????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_17__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_17__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_17__string = "URS1 "; + default : _zz_17__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_18_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_18__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_18__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_18__string = "URS1 "; + default : _zz_18__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_19_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_19__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_19__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_19__string = "URS1 "; + default : _zz_19__string = "????????????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_20_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20__string = "BITWISE "; + default : _zz_20__string = "????????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21__string = "BITWISE "; + default : _zz_21__string = "????????"; + endcase + end + always @(*) begin + case(_zz_22_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22__string = "BITWISE "; + default : _zz_22__string = "????????"; + endcase + end + always @(*) begin + case(_zz_23_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_23__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_23__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_23__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_23__string = "JALR"; + default : _zz_23__string = "????"; + endcase + end + always @(*) begin + case(_zz_24_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_24__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_24__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_24__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_24__string = "JALR"; + default : _zz_24__string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : memory_ENV_CTRL_string = "EBREAK"; + default : memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_26_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_26__string = "EBREAK"; + default : _zz_26__string = "??????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_27_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_27__string = "EBREAK"; + default : _zz_27__string = "??????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : writeBack_ENV_CTRL_string = "EBREAK"; + default : writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_30_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_30__string = "EBREAK"; + default : _zz_30__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_34_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_34__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_34__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_34__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_34__string = "JALR"; + default : _zz_34__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_38_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38__string = "SRA_1 "; + default : _zz_38__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_43_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_43__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_43__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_43__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_43__string = "PC "; + default : _zz_43__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_45_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_45__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_45__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_45__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_45__string = "URS1 "; + default : _zz_45__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_47_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_47__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_47__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_47__string = "BITWISE "; + default : _zz_47__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_49__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_49__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_49__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_49__string = "SRC1 "; + default : _zz_49__string = "?????"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; + default : _zz_56__string = "????????"; + endcase + end + always @(*) begin + case(_zz_62_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_62__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_62__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_62__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_62__string = "SRA_1 "; + default : _zz_62__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_63_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_63__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_63__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_63__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_63__string = "PC "; + default : _zz_63__string = "???"; + endcase + end + always @(*) begin + case(_zz_64_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_64__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_64__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_64__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_64__string = "JALR"; + default : _zz_64__string = "????"; + endcase + end + always @(*) begin + case(_zz_66_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_66__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_66__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_66__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_66__string = "SRC1 "; + default : _zz_66__string = "?????"; + endcase + end + always @(*) begin + case(_zz_70_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_70__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_70__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_70__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_70__string = "EBREAK"; + default : _zz_70__string = "??????"; + endcase + end + always @(*) begin + case(_zz_71_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_71__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_71__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_71__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_71__string = "URS1 "; + default : _zz_71__string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_76_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_76__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_76__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_76__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_76__string = "JALR"; + default : _zz_76__string = "????"; + endcase + end + always @(*) begin + case(_zz_129_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_129__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_129__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_129__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_129__string = "URS1 "; + default : _zz_129__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_130_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_130__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_130__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_130__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_130__string = "EBREAK"; + default : _zz_130__string = "??????"; + endcase + end + always @(*) begin + case(_zz_131_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_131__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_131__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_131__string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_131__string = "SRC1 "; + default : _zz_131__string = "?????"; + endcase + end + always @(*) begin + case(_zz_132_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_132__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_132__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_132__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_132__string = "JALR"; + default : _zz_132__string = "????"; + endcase + end + always @(*) begin + case(_zz_133_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_133__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_133__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_133__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_133__string = "PC "; + default : _zz_133__string = "???"; + endcase + end + always @(*) begin + case(_zz_134_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_134__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_134__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_134__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_134__string = "SRA_1 "; + default : _zz_134__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_135_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_135__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_135__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_135__string = "BITWISE "; + default : _zz_135__string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_to_memory_ENV_CTRL_string = "EBREAK"; + default : execute_to_memory_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : memory_to_writeBack_ENV_CTRL_string = "EBREAK"; + default : memory_to_writeBack_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_to_execute_ALU_BITWISE_CTRL_string = "SRC1 "; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + `endif + + assign decode_SHIFT_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_SRC_LESS_UNSIGNED = _zz_67_; + assign decode_SRC_USE_SUB_LESS = _zz_57_; + assign decode_SRC2_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign memory_PC = execute_to_memory_PC; + assign decode_ALU_BITWISE_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_36_; + assign decode_CSR_WRITE_OPCODE = _zz_29_; + assign decode_CSR_READ_OPCODE = _zz_28_; + assign decode_DO_EBREAK = _zz_25_; + assign _zz_10_ = _zz_11_; + assign _zz_12_ = _zz_13_; + assign decode_ENV_CTRL = _zz_14_; + assign _zz_15_ = _zz_16_; + assign decode_RS2_USE = _zz_61_; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_68_; + assign decode_MEMORY_ENABLE = _zz_60_; + assign decode_RS1_USE = _zz_65_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_74_; + assign decode_SRC1_CTRL = _zz_17_; + assign _zz_18_ = _zz_19_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign decode_ALU_CTRL = _zz_20_; + assign _zz_21_ = _zz_22_; + assign _zz_23_ = _zz_24_; + assign decode_IS_CSR = _zz_55_; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_48_; + assign memory_MEMORY_READ_DATA = _zz_73_; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_79_; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_69_; + assign execute_RS2_USE = decode_to_execute_RS2_USE; + assign execute_RS1_USE = decode_to_execute_RS1_USE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_26_; + assign execute_ENV_CTRL = _zz_27_; + assign writeBack_ENV_CTRL = _zz_30_; + assign execute_IS_FENCEI = decode_to_execute_IS_FENCEI; + always @ (*) begin + _zz_31_ = decode_INSTRUCTION; + if(decode_IS_FENCEI)begin + _zz_31_[12] = 1'b0; + _zz_31_[22] = 1'b1; + end + end + + assign execute_BRANCH_CALC = _zz_32_; + assign execute_BRANCH_DO = _zz_33_; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = _zz_54_; + assign execute_BRANCH_COND_RESULT = _zz_35_; + assign execute_BRANCH_CTRL = _zz_34_; + assign decode_IS_FENCEI = _zz_59_; + always @ (*) begin + _zz_37_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_182_)begin + _zz_37_ = _zz_143_; + if(_zz_183_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_37_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_SHIFT_CTRL = _zz_38_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_42_ = execute_PC; + assign execute_SRC2_CTRL = _zz_43_; + assign execute_SRC1_CTRL = _zz_45_; + assign execute_SRC_ADD_SUB = _zz_41_; + assign execute_SRC_LESS = _zz_39_; + assign execute_ALU_CTRL = _zz_47_; + assign execute_SRC2 = _zz_44_; + assign execute_SRC1 = _zz_46_; + assign execute_ALU_BITWISE_CTRL = _zz_49_; + assign _zz_50_ = writeBack_INSTRUCTION; + assign _zz_51_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_52_ = 1'b0; + if(writeBack_RegFilePlugin_regFileWrite_valid)begin + _zz_52_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_58_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_72_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_72_ = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_RS2 = _zz_53_; + assign execute_SRC_ADD = _zz_40_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_ALIGNEMENT_FAULT = _zz_75_; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign decode_BRANCH_CTRL = _zz_76_; + always @ (*) begin + _zz_77_ = execute_FORMAL_PC_NEXT; + if(_zz_88_)begin + _zz_77_ = _zz_89_; + end + end + + always @ (*) begin + _zz_78_ = decode_FORMAL_PC_NEXT; + if(_zz_85_)begin + _zz_78_ = _zz_86_; + end + end + + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + assign decode_PC = _zz_81_; + always @ (*) begin + decode_INSTRUCTION = _zz_80_; + if((_zz_173_ != (3'b000)))begin + decode_INSTRUCTION = _zz_174_; + end + end + + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + decode_arbitration_isValid = (IBusSimplePlugin_iBusRsp_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved)); + _zz_98_ = 1'b0; + case(_zz_173_) + 3'b000 : begin + end + 3'b001 : begin + end + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + decode_arbitration_haltItself = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b100 : begin + _zz_98_ = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((CsrPlugin_interrupt && decode_arbitration_isValid))begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))} != (2'b00)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_removeIt = 1'b0; + if(_zz_88_)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_exception_agregat_valid)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_redoIt = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + _zz_82_ = 1'b0; + _zz_83_ = 1'b0; + if(((execute_arbitration_isValid && execute_IS_FENCEI) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))))begin + execute_arbitration_haltByOther = 1'b1; + end + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode}}} != (4'b0000)))begin + _zz_82_ = 1'b1; + end + if((execute_arbitration_isValid && (_zz_165_ || _zz_166_)))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_184_)begin + execute_arbitration_haltByOther = 1'b1; + if(_zz_185_)begin + _zz_83_ = 1'b1; + _zz_82_ = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + _zz_82_ = 1'b1; + end + if(_zz_186_)begin + _zz_82_ = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(memory_exception_agregat_valid)begin + execute_arbitration_flushAll = 1'b1; + end + if(_zz_184_)begin + if(_zz_185_)begin + execute_arbitration_flushAll = 1'b1; + end + end + end + + assign execute_arbitration_redoIt = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin + memory_arbitration_haltItself = 1'b1; + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_exception_agregat_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushAll = 1'b0; + _zz_91_ = 1'b0; + _zz_92_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_187_)begin + _zz_91_ = 1'b1; + _zz_92_ = {CsrPlugin_mtvec_base,(2'b00)}; + memory_arbitration_flushAll = 1'b1; + end + if(_zz_188_)begin + _zz_92_ = CsrPlugin_mepc; + _zz_91_ = 1'b1; + memory_arbitration_flushAll = 1'b1; + end + end + + assign memory_arbitration_redoIt = 1'b0; + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushAll = 1'b0; + assign writeBack_arbitration_redoIt = 1'b0; + always @ (*) begin + _zz_84_ = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + _zz_84_ = 1'b1; + end + end + + always @ (*) begin + _zz_95_ = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + _zz_95_ = 1'b0; + end + end + + always @ (*) begin + _zz_96_ = 1'b1; + if(DebugPlugin_haltIt)begin + _zz_96_ = 1'b0; + end + end + + assign IBusSimplePlugin_jump_pcLoad_valid = ({_zz_91_,{_zz_88_,_zz_85_}} != (3'b000)); + assign _zz_99_ = {_zz_85_,{_zz_88_,_zz_91_}}; + assign _zz_100_ = (_zz_99_ & (~ _zz_195_)); + assign _zz_101_ = _zz_100_[1]; + assign _zz_102_ = _zz_100_[2]; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_181_; + assign _zz_103_ = (! _zz_82_); + assign IBusSimplePlugin_fetchPc_output_valid = (IBusSimplePlugin_fetchPc_preOutput_valid && _zz_103_); + assign IBusSimplePlugin_fetchPc_preOutput_ready = (IBusSimplePlugin_fetchPc_output_ready && _zz_103_); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusSimplePlugin_fetchPc_propagatePc = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_iBusRsp_stages_1_input_ready))begin + IBusSimplePlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_197_); + IBusSimplePlugin_fetchPc_samplePcNext = 1'b0; + if(IBusSimplePlugin_fetchPc_propagatePc)begin + IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + if(_zz_189_)begin + IBusSimplePlugin_fetchPc_samplePcNext = 1'b1; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusSimplePlugin_fetchPc_preOutput_valid = _zz_104_; + assign IBusSimplePlugin_fetchPc_preOutput_payload = IBusSimplePlugin_fetchPc_pc; + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_105_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_105_); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_105_); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + assign _zz_106_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_106_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_106_); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_107_; + assign _zz_107_ = ((1'b0 && (! _zz_108_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_108_ = _zz_109_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_108_; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + assign IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + assign IBusSimplePlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign _zz_81_ = IBusSimplePlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_80_ = IBusSimplePlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_79_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_110_ = _zz_198_[11]; + always @ (*) begin + _zz_111_[18] = _zz_110_; + _zz_111_[17] = _zz_110_; + _zz_111_[16] = _zz_110_; + _zz_111_[15] = _zz_110_; + _zz_111_[14] = _zz_110_; + _zz_111_[13] = _zz_110_; + _zz_111_[12] = _zz_110_; + _zz_111_[11] = _zz_110_; + _zz_111_[10] = _zz_110_; + _zz_111_[9] = _zz_110_; + _zz_111_[8] = _zz_110_; + _zz_111_[7] = _zz_110_; + _zz_111_[6] = _zz_110_; + _zz_111_[5] = _zz_110_; + _zz_111_[4] = _zz_110_; + _zz_111_[3] = _zz_110_; + _zz_111_[2] = _zz_110_; + _zz_111_[1] = _zz_110_; + _zz_111_[0] = _zz_110_; + end + + assign _zz_87_ = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_199_[31])); + assign _zz_85_ = (_zz_87_ && decode_arbitration_isFiring); + assign _zz_112_ = _zz_200_[19]; + always @ (*) begin + _zz_113_[10] = _zz_112_; + _zz_113_[9] = _zz_112_; + _zz_113_[8] = _zz_112_; + _zz_113_[7] = _zz_112_; + _zz_113_[6] = _zz_112_; + _zz_113_[5] = _zz_112_; + _zz_113_[4] = _zz_112_; + _zz_113_[3] = _zz_112_; + _zz_113_[2] = _zz_112_; + _zz_113_[1] = _zz_112_; + _zz_113_[0] = _zz_112_; + end + + assign _zz_114_ = _zz_201_[11]; + always @ (*) begin + _zz_115_[18] = _zz_114_; + _zz_115_[17] = _zz_114_; + _zz_115_[16] = _zz_114_; + _zz_115_[15] = _zz_114_; + _zz_115_[14] = _zz_114_; + _zz_115_[13] = _zz_114_; + _zz_115_[12] = _zz_114_; + _zz_115_[11] = _zz_114_; + _zz_115_[10] = _zz_114_; + _zz_115_[9] = _zz_114_; + _zz_115_[8] = _zz_114_; + _zz_115_[7] = _zz_114_; + _zz_115_[6] = _zz_114_; + _zz_115_[5] = _zz_114_; + _zz_115_[4] = _zz_114_; + _zz_115_[3] = _zz_114_; + _zz_115_[2] = _zz_114_; + _zz_115_[1] = _zz_114_; + _zz_115_[0] = _zz_114_; + end + + assign _zz_86_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_113_,{{{_zz_267_,_zz_268_},_zz_269_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_115_,{{{_zz_270_,_zz_271_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pendingCmdNext = (_zz_202_ - _zz_206_); + assign IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (2'b11))); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],(2'b00)}; + assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (2'b00)))); + assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error; + assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst; + assign _zz_178_ = (IBusSimplePlugin_jump_pcLoad_valid || _zz_83_); + assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; + assign IBusSimplePlugin_rspJoin_issueDetected = 1'b0; + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_116_ = (! IBusSimplePlugin_rspJoin_issueDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_decodeInput_ready && _zz_116_); + assign IBusSimplePlugin_iBusRsp_decodeInput_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_116_); + assign IBusSimplePlugin_iBusRsp_decodeInput_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_decodeInput_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_decodeInput_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + assign execute_DBusSimplePlugin_cmdSent = 1'b0; + assign _zz_75_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_INSTRUCTION[5]; + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_117_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_117_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_117_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_117_; + assign _zz_74_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_118_ = (4'b0001); + end + 2'b01 : begin + _zz_118_ = (4'b0011); + end + default : begin + _zz_118_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_118_ <<< dBus_cmd_payload_address[1 : 0]); + assign _zz_73_ = dBus_rsp_data; + assign memory_exception_agregat_payload_code = {1'd0, _zz_211_}; + always @ (*) begin + memory_exception_agregat_valid = memory_ALIGNEMENT_FAULT; + if((! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && 1'b1)))begin + memory_exception_agregat_valid = 1'b0; + end + end + + assign memory_exception_agregat_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_119_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_120_[31] = _zz_119_; + _zz_120_[30] = _zz_119_; + _zz_120_[29] = _zz_119_; + _zz_120_[28] = _zz_119_; + _zz_120_[27] = _zz_119_; + _zz_120_[26] = _zz_119_; + _zz_120_[25] = _zz_119_; + _zz_120_[24] = _zz_119_; + _zz_120_[23] = _zz_119_; + _zz_120_[22] = _zz_119_; + _zz_120_[21] = _zz_119_; + _zz_120_[20] = _zz_119_; + _zz_120_[19] = _zz_119_; + _zz_120_[18] = _zz_119_; + _zz_120_[17] = _zz_119_; + _zz_120_[16] = _zz_119_; + _zz_120_[15] = _zz_119_; + _zz_120_[14] = _zz_119_; + _zz_120_[13] = _zz_119_; + _zz_120_[12] = _zz_119_; + _zz_120_[11] = _zz_119_; + _zz_120_[10] = _zz_119_; + _zz_120_[9] = _zz_119_; + _zz_120_[8] = _zz_119_; + _zz_120_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_121_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_122_[31] = _zz_121_; + _zz_122_[30] = _zz_121_; + _zz_122_[29] = _zz_121_; + _zz_122_[28] = _zz_121_; + _zz_122_[27] = _zz_121_; + _zz_122_[26] = _zz_121_; + _zz_122_[25] = _zz_121_; + _zz_122_[24] = _zz_121_; + _zz_122_[23] = _zz_121_; + _zz_122_[22] = _zz_121_; + _zz_122_[21] = _zz_121_; + _zz_122_[20] = _zz_121_; + _zz_122_[19] = _zz_121_; + _zz_122_[18] = _zz_121_; + _zz_122_[17] = _zz_121_; + _zz_122_[16] = _zz_121_; + _zz_122_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_192_) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_120_; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_122_; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_124_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_125_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); + assign _zz_126_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_127_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_128_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_123_ = {({(_zz_272_ == _zz_273_),(_zz_274_ == _zz_275_)} != (2'b00)),{({_zz_276_,{_zz_277_,_zz_278_}} != (3'b000)),{(_zz_279_ != (1'b0)),{(_zz_280_ != _zz_281_),{_zz_282_,{_zz_283_,_zz_284_}}}}}}; + assign _zz_129_ = _zz_123_[1 : 0]; + assign _zz_71_ = _zz_129_; + assign _zz_130_ = _zz_123_[3 : 2]; + assign _zz_70_ = _zz_130_; + assign _zz_69_ = _zz_212_[0]; + assign _zz_68_ = _zz_213_[0]; + assign _zz_67_ = _zz_214_[0]; + assign _zz_131_ = _zz_123_[8 : 7]; + assign _zz_66_ = _zz_131_; + assign _zz_65_ = _zz_215_[0]; + assign _zz_132_ = _zz_123_[12 : 11]; + assign _zz_64_ = _zz_132_; + assign _zz_133_ = _zz_123_[14 : 13]; + assign _zz_63_ = _zz_133_; + assign _zz_134_ = _zz_123_[16 : 15]; + assign _zz_62_ = _zz_134_; + assign _zz_61_ = _zz_216_[0]; + assign _zz_60_ = _zz_217_[0]; + assign _zz_59_ = _zz_218_[0]; + assign _zz_58_ = _zz_219_[0]; + assign _zz_57_ = _zz_220_[0]; + assign _zz_135_ = _zz_123_[24 : 23]; + assign _zz_56_ = _zz_135_; + assign _zz_55_ = _zz_221_[0]; + assign execute_RegFilePlugin_srcInstruction = (execute_arbitration_isStuck ? execute_INSTRUCTION : decode_INSTRUCTION); + assign execute_RegFilePlugin_regFileReadAddress1 = execute_RegFilePlugin_srcInstruction[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = execute_RegFilePlugin_srcInstruction[24 : 20]; + assign execute_RegFilePlugin_rs1Data = _zz_179_; + assign execute_RegFilePlugin_rs2Data = _zz_180_; + assign _zz_54_ = execute_RegFilePlugin_rs1Data; + assign _zz_53_ = execute_RegFilePlugin_rs2Data; + assign writeBack_RegFilePlugin_regFileWrite_valid = (_zz_51_ && writeBack_arbitration_isFiring); + assign writeBack_RegFilePlugin_regFileWrite_payload_address = _zz_50_[11 : 7]; + assign writeBack_RegFilePlugin_regFileWrite_payload_data = _zz_72_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = execute_SRC1; + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_136_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_136_ = {31'd0, _zz_222_}; + end + default : begin + _zz_136_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_48_ = _zz_136_; + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_137_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_137_ = {29'd0, _zz_223_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_137_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_137_ = {27'd0, _zz_224_}; + end + endcase + end + + assign _zz_46_ = _zz_137_; + assign _zz_138_ = _zz_225_[11]; + always @ (*) begin + _zz_139_[19] = _zz_138_; + _zz_139_[18] = _zz_138_; + _zz_139_[17] = _zz_138_; + _zz_139_[16] = _zz_138_; + _zz_139_[15] = _zz_138_; + _zz_139_[14] = _zz_138_; + _zz_139_[13] = _zz_138_; + _zz_139_[12] = _zz_138_; + _zz_139_[11] = _zz_138_; + _zz_139_[10] = _zz_138_; + _zz_139_[9] = _zz_138_; + _zz_139_[8] = _zz_138_; + _zz_139_[7] = _zz_138_; + _zz_139_[6] = _zz_138_; + _zz_139_[5] = _zz_138_; + _zz_139_[4] = _zz_138_; + _zz_139_[3] = _zz_138_; + _zz_139_[2] = _zz_138_; + _zz_139_[1] = _zz_138_; + _zz_139_[0] = _zz_138_; + end + + assign _zz_140_ = _zz_226_[11]; + always @ (*) begin + _zz_141_[19] = _zz_140_; + _zz_141_[18] = _zz_140_; + _zz_141_[17] = _zz_140_; + _zz_141_[16] = _zz_140_; + _zz_141_[15] = _zz_140_; + _zz_141_[14] = _zz_140_; + _zz_141_[13] = _zz_140_; + _zz_141_[12] = _zz_140_; + _zz_141_[11] = _zz_140_; + _zz_141_[10] = _zz_140_; + _zz_141_[9] = _zz_140_; + _zz_141_[8] = _zz_140_; + _zz_141_[7] = _zz_140_; + _zz_141_[6] = _zz_140_; + _zz_141_[5] = _zz_140_; + _zz_141_[4] = _zz_140_; + _zz_141_[3] = _zz_140_; + _zz_141_[2] = _zz_140_; + _zz_141_[1] = _zz_140_; + _zz_141_[0] = _zz_140_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_142_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_142_ = {_zz_139_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_142_ = {_zz_141_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_142_ = _zz_42_; + end + endcase + end + + assign _zz_44_ = _zz_142_; + assign execute_SrcPlugin_addSub = _zz_227_; + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_41_ = execute_SrcPlugin_addSub; + assign _zz_40_ = execute_SrcPlugin_addSub; + assign _zz_39_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_143_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_143_ = _zz_235_; + end + endcase + end + + assign _zz_36_ = (_zz_87_ && (! decode_IS_FENCEI)); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_144_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_144_ == (3'b000))) begin + _zz_145_ = execute_BranchPlugin_eq; + end else if((_zz_144_ == (3'b001))) begin + _zz_145_ = (! execute_BranchPlugin_eq); + end else if((((_zz_144_ & (3'b101)) == (3'b101)))) begin + _zz_145_ = (! execute_SRC_LESS); + end else begin + _zz_145_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_146_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_146_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_146_ = 1'b1; + end + default : begin + _zz_146_ = _zz_145_; + end + endcase + end + + assign _zz_35_ = _zz_146_; + assign _zz_147_ = _zz_237_[11]; + always @ (*) begin + _zz_148_[19] = _zz_147_; + _zz_148_[18] = _zz_147_; + _zz_148_[17] = _zz_147_; + _zz_148_[16] = _zz_147_; + _zz_148_[15] = _zz_147_; + _zz_148_[14] = _zz_147_; + _zz_148_[13] = _zz_147_; + _zz_148_[12] = _zz_147_; + _zz_148_[11] = _zz_147_; + _zz_148_[10] = _zz_147_; + _zz_148_[9] = _zz_147_; + _zz_148_[8] = _zz_147_; + _zz_148_[7] = _zz_147_; + _zz_148_[6] = _zz_147_; + _zz_148_[5] = _zz_147_; + _zz_148_[4] = _zz_147_; + _zz_148_[3] = _zz_147_; + _zz_148_[2] = _zz_147_; + _zz_148_[1] = _zz_147_; + _zz_148_[0] = _zz_147_; + end + + assign _zz_149_ = _zz_238_[19]; + always @ (*) begin + _zz_150_[10] = _zz_149_; + _zz_150_[9] = _zz_149_; + _zz_150_[8] = _zz_149_; + _zz_150_[7] = _zz_149_; + _zz_150_[6] = _zz_149_; + _zz_150_[5] = _zz_149_; + _zz_150_[4] = _zz_149_; + _zz_150_[3] = _zz_149_; + _zz_150_[2] = _zz_149_; + _zz_150_[1] = _zz_149_; + _zz_150_[0] = _zz_149_; + end + + assign _zz_151_ = _zz_239_[11]; + always @ (*) begin + _zz_152_[18] = _zz_151_; + _zz_152_[17] = _zz_151_; + _zz_152_[16] = _zz_151_; + _zz_152_[15] = _zz_151_; + _zz_152_[14] = _zz_151_; + _zz_152_[13] = _zz_151_; + _zz_152_[12] = _zz_151_; + _zz_152_[11] = _zz_151_; + _zz_152_[10] = _zz_151_; + _zz_152_[9] = _zz_151_; + _zz_152_[8] = _zz_151_; + _zz_152_[7] = _zz_151_; + _zz_152_[6] = _zz_151_; + _zz_152_[5] = _zz_151_; + _zz_152_[4] = _zz_151_; + _zz_152_[3] = _zz_151_; + _zz_152_[2] = _zz_151_; + _zz_152_[1] = _zz_151_; + _zz_152_[0] = _zz_151_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_153_ = (_zz_240_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_153_ = _zz_241_[1]; + end + default : begin + _zz_153_ = _zz_242_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_153_); + assign _zz_33_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + execute_BranchPlugin_branch_src2 = {_zz_155_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_157_,{{{_zz_388_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_159_,{{{_zz_389_,_zz_390_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if((execute_PREDICTION_HAD_BRANCHED2 && (! execute_BranchPlugin_missAlignedTarget)))begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_246_}; + end + end + endcase + end + + assign _zz_154_ = _zz_243_[11]; + always @ (*) begin + _zz_155_[19] = _zz_154_; + _zz_155_[18] = _zz_154_; + _zz_155_[17] = _zz_154_; + _zz_155_[16] = _zz_154_; + _zz_155_[15] = _zz_154_; + _zz_155_[14] = _zz_154_; + _zz_155_[13] = _zz_154_; + _zz_155_[12] = _zz_154_; + _zz_155_[11] = _zz_154_; + _zz_155_[10] = _zz_154_; + _zz_155_[9] = _zz_154_; + _zz_155_[8] = _zz_154_; + _zz_155_[7] = _zz_154_; + _zz_155_[6] = _zz_154_; + _zz_155_[5] = _zz_154_; + _zz_155_[4] = _zz_154_; + _zz_155_[3] = _zz_154_; + _zz_155_[2] = _zz_154_; + _zz_155_[1] = _zz_154_; + _zz_155_[0] = _zz_154_; + end + + assign _zz_156_ = _zz_244_[19]; + always @ (*) begin + _zz_157_[10] = _zz_156_; + _zz_157_[9] = _zz_156_; + _zz_157_[8] = _zz_156_; + _zz_157_[7] = _zz_156_; + _zz_157_[6] = _zz_156_; + _zz_157_[5] = _zz_156_; + _zz_157_[4] = _zz_156_; + _zz_157_[3] = _zz_156_; + _zz_157_[2] = _zz_156_; + _zz_157_[1] = _zz_156_; + _zz_157_[0] = _zz_156_; + end + + assign _zz_158_ = _zz_245_[11]; + always @ (*) begin + _zz_159_[18] = _zz_158_; + _zz_159_[17] = _zz_158_; + _zz_159_[16] = _zz_158_; + _zz_159_[15] = _zz_158_; + _zz_159_[14] = _zz_158_; + _zz_159_[13] = _zz_158_; + _zz_159_[12] = _zz_158_; + _zz_159_[11] = _zz_158_; + _zz_159_[10] = _zz_158_; + _zz_159_[9] = _zz_158_; + _zz_159_[8] = _zz_158_; + _zz_159_[7] = _zz_158_; + _zz_159_[6] = _zz_158_; + _zz_159_[5] = _zz_158_; + _zz_159_[4] = _zz_158_; + _zz_159_[3] = _zz_158_; + _zz_159_[2] = _zz_158_; + _zz_159_[1] = _zz_158_; + _zz_159_[0] = _zz_158_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_32_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign _zz_88_ = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign _zz_89_ = execute_BRANCH_CALC; + always @ (*) begin + _zz_90_ = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(execute_arbitration_isStuckByOthers)begin + _zz_90_ = 1'b0; + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_medeleg = (32'b00000000000000000000000000000000); + assign CsrPlugin_mideleg = (32'b00000000000000000000000000000000); + assign _zz_160_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_161_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_162_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 1'b0; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = (2'b11); + assign execute_exception_agregat_valid = ({_zz_93_,_zz_90_} != (2'b00)); + assign _zz_163_ = {_zz_93_,_zz_90_}; + assign _zz_164_ = _zz_247_[0]; + assign execute_exception_agregat_payload_code = (_zz_164_ ? (4'b0000) : _zz_94_); + assign execute_exception_agregat_payload_badAddr = (_zz_164_ ? execute_BRANCH_CALC : (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx)); + assign CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(memory_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + assign CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + if(CsrPlugin_mstatus_MIE)begin + if(({_zz_162_,{_zz_161_,_zz_160_}} != (3'b000)))begin + CsrPlugin_interrupt = 1'b1; + end + if(_zz_160_)begin + CsrPlugin_interruptCode = (4'b0111); + end + if(_zz_161_)begin + CsrPlugin_interruptCode = (4'b0011); + end + if(_zz_162_)begin + CsrPlugin_interruptCode = (4'b1011); + end + end + if((! _zz_95_))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_interruptTargetPrivilege = (2'b11); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && _zz_96_); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_injector_nextPcCalc_valids_3); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + assign contextSwitching = _zz_91_; + assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_170_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_171_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((execute_INSTRUCTION[29 : 28] != CsrPlugin_privilege))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + _zz_93_ = 1'b0; + _zz_94_ = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + _zz_93_ = 1'b1; + _zz_94_ = (4'b1011); + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + _zz_93_ = 1'b1; + _zz_94_ = (4'b0011); + end + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + case(_zz_194_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readData & (~ execute_SRC1)) : (execute_CsrPlugin_readData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + always @ (*) begin + _zz_165_ = 1'b0; + _zz_166_ = 1'b0; + if(_zz_168_)begin + if((_zz_169_ == execute_INSTRUCTION[19 : 15]))begin + _zz_165_ = 1'b1; + end + if((_zz_169_ == execute_INSTRUCTION[24 : 20]))begin + _zz_166_ = 1'b1; + end + end + if((writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID))begin + if((1'b1 || (! 1'b1)))begin + if((writeBack_INSTRUCTION[11 : 7] == execute_INSTRUCTION[19 : 15]))begin + _zz_165_ = 1'b1; + end + if((writeBack_INSTRUCTION[11 : 7] == execute_INSTRUCTION[24 : 20]))begin + _zz_166_ = 1'b1; + end + end + end + if((memory_arbitration_isValid && memory_REGFILE_WRITE_VALID))begin + if((1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)))begin + if((memory_INSTRUCTION[11 : 7] == execute_INSTRUCTION[19 : 15]))begin + _zz_165_ = 1'b1; + end + if((memory_INSTRUCTION[11 : 7] == execute_INSTRUCTION[24 : 20]))begin + _zz_166_ = 1'b1; + end + end + end + if((! execute_RS1_USE))begin + _zz_165_ = 1'b0; + end + if((! execute_RS2_USE))begin + _zz_166_ = 1'b0; + end + end + + assign _zz_167_ = (_zz_51_ && writeBack_arbitration_isFiring); + assign _zz_171_ = (_zz_170_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_171_ != (32'b00000000000000000000000000000000)); + assign DebugPlugin_isPipBusy = (DebugPlugin_isPipActive || DebugPlugin_isPipActive_regNext); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + _zz_97_ = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_190_) + 6'b000000 : begin + end + 6'b000001 : begin + if(debug_bus_cmd_payload_wr)begin + _zz_97_ = 1'b1; + debug_bus_cmd_ready = _zz_98_; + end + end + 6'b010000 : begin + end + 6'b010001 : begin + end + 6'b010010 : begin + end + 6'b010011 : begin + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_172_))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign _zz_25_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || ((((1'b0 || (DebugPlugin_hardwareBreakpoints_0_valid && (DebugPlugin_hardwareBreakpoints_0_pc == _zz_253_))) || (DebugPlugin_hardwareBreakpoints_1_valid && (DebugPlugin_hardwareBreakpoints_1_pc == _zz_254_))) || (DebugPlugin_hardwareBreakpoints_2_valid && (DebugPlugin_hardwareBreakpoints_2_pc == _zz_255_))) || (DebugPlugin_hardwareBreakpoints_3_valid && (DebugPlugin_hardwareBreakpoints_3_pc == _zz_256_))))); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_24_ = decode_BRANCH_CTRL; + assign _zz_76_ = _zz_64_; + assign _zz_34_ = decode_to_execute_BRANCH_CTRL; + assign _zz_22_ = decode_ALU_CTRL; + assign _zz_20_ = _zz_56_; + assign _zz_47_ = decode_to_execute_ALU_CTRL; + assign _zz_19_ = decode_SRC1_CTRL; + assign _zz_17_ = _zz_71_; + assign _zz_45_ = decode_to_execute_SRC1_CTRL; + assign _zz_16_ = decode_ENV_CTRL; + assign _zz_13_ = execute_ENV_CTRL; + assign _zz_11_ = memory_ENV_CTRL; + assign _zz_14_ = _zz_70_; + assign _zz_27_ = decode_to_execute_ENV_CTRL; + assign _zz_26_ = execute_to_memory_ENV_CTRL; + assign _zz_30_ = memory_to_writeBack_ENV_CTRL; + assign _zz_9_ = decode_ALU_BITWISE_CTRL; + assign _zz_7_ = _zz_66_; + assign _zz_49_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_6_ = decode_SRC2_CTRL; + assign _zz_4_ = _zz_63_; + assign _zz_43_ = decode_to_execute_SRC2_CTRL; + assign _zz_3_ = decode_SHIFT_CTRL; + assign _zz_1_ = _zz_62_; + assign _zz_38_ = decode_to_execute_SHIFT_CTRL; + assign decode_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,{execute_arbitration_flushAll,decode_arbitration_flushAll}}} != (4'b0000)); + assign execute_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,execute_arbitration_flushAll}} != (3'b000)); + assign memory_arbitration_isFlushed = ({writeBack_arbitration_flushAll,memory_arbitration_flushAll} != (2'b00)); + assign writeBack_arbitration_isFlushed = (writeBack_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); + assign iBus_cmd_m2sPipe_valid = _zz_175_; + assign iBus_cmd_m2sPipe_payload_pc = _zz_176_; + assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); + assign iBusWishbone_CTI = (3'b000); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; + assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; + assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); + assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_177_ = (4'b0001); + end + 2'b01 : begin + _zz_177_ = (4'b0011); + end + default : begin + _zz_177_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_263_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + CsrPlugin_privilege <= (2'b11); + IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_104_ <= 1'b0; + _zz_109_ <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_decodeRemoved <= 1'b0; + IBusSimplePlugin_pendingCmd <= (2'b00); + IBusSimplePlugin_rspJoin_discardCounter <= (2'b00); + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mip_MEIP <= 1'b0; + CsrPlugin_mip_MTIP <= 1'b0; + CsrPlugin_mip_MSIP <= 1'b0; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_168_ <= 1'b0; + _zz_170_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_173_ <= (3'b000); + _zz_175_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusSimplePlugin_fetchPc_propagatePc)begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if(_zz_189_)begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_samplePcNext)begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + _zz_104_ <= 1'b1; + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + _zz_109_ <= 1'b0; + end + if(_zz_107_)begin + _zz_109_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusSimplePlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_injector_decodeRemoved <= 1'b0; + end + IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext; + IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_208_); + if((IBusSimplePlugin_jump_pcLoad_valid || _zz_83_))begin + IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_210_); + end + if(_zz_182_)begin + if(_zz_183_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_187_)begin + CsrPlugin_privilege <= CsrPlugin_targetPrivilege; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_188_)begin + case(_zz_193_) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPIE <= 1'b1; + CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; + end + default : begin + end + endcase + end + _zz_168_ <= _zz_167_; + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_173_) + 3'b000 : begin + if(_zz_97_)begin + _zz_173_ <= (3'b001); + end + end + 3'b001 : begin + _zz_173_ <= (3'b010); + end + 3'b010 : begin + _zz_173_ <= (3'b011); + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_173_ <= (3'b100); + end + end + 3'b100 : begin + _zz_173_ <= (3'b000); + end + default : begin + end + endcase + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_170_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_257_[0]; + CsrPlugin_mstatus_MIE <= _zz_258_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_259_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_260_[0]; + CsrPlugin_mie_MTIE <= _zz_261_[0]; + CsrPlugin_mie_MSIE <= _zz_262_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(iBus_cmd_ready)begin + _zz_175_ <= iBus_cmd_valid; + end + if(_zz_191_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); + end + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_INSTRUCTION[5])) && writeBack_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + end + if(_zz_182_)begin + if(_zz_183_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(execute_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= execute_exception_agregat_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= execute_exception_agregat_payload_badAddr; + end + if(memory_exception_agregat_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= memory_exception_agregat_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= memory_exception_agregat_payload_badAddr; + end + if((CsrPlugin_exception || CsrPlugin_interruptJump))begin + case(CsrPlugin_privilege) + 2'b11 : begin + CsrPlugin_mepc <= writeBack_PC; + end + default : begin + end + endcase + end + if(_zz_187_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + default : begin + end + endcase + end + if(_zz_167_)begin + _zz_169_ <= _zz_50_[11 : 7]; + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_FENCEI <= decode_IS_FENCEI; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_78_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_77_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_23_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_21_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_18_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1_USE <= decode_RS1_USE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= _zz_31_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2_USE <= decode_RS2_USE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_15_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_12_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_10_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_42_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_2_; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(iBus_cmd_ready)begin + _zz_176_ <= iBus_cmd_payload_pc; + end + if(_zz_191_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipActive <= ({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)); + DebugPlugin_isPipActive_regNext <= DebugPlugin_isPipActive; + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_72_; + end + _zz_172_ <= debug_bus_cmd_payload_address[2]; + if(debug_bus_cmd_valid)begin + case(_zz_190_) + 6'b000000 : begin + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_pc <= debug_bus_cmd_payload_data[31 : 1]; + end + end + default : begin + end + endcase + end + if(_zz_184_)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_hardwareBreakpoints_0_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_1_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_2_valid <= 1'b0; + DebugPlugin_hardwareBreakpoints_3_valid <= 1'b0; + end else begin + if(debug_bus_cmd_valid)begin + case(_zz_190_) + 6'b000000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + end + end + 6'b000001 : begin + end + 6'b010000 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_0_valid <= _zz_249_[0]; + end + end + 6'b010001 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_1_valid <= _zz_250_[0]; + end + end + 6'b010010 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_2_valid <= _zz_251_[0]; + end + end + 6'b010011 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_hardwareBreakpoints_3_valid <= _zz_252_[0]; + end + end + default : begin + end + endcase + end + if(_zz_184_)begin + if(_zz_185_)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_186_)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + if((DebugPlugin_stepIt && ({writeBack_arbitration_redoIt,{memory_arbitration_redoIt,{execute_arbitration_redoIt,decode_arbitration_redoIt}}} != (4'b0000))))begin + DebugPlugin_haltIt <= 1'b0; + end + end + end + + always @ (posedge clk) begin + _zz_174_ <= debug_bus_cmd_payload_data; + end + +endmodule + diff --git a/hw/5-stage-pipelined-no-cache-debug.yaml b/hw/5-stage-pipelined-no-cache-debug.yaml new file mode 100644 index 0000000..6ab729f --- /dev/null +++ b/hw/5-stage-pipelined-no-cache-debug.yaml @@ -0,0 +1 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 4} diff --git a/hw/foboot-bitstream.py b/hw/foboot-bitstream.py index dd97bff..6709471 100755 --- a/hw/foboot-bitstream.py +++ b/hw/foboot-bitstream.py @@ -77,95 +77,130 @@ _io = [ _connectors = [] class _CRG(Module): - def __init__(self, platform): - clk48_raw = platform.request("clk48") - clk12_raw = Signal() - clk48 = Signal() - clk12 = Signal() + def __init__(self, platform, use_pll=False): + if use_pll: + clk48_raw = platform.request("clk48") + clk12_raw = Signal() + clk48 = Signal() + clk12 = Signal() - # Divide clk48 down to clk12, to ensure they're synchronized. - # By doing this, we avoid needing clock-domain crossing. - clk12_counter = Signal(2) + # Divide clk48 down to clk12, to ensure they're synchronized. + # By doing this, we avoid needing clock-domain crossing. + clk12_counter = Signal(2) - # # "0b00" Sets 48MHz HFOSC output - # # "0b01" Sets 24MHz HFOSC output. - # # "0b10" Sets 12MHz HFOSC output. - # # "0b11" Sets 6MHz HFOSC output - # self.specials += Instance( - # "SB_HFOSC", - # i_CLKHFEN=1, - # i_CLKHFPU=1, - # o_CLKHF=clk12, - # p_CLKHF_DIV="0b10", # 12MHz - # ) - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_usb_12 = ClockDomain() - self.clock_domains.cd_usb_48 = ClockDomain() - self.clock_domains.cd_usb_48_raw = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + self.clock_domains.cd_usb_48_raw = ClockDomain() - platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) - platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6) - platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6) - platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6) - platform.add_period_constraint(clk48, 1e9/48e6) - platform.add_period_constraint(clk48_raw, 1e9/48e6) + platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) + platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6) + platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6) + platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6) + platform.add_period_constraint(clk48, 1e9/48e6) + platform.add_period_constraint(clk48_raw, 1e9/48e6) - self.reset = Signal() + self.reset = Signal() - # POR reset logic- POR generated from sys clk, POR logic feeds sys clk - # reset. - self.clock_domains.cd_por = ClockDomain() - reset_delay = Signal(12, reset=4095) - self.comb += [ - self.cd_por.clk.eq(self.cd_sys.clk), - self.cd_sys.rst.eq(reset_delay != 0), - self.cd_usb_12.rst.eq(reset_delay != 0), - self.cd_usb_48.rst.eq(reset_delay != 0), - # self.cd_usb_48_raw.rst.eq(reset_delay != 0), - ] + # POR reset logic- POR generated from sys clk, POR logic feeds sys clk + # reset. + self.clock_domains.cd_por = ClockDomain() + reset_delay = Signal(10, reset=1023) + self.comb += [ + self.cd_por.clk.eq(self.cd_sys.clk), + self.cd_sys.rst.eq(reset_delay != 0), + self.cd_usb_12.rst.eq(reset_delay != 0), + self.cd_usb_48.rst.eq(reset_delay != 0), + # self.cd_usb_48_raw.rst.eq(reset_delay != 0), + ] - self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw) - self.comb += self.cd_usb_48.clk.eq(clk48) + self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw) + self.comb += self.cd_usb_48.clk.eq(clk48) - self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1) + self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1) - self.comb += clk12_raw.eq(clk12_counter[1]) - self.specials += Instance( - "SB_GB", - i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw, - o_GLOBAL_BUFFER_OUTPUT=clk12, - ) - platform.add_period_constraint(clk12_raw, 1e9/12e6) + self.comb += clk12_raw.eq(clk12_counter[1]) + self.specials += Instance( + "SB_GB", + i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw, + o_GLOBAL_BUFFER_OUTPUT=clk12, + ) + platform.add_period_constraint(clk12_raw, 1e9/12e6) - self.specials += Instance( - "SB_PLL40_CORE", - # Parameters - p_DIVR = 0, - p_DIVF = 3, - p_DIVQ = 2, - p_FILTER_RANGE = 1, - p_FEEDBACK_PATH = "PHASE_AND_DELAY", - p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED", - p_FDA_FEEDBACK = 15, - p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED", - p_FDA_RELATIVE = 0, - p_SHIFTREG_DIV_MODE = 1, - p_PLLOUT_SELECT = "SHIFTREG_0deg", - p_ENABLE_ICEGATE = 0, - # IO - i_REFERENCECLK = clk12, - # o_PLLOUTCORE = clk12, - o_PLLOUTGLOBAL = clk48, - #i_EXTFEEDBACK, - #i_DYNAMICDELAY, - #o_LOCK, - i_BYPASS = 0, - i_RESETB = 1, - #i_LATCHINPUTVALUE, - #o_SDO, - #i_SDI, - ) + self.specials += Instance( + "SB_PLL40_CORE", + # Parameters + p_DIVR = 0, + p_DIVF = 3, + p_DIVQ = 2, + p_FILTER_RANGE = 1, + p_FEEDBACK_PATH = "PHASE_AND_DELAY", + p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED", + p_FDA_FEEDBACK = 15, + p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED", + p_FDA_RELATIVE = 0, + p_SHIFTREG_DIV_MODE = 1, + p_PLLOUT_SELECT = "SHIFTREG_0deg", + p_ENABLE_ICEGATE = 0, + # IO + i_REFERENCECLK = clk12, + # o_PLLOUTCORE = clk12, + o_PLLOUTGLOBAL = clk48, + #i_EXTFEEDBACK, + #i_DYNAMICDELAY, + #o_LOCK, + i_BYPASS = 0, + i_RESETB = 1, + #i_LATCHINPUTVALUE, + #o_SDO, + #i_SDI, + ) + else: + clk48_raw = platform.request("clk48") + clk12_raw = Signal() + clk48 = Signal() + clk12 = Signal() + + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + + platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) + platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6) + platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6) + platform.add_period_constraint(clk48, 1e9/48e6) + + self.reset = Signal() + + # POR reset logic- POR generated from sys clk, POR logic feeds sys clk + # reset. + self.clock_domains.cd_por = ClockDomain() + reset_delay = Signal(10, reset=1023) + self.comb += [ + self.cd_por.clk.eq(self.cd_sys.clk), + self.cd_sys.rst.eq(reset_delay != 0), + self.cd_usb_12.rst.eq(reset_delay != 0), + # self.cd_usb_48.rst.eq(reset_delay != 0), + ] + + self.specials += Instance( + "SB_GB", + i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw, + o_GLOBAL_BUFFER_OUTPUT=clk48, + ) + self.comb += self.cd_usb_48.clk.eq(clk48) + + clk12_counter = Signal(2) + self.sync.usb_48 += clk12_counter.eq(clk12_counter + 1) + + self.comb += clk12_raw.eq(clk12_counter[1]) + platform.add_period_constraint(clk12_raw, 1e9/12e6) + self.specials += Instance( + "SB_GB", + i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw, + o_GLOBAL_BUFFER_OUTPUT=clk12, + ) self.comb += self.cd_sys.clk.eq(clk12) self.comb += self.cd_usb_12.clk.eq(clk12) @@ -202,6 +237,13 @@ class RandomFirmwareROM(wishbone.SRAM): data.append(seed) wishbone.SRAM.__init__(self, size, read_only=True, init=data) +class FirmwareROM(wishbone.SRAM): + def __init__(self, size, filename): + data = [] + with open(filename, 'rb') as inp: + data = inp.read() + wishbone.SRAM.__init__(self, size, read_only=True, init=data) + class Platform(LatticePlatform): default_clk_name = "clk48" default_clk_period = 20.833 @@ -210,35 +252,43 @@ class Platform(LatticePlatform): def __init__(self, toolchain="icestorm"): LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm") - # Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command. - # The "-reult" adds an additional LUT pass to pack more stuff in, - # and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a - # Clock Enable signal for a LUT that has fewer than 4 flip-flops. - # This increases density, and lets us use the FPGA more efficiently. - for i in range(len(self.toolchain.nextpnr_yosys_template)): - entry = self.toolchain.nextpnr_yosys_template[i] - if "synth_ice40" in entry: - self.toolchain.nextpnr_yosys_template[i] = entry + " -dsp -relut -dffe_min_ce_use 4" + def create_programmer(self): raise ValueError("programming is not supported") # def do_finalize(self, fragment): # LatticePlatform.do_finalize(self, fragment) -class PicoSoCSpi(Module, AutoCSR): +class SBWarmBoot(Module, AutoCSR): + def __init__(self): + self.ctrl = CSRStorage(size=8) + do_reset = Signal() + self.comb += [ + # "Reset Key" is 0xac + do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4] + & self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7]) + ] + self.specials += Instance("SB_WARMBOOT", + i_BOOT=do_reset, + i_S0 = self.ctrl.storage[0], + i_S1 = self.ctrl.storage[1] + ) + + +class BBSpi(Module, AutoCSR): def __init__(self, platform, pads): self.reset = Signal() - self.rdata = Signal(32) - self.addr = Signal(24) - self.ready = Signal() - self.valid = Signal() + # self.rdata = Signal(32) + # self.addr = Signal(24) + # self.ready = Signal() + # self.valid = Signal() - self.flash_csb = Signal() - self.flash_clk = Signal() + # self.flash_csb = Signal() + # self.flash_clk = Signal() - cfgreg_we = Signal(4) - cfgreg_di = Signal(32) - cfgreg_do = Signal(32) + # cfgreg_we = Signal(4) + # cfgreg_di = Signal(32) + # cfgreg_do = Signal(32) mosi_pad = TSTriple() miso_pad = TSTriple() @@ -254,7 +304,7 @@ class PicoSoCSpi(Module, AutoCSR): # cfg_remapped = Cat(self.cfg.storage[0:7], Signal(7), self.cfg.storage[7]) - self.comb += self.reset.eq(0) + # self.comb += self.reset.eq(0) # self.comb += [ # cfgreg_di.eq(Cat(self.do.storage, Replicate(2, 0), # Attach "DO" to lower 6 bits # self.oe.storage, Replicate(4, 0), # Attach "OE" to bits 8-11 @@ -326,7 +376,8 @@ class BaseSoC(SoCCore): csr_peripherals = [ "cpu_or_bridge", "usb", - "picospi", + "bbspi", + "reboot", ] csr_map_update(SoCCore.csr_map, csr_peripherals) @@ -340,18 +391,21 @@ class BaseSoC(SoCCore): } interrupt_map.update(SoCCore.interrupt_map) - def __init__(self, platform, boot_source="random_rom", debug=False, **kwargs): + def __init__(self, platform, boot_source="random_rom", debug=False, bios_file=None, use_pll=True, **kwargs): # Disable integrated RAM as we'll add it later self.integrated_sram_size = 0 clk_freq = int(12e6) - self.submodules.crg = _CRG(platform) + self.submodules.crg = _CRG(platform, use_pll) - SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs) + SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, with_uart=False, **kwargs) if debug: - self.cpu.use_external_variant("vexriscv-2-stage-with-debug.v") + from litex.soc.cores.uart import UARTWishboneBridge + self.cpu.use_external_variant("2-stage-1024-cache-debug.v") self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x10) + self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200) + self.add_wb_master(self.uart_bridge.wishbone) # SPRAM- UP5K has single port RAM, might as well use it as SRAM to # free up scarce block RAM. @@ -367,8 +421,15 @@ class BaseSoC(SoCCore): self.register_rom(self.random_rom.bus, bios_size) elif boot_source == "bios_rom": kwargs['cpu_reset_address']=0 - bios_size = 0x2000 - self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size) + if bios_file is None: + bios_size = 0x2000 + self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size) + else: + bios_size = 0x2000 + self.submodules.firmware_rom = FirmwareROM(bios_size, bios_file) + self.add_constant("ROM_DISABLE", 1) + self.register_rom(self.firmware_rom.bus, bios_size) + elif boot_source == "spi_rom": bios_size = 0x8000 kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size @@ -383,9 +444,11 @@ class BaseSoC(SoCCore): else: raise ValueError("unrecognized boot_source: {}".format(boot_source)) - # Add SPI Flash module, based on PicoSoC + # Add a simple bit-banged SPI Flash module spi_pads = platform.request("spiflash") - self.submodules.picospi = PicoSoCSpi(platform, spi_pads) + self.submodules.bbspi = BBSpi(platform, spi_pads) + + self.submodules.reboot = SBWarmBoot() # Add USB pads usb_pads = platform.request("usb") @@ -394,50 +457,127 @@ class BaseSoC(SoCCore): # self.submodules.usb = epmem.MemInterface(usb_iobuf) # self.submodules.usb = unififo.UsbUniFifo(usb_iobuf) + # Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command. + # The "-reult" adds an additional LUT pass to pack more stuff in, + # and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a + # Clock Enable signal for a LUT that has fewer than 4 flip-flops. + # This increases density, and lets us use the FPGA more efficiently. + platform.toolchain.nextpnr_yosys_template[2] += " -dsp -relut -dffe_min_ce_use 5" + # Disable final deep-sleep power down so firmware words are loaded # onto softcore's address bus. platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin" platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin" + # # Add a "Multiboot" variant + # platform.toolchain.nextpnr_build_template[3] = "icepack -s {build_name}.txt {build_name}-multi.bin" + +def make_multiboot_header(filename, boot_offsets=[128]): + """ + ICE40 allows you to program the SB_WARMBOOT state machine by adding the following + values to the bitstream, before any given image: + + [7e aa 99 7e] Sync Header + [92 00 k0] Boot mode (k = 1 for cold boot, 0 for warmboot) + [44 03 o1 o2 o3] Boot address + [82 00 00] Bank offset + [01 08] Reboot + + Note that in ICE40, the second nybble indicates the number of remaining bytes + (with the exception of the sync header) + """ + with open(filename, 'wb') as output: + for offset in boot_offsets: + # Sync Header + output.write(bytes([0x7e, 0xaa, 0x99, 0x7e])) + + # Boot mode + output.write(bytes([0x92, 0x00, 0x00])) + + # Boot address + output.write(bytes([0x44, 0x03, + (offset >> 16) & 0xff, + (offset >> 8) & 0xff, + (offset >> 0) & 0xff])) + + # Bank offset + output.write(bytes([0x82, 0x00, 0x00])) + + # Reboot command + output.write(bytes([0x01, 0x08])) + + for x in range(17, 32): + output.write(bytes([0])) + def main(): + # make_multiboot_header("multiboot", [128, 262144, 524288, 524288*2]) + # import sys + # sys.exit(0) platform = Platform() parser = argparse.ArgumentParser( - description="Build Fomu Main Gateware", - add_help=False) + description="Build Fomu Main Gateware") parser.add_argument( - "--bios", help="use bios as boot source", action="store_true" + "--boot-source", choices=["spi", "rand", "bios"], default="rand" ) parser.add_argument( - "--rand", help="use random data as boot source", action="store_false" - ) - parser.add_argument( - "--spi", help="boot from spi", action="store_true" + "--bios", help="use specified file as a BIOS, rather than building one" ) parser.add_argument( "--with-debug", help="enable debug support", action="store_true" ) - (args, rest) = parser.parse_known_args() + parser.add_argument( + "--no-pll", help="disable pll (possibly improving timing)", action="store_false" + ) + parser.add_argument( + "--export-random-rom-file", help="Generate a random ROM file and save it to a file" + ) + args = parser.parse_args() - debug = False - cpu_variant = "min" - if args.rand: - boot_source="random_rom" - compile_software=False - elif args.bios: - boot_source="bios_rom" - compile_software=True - elif args.spi: + if args.export_random_rom_file is not None: + size = 0x2000 + def xorshift32(x): + x = x ^ (x << 13) & 0xffffffff + x = x ^ (x >> 17) & 0xffffffff + x = x ^ (x << 5) & 0xffffffff + return x & 0xffffffff + + def get_rand(x): + out = 0 + for i in range(32): + x = xorshift32(x) + if (x & 1) == 1: + out = out | (1 << i) + return out & 0xffffffff + seed = 1 + with open(args.export_random_rom_file, "w", newline="\n") as output: + for d in range(int(size / 4)): + seed = get_rand(seed) + print("{:08x}".format(seed), file=output) + return 0 + + bios_file = None + compile_software = False + if args.boot_source == "rand": + boot_source = "random_rom" + elif args.boot_source == "bios": + boot_source = "bios_rom" + if args.bios is not None: + bios_file = args.bios + else: + compile_software = True + elif args.boot_source == "spi": boot_source = "spi_rom" - compile_software = False + + cpu_variant = "min" + debug = False if args.with_debug: cpu_variant = "debug" debug = True - else: - cpu_variant = "min" - debug = False - soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant, debug=debug, boot_source=boot_source) + soc = BaseSoC(platform, cpu_type="vexriscv", cpu_variant=cpu_variant, + debug=debug, boot_source=boot_source, + bios_file=bios_file, use_pll=not args.no_pll) builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv", compile_software=compile_software) vns = builder.build() soc.do_exit(vns)