From 3df59a866dd317a02df6e29bc0e637e66f5a6bb0 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Tue, 5 Mar 2019 20:28:54 +0800 Subject: [PATCH] metastable fix: wip Trying to figure out what's causing this problem. Signed-off-by: Sean Cross --- hw/crc5-test.c | 48 ++- hw/deps/valentyusb | 2 +- hw/foboot-bitstream.py | 85 ++-- sw/include/generated/csr.h | 778 +++++++++++++++++-------------------- sw/include/generated/mem.h | 20 +- sw/ld/output_format.ld | 2 +- sw/ld/regions.ld | 8 +- sw/src/main.c | 9 + sw/src/usb-rawfifo.c | 116 ------ sw/src/usb-unififo.c | 6 +- 10 files changed, 477 insertions(+), 597 deletions(-) delete mode 100644 sw/src/usb-rawfifo.c diff --git a/hw/crc5-test.c b/hw/crc5-test.c index 9d57cfb..3a0cba8 100644 --- a/hw/crc5-test.c +++ b/hw/crc5-test.c @@ -100,14 +100,17 @@ static uint16_t make_token(uint16_t data) { return (reverse_byte(val >> 8) << 8) | reverse_byte(val); } -int do_crc5(uint16_t pkt) { +int do_crc5(uint8_t bfr[2]) { uint8_t pkt_flipped[2] = { - reverse_byte(pkt >> 8), - reverse_byte(pkt), + reverse_byte(bfr[0]), + reverse_byte(bfr[1]), }; uint32_t data = (pkt_flipped[1] >> 5) | (pkt_flipped[0] << 3); uint32_t data_flipped; uint8_t crc; + uint16_t pkt; + ((uint8_t *)&pkt)[0] = bfr[1]; + ((uint8_t *)&pkt)[1] = bfr[0]; uint8_t found_crc = (pkt >> 3) & 0x1f; data_flipped = reverse_sof(data); @@ -131,24 +134,29 @@ int do_crc5(uint16_t pkt) { #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*x)) int main(int argc, char **argv) { - uint32_t check_bytes[] = { - /* - 0xff3c, - 0x12c5, - 0xe17e, - 0x19f5, - 0x0225, - 0x0165, - 0x009d, - 0x102f, - make_token(1013), - make_token(1429), - make_token(100), - */ - 0x82bc, - make_token(0x0483),//0x5fde, - 0x843c, + // uint32_t check_bytes[] = { + // /* + // 0xff3c, + // 0x12c5, + // 0xe17e, + // 0x19f5, + // 0x0225, + // 0x0165, + // 0x009d, + // 0x102f, + // make_token(1013), + // make_token(1429), + // make_token(100), + // */ + // 0x82bc, + // make_token(0x0483),//0x5fde, + // 0x843c, + // }; + uint8_t check_bytes[][2] = { + {0x82, 0xbc}, + {0x83, 0x44}, + {0x84, 0x3c}, }; unsigned int i; diff --git a/hw/deps/valentyusb b/hw/deps/valentyusb index ac9a522..f470661 160000 --- a/hw/deps/valentyusb +++ b/hw/deps/valentyusb @@ -1 +1 @@ -Subproject commit ac9a522847a116c842c8f7f795e587ff3d0d0dbb +Subproject commit f47066124207b43d38cb0e6bffacedd8fb0f523e diff --git a/hw/foboot-bitstream.py b/hw/foboot-bitstream.py index e7aa9f4..376a35d 100755 --- a/hw/foboot-bitstream.py +++ b/hw/foboot-bitstream.py @@ -42,12 +42,24 @@ _io = [ Subsignal("pullup", Pins("35")), IOStandard("LVCMOS33") ), + ("pmoda", 0, + Subsignal("p1", Pins("28"), IOStandard("LVCMOS33")), + Subsignal("p2", Pins("27"), IOStandard("LVCMOS33")), + Subsignal("p3", Pins("26"), IOStandard("LVCMOS33")), + Subsignal("p4", Pins("23"), IOStandard("LVCMOS33")), + ), + ("pmodb", 0, + Subsignal("p1", Pins("48"), IOStandard("LVCMOS33")), + Subsignal("p2", Pins("47"), IOStandard("LVCMOS33")), + Subsignal("p3", Pins("46"), IOStandard("LVCMOS33")), + Subsignal("p4", Pins("45"), IOStandard("LVCMOS33")), + ), ("spiflash", 0, - Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), - Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), - Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")), - Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")), - Subsignal("wp", Pins("18"), IOStandard("LVCMOS33")), + Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")), + Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")), + Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")), + Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")), + Subsignal("wp", Pins("18"), IOStandard("LVCMOS33")), Subsignal("hold", Pins("19"), IOStandard("LVCMOS33")), ), ("spiflash4x", 0, @@ -62,7 +74,14 @@ _connectors = [] class _CRG(Module): def __init__(self, platform): + clk48_raw = platform.request("clk48") + clk48 = Signal() clk12 = Signal() + + # Divide clk48 down to clk12, to ensure they're synchronized. + # By doing this, we avoid needing clock-domain crossing. + clk12_counter = Signal(2) + # # "0b00" Sets 48MHz HFOSC output # # "0b01" Sets 24MHz HFOSC output. # # "0b10" Sets 12MHz HFOSC output. @@ -77,10 +96,14 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + + platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) + platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6) + platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6) + self.reset = Signal() - # FIXME: Use PLL, increase system clock to 32 MHz, pending nextpnr - # fixes. self.comb += self.cd_sys.clk.eq(clk12) self.comb += self.cd_usb_12.clk.eq(clk12) @@ -94,16 +117,25 @@ class _CRG(Module): self.cd_usb_12.rst.eq(reset_delay != 0) ] - # Divide clk48 down to clk12, to ensure they're synchronized. - clk12_counter = Signal(2) + # self.specials += Instance( + # "SB_GB", + # i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_counter[1], + # o_GLOBAL_BUFFER_OUTPUT=clk12, + # ) + self.specials += Instance( + "SB_GB", + i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw, + o_GLOBAL_BUFFER_OUTPUT=clk48, + ) + + self.comb += [ + self.cd_usb_48.clk.eq(clk48), + ] + self.sync.usb_48 += [ clk12_counter.eq(clk12_counter + 1), ] - self.specials += Instance( - "SB_GB", - i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_counter[1], - o_GLOBAL_BUFFER_OUTPUT=clk12, - ) + self.comb += clk12.eq(clk12_counter[1]) self.sync.por += \ If(reset_delay != 0, @@ -111,12 +143,6 @@ class _CRG(Module): ) self.specials += AsyncResetSynchronizer(self.cd_por, self.reset) - self.clock_domains.cd_usb_48 = ClockDomain() - platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) - self.comb += [ - self.cd_usb_48.clk.eq(platform.request("clk48")), - ] - class RandomFirmwareROM(wishbone.SRAM): """ Seed the random data with a fixed number, so different bitstreams @@ -183,8 +209,6 @@ class BaseSoC(SoCCore): clk_freq = int(12e6) self.submodules.crg = _CRG(platform) - platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq) - platform.add_period_constraint(self.crg.cd_usb_12.clk, 1e9/clk_freq) SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, **kwargs) @@ -218,12 +242,23 @@ class BaseSoC(SoCCore): else: raise ValueError("unrecognized boot_source: {}".format(boot_source)) + pmoda = platform.request("pmoda") + pmodb = platform.request("pmodb") + # Add USB pads usb_pads = platform.request("usb") - usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup) - self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, endpoints=[EndpointType.BIDIR]) + usb_iobuf = usbio.IoBuf(pmoda.p4, pmodb.p4, usb_pads.pullup) + # self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, endpoints=[EndpointType.BIDIR]) # self.submodules.usb = epmem.MemInterface(usb_iobuf) - # self.submodules.usb = unififo.UsbUniFifo(usb_iobuf) + self.submodules.usb = unififo.UsbUniFifo(usb_iobuf) + + self.comb += [ + pmoda.p1.eq(self.crg.cd_usb_48.clk), + pmodb.p1.eq(self.crg.cd_usb_12.clk), + pmodb.p2.eq(self.usb.tx.i_bit_strobe), + pmoda.p2.eq(self.usb.tx.fit_dat), + pmodb.p3.eq(self.usb.tx.fit_oe), + ] # Disable final deep-sleep power down so firmware words are loaded # onto softcore's address bus. diff --git a/sw/include/generated/csr.h b/sw/include/generated/csr.h index ba0aa77..d708825 100644 --- a/sw/include/generated/csr.h +++ b/sw/include/generated/csr.h @@ -1,419 +1,359 @@ -#ifndef __GENERATED_CSR_H -#define __GENERATED_CSR_H -#include -#ifdef CSR_ACCESSORS_DEFINED -extern void csr_writeb(uint8_t value, uint32_t addr); -extern uint8_t csr_readb(uint32_t addr); -extern void csr_writew(uint16_t value, uint32_t addr); -extern uint16_t csr_readw(uint32_t addr); -extern void csr_writel(uint32_t value, uint32_t addr); -extern uint32_t csr_readl(uint32_t addr); -#else /* ! CSR_ACCESSORS_DEFINED */ -#include -#endif /* ! CSR_ACCESSORS_DEFINED */ - -/* ctrl */ -#define CSR_CTRL_BASE 0xe0000000 -#define CSR_CTRL_RESET_ADDR 0xe0000000 -#define CSR_CTRL_RESET_SIZE 1 -static inline unsigned char ctrl_reset_read(void) { - unsigned char r = csr_readl(0xe0000000); - return r; -} -static inline void ctrl_reset_write(unsigned char value) { - csr_writel(value, 0xe0000000); -} -#define CSR_CTRL_SCRATCH_ADDR 0xe0000004 -#define CSR_CTRL_SCRATCH_SIZE 4 -static inline unsigned int ctrl_scratch_read(void) { - unsigned int r = csr_readl(0xe0000004); - r <<= 8; - r |= csr_readl(0xe0000008); - r <<= 8; - r |= csr_readl(0xe000000c); - r <<= 8; - r |= csr_readl(0xe0000010); - return r; -} -static inline void ctrl_scratch_write(unsigned int value) { - csr_writel(value >> 24, 0xe0000004); - csr_writel(value >> 16, 0xe0000008); - csr_writel(value >> 8, 0xe000000c); - csr_writel(value, 0xe0000010); -} -#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014 -#define CSR_CTRL_BUS_ERRORS_SIZE 4 -static inline unsigned int ctrl_bus_errors_read(void) { - unsigned int r = csr_readl(0xe0000014); - r <<= 8; - r |= csr_readl(0xe0000018); - r <<= 8; - r |= csr_readl(0xe000001c); - r <<= 8; - r |= csr_readl(0xe0000020); - return r; -} - -/* timer0 */ -#define CSR_TIMER0_BASE 0xe0002800 -#define CSR_TIMER0_LOAD_ADDR 0xe0002800 -#define CSR_TIMER0_LOAD_SIZE 4 -static inline unsigned int timer0_load_read(void) { - unsigned int r = csr_readl(0xe0002800); - r <<= 8; - r |= csr_readl(0xe0002804); - r <<= 8; - r |= csr_readl(0xe0002808); - r <<= 8; - r |= csr_readl(0xe000280c); - return r; -} -static inline void timer0_load_write(unsigned int value) { - csr_writel(value >> 24, 0xe0002800); - csr_writel(value >> 16, 0xe0002804); - csr_writel(value >> 8, 0xe0002808); - csr_writel(value, 0xe000280c); -} -#define CSR_TIMER0_RELOAD_ADDR 0xe0002810 -#define CSR_TIMER0_RELOAD_SIZE 4 -static inline unsigned int timer0_reload_read(void) { - unsigned int r = csr_readl(0xe0002810); - r <<= 8; - r |= csr_readl(0xe0002814); - r <<= 8; - r |= csr_readl(0xe0002818); - r <<= 8; - r |= csr_readl(0xe000281c); - return r; -} -static inline void timer0_reload_write(unsigned int value) { - csr_writel(value >> 24, 0xe0002810); - csr_writel(value >> 16, 0xe0002814); - csr_writel(value >> 8, 0xe0002818); - csr_writel(value, 0xe000281c); -} -#define CSR_TIMER0_EN_ADDR 0xe0002820 -#define CSR_TIMER0_EN_SIZE 1 -static inline unsigned char timer0_en_read(void) { - unsigned char r = csr_readl(0xe0002820); - return r; -} -static inline void timer0_en_write(unsigned char value) { - csr_writel(value, 0xe0002820); -} -#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824 -#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 -static inline unsigned char timer0_update_value_read(void) { - unsigned char r = csr_readl(0xe0002824); - return r; -} -static inline void timer0_update_value_write(unsigned char value) { - csr_writel(value, 0xe0002824); -} -#define CSR_TIMER0_VALUE_ADDR 0xe0002828 -#define CSR_TIMER0_VALUE_SIZE 4 -static inline unsigned int timer0_value_read(void) { - unsigned int r = csr_readl(0xe0002828); - r <<= 8; - r |= csr_readl(0xe000282c); - r <<= 8; - r |= csr_readl(0xe0002830); - r <<= 8; - r |= csr_readl(0xe0002834); - return r; -} -#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838 -#define CSR_TIMER0_EV_STATUS_SIZE 1 -static inline unsigned char timer0_ev_status_read(void) { - unsigned char r = csr_readl(0xe0002838); - return r; -} -static inline void timer0_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0002838); -} -#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283c -#define CSR_TIMER0_EV_PENDING_SIZE 1 -static inline unsigned char timer0_ev_pending_read(void) { - unsigned char r = csr_readl(0xe000283c); - return r; -} -static inline void timer0_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe000283c); -} -#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840 -#define CSR_TIMER0_EV_ENABLE_SIZE 1 -static inline unsigned char timer0_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0002840); - return r; -} -static inline void timer0_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0002840); -} - -/* uart */ -#define CSR_UART_BASE 0xe0001800 -#define CSR_UART_RXTX_ADDR 0xe0001800 -#define CSR_UART_RXTX_SIZE 1 -static inline unsigned char uart_rxtx_read(void) { - unsigned char r = csr_readl(0xe0001800); - return r; -} -static inline void uart_rxtx_write(unsigned char value) { - csr_writel(value, 0xe0001800); -} -#define CSR_UART_TXFULL_ADDR 0xe0001804 -#define CSR_UART_TXFULL_SIZE 1 -static inline unsigned char uart_txfull_read(void) { - unsigned char r = csr_readl(0xe0001804); - return r; -} -#define CSR_UART_RXEMPTY_ADDR 0xe0001808 -#define CSR_UART_RXEMPTY_SIZE 1 -static inline unsigned char uart_rxempty_read(void) { - unsigned char r = csr_readl(0xe0001808); - return r; -} -#define CSR_UART_EV_STATUS_ADDR 0xe000180c -#define CSR_UART_EV_STATUS_SIZE 1 -static inline unsigned char uart_ev_status_read(void) { - unsigned char r = csr_readl(0xe000180c); - return r; -} -static inline void uart_ev_status_write(unsigned char value) { - csr_writel(value, 0xe000180c); -} -#define CSR_UART_EV_PENDING_ADDR 0xe0001810 -#define CSR_UART_EV_PENDING_SIZE 1 -static inline unsigned char uart_ev_pending_read(void) { - unsigned char r = csr_readl(0xe0001810); - return r; -} -static inline void uart_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe0001810); -} -#define CSR_UART_EV_ENABLE_ADDR 0xe0001814 -#define CSR_UART_EV_ENABLE_SIZE 1 -static inline unsigned char uart_ev_enable_read(void) { - unsigned char r = csr_readl(0xe0001814); - return r; -} -static inline void uart_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe0001814); -} - -/* uart_phy */ -#define CSR_UART_PHY_BASE 0xe0001000 -#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0001000 -#define CSR_UART_PHY_TUNING_WORD_SIZE 4 -static inline unsigned int uart_phy_tuning_word_read(void) { - unsigned int r = csr_readl(0xe0001000); - r <<= 8; - r |= csr_readl(0xe0001004); - r <<= 8; - r |= csr_readl(0xe0001008); - r <<= 8; - r |= csr_readl(0xe000100c); - return r; -} -static inline void uart_phy_tuning_word_write(unsigned int value) { - csr_writel(value >> 24, 0xe0001000); - csr_writel(value >> 16, 0xe0001004); - csr_writel(value >> 8, 0xe0001008); - csr_writel(value, 0xe000100c); -} - -/* usb */ -#define CSR_USB_BASE 0xe0004800 -#define CSR_USB_PULLUP_OUT_ADDR 0xe0004800 -#define CSR_USB_PULLUP_OUT_SIZE 1 -static inline unsigned char usb_pullup_out_read(void) { - unsigned char r = csr_readl(0xe0004800); - return r; -} -static inline void usb_pullup_out_write(unsigned char value) { - csr_writel(value, 0xe0004800); -} -#define CSR_USB_EP_0_OUT_EV_STATUS_ADDR 0xe0004804 -#define CSR_USB_EP_0_OUT_EV_STATUS_SIZE 1 -static inline unsigned char usb_ep_0_out_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004804); - return r; -} -static inline void usb_ep_0_out_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004804); -} -#define CSR_USB_EP_0_OUT_EV_PENDING_ADDR 0xe0004808 -#define CSR_USB_EP_0_OUT_EV_PENDING_SIZE 1 -static inline unsigned char usb_ep_0_out_ev_pending_read(void) { - unsigned char r = csr_readl(0xe0004808); - return r; -} -static inline void usb_ep_0_out_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe0004808); -} -#define CSR_USB_EP_0_OUT_EV_ENABLE_ADDR 0xe000480c -#define CSR_USB_EP_0_OUT_EV_ENABLE_SIZE 1 -static inline unsigned char usb_ep_0_out_ev_enable_read(void) { - unsigned char r = csr_readl(0xe000480c); - return r; -} -static inline void usb_ep_0_out_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe000480c); -} -#define CSR_USB_EP_0_OUT_LAST_TOK_ADDR 0xe0004810 -#define CSR_USB_EP_0_OUT_LAST_TOK_SIZE 1 -static inline unsigned char usb_ep_0_out_last_tok_read(void) { - unsigned char r = csr_readl(0xe0004810); - return r; -} -#define CSR_USB_EP_0_OUT_RESPOND_ADDR 0xe0004814 -#define CSR_USB_EP_0_OUT_RESPOND_SIZE 1 -static inline unsigned char usb_ep_0_out_respond_read(void) { - unsigned char r = csr_readl(0xe0004814); - return r; -} -static inline void usb_ep_0_out_respond_write(unsigned char value) { - csr_writel(value, 0xe0004814); -} -#define CSR_USB_EP_0_OUT_DTB_ADDR 0xe0004818 -#define CSR_USB_EP_0_OUT_DTB_SIZE 1 -static inline unsigned char usb_ep_0_out_dtb_read(void) { - unsigned char r = csr_readl(0xe0004818); - return r; -} -static inline void usb_ep_0_out_dtb_write(unsigned char value) { - csr_writel(value, 0xe0004818); -} -#define CSR_USB_EP_0_OUT_OBUF_HEAD_ADDR 0xe000481c -#define CSR_USB_EP_0_OUT_OBUF_HEAD_SIZE 1 -static inline unsigned char usb_ep_0_out_obuf_head_read(void) { - unsigned char r = csr_readl(0xe000481c); - return r; -} -static inline void usb_ep_0_out_obuf_head_write(unsigned char value) { - csr_writel(value, 0xe000481c); -} -#define CSR_USB_EP_0_OUT_OBUF_EMPTY_ADDR 0xe0004820 -#define CSR_USB_EP_0_OUT_OBUF_EMPTY_SIZE 1 -static inline unsigned char usb_ep_0_out_obuf_empty_read(void) { - unsigned char r = csr_readl(0xe0004820); - return r; -} -#define CSR_USB_EP_0_IN_EV_STATUS_ADDR 0xe0004824 -#define CSR_USB_EP_0_IN_EV_STATUS_SIZE 1 -static inline unsigned char usb_ep_0_in_ev_status_read(void) { - unsigned char r = csr_readl(0xe0004824); - return r; -} -static inline void usb_ep_0_in_ev_status_write(unsigned char value) { - csr_writel(value, 0xe0004824); -} -#define CSR_USB_EP_0_IN_EV_PENDING_ADDR 0xe0004828 -#define CSR_USB_EP_0_IN_EV_PENDING_SIZE 1 -static inline unsigned char usb_ep_0_in_ev_pending_read(void) { - unsigned char r = csr_readl(0xe0004828); - return r; -} -static inline void usb_ep_0_in_ev_pending_write(unsigned char value) { - csr_writel(value, 0xe0004828); -} -#define CSR_USB_EP_0_IN_EV_ENABLE_ADDR 0xe000482c -#define CSR_USB_EP_0_IN_EV_ENABLE_SIZE 1 -static inline unsigned char usb_ep_0_in_ev_enable_read(void) { - unsigned char r = csr_readl(0xe000482c); - return r; -} -static inline void usb_ep_0_in_ev_enable_write(unsigned char value) { - csr_writel(value, 0xe000482c); -} -#define CSR_USB_EP_0_IN_LAST_TOK_ADDR 0xe0004830 -#define CSR_USB_EP_0_IN_LAST_TOK_SIZE 1 -static inline unsigned char usb_ep_0_in_last_tok_read(void) { - unsigned char r = csr_readl(0xe0004830); - return r; -} -#define CSR_USB_EP_0_IN_RESPOND_ADDR 0xe0004834 -#define CSR_USB_EP_0_IN_RESPOND_SIZE 1 -static inline unsigned char usb_ep_0_in_respond_read(void) { - unsigned char r = csr_readl(0xe0004834); - return r; -} -static inline void usb_ep_0_in_respond_write(unsigned char value) { - csr_writel(value, 0xe0004834); -} -#define CSR_USB_EP_0_IN_DTB_ADDR 0xe0004838 -#define CSR_USB_EP_0_IN_DTB_SIZE 1 -static inline unsigned char usb_ep_0_in_dtb_read(void) { - unsigned char r = csr_readl(0xe0004838); - return r; -} -static inline void usb_ep_0_in_dtb_write(unsigned char value) { - csr_writel(value, 0xe0004838); -} -#define CSR_USB_EP_0_IN_IBUF_HEAD_ADDR 0xe000483c -#define CSR_USB_EP_0_IN_IBUF_HEAD_SIZE 1 -static inline unsigned char usb_ep_0_in_ibuf_head_read(void) { - unsigned char r = csr_readl(0xe000483c); - return r; -} -static inline void usb_ep_0_in_ibuf_head_write(unsigned char value) { - csr_writel(value, 0xe000483c); -} -#define CSR_USB_EP_0_IN_IBUF_EMPTY_ADDR 0xe0004840 -#define CSR_USB_EP_0_IN_IBUF_EMPTY_SIZE 1 -static inline unsigned char usb_ep_0_in_ibuf_empty_read(void) { - unsigned char r = csr_readl(0xe0004840); - return r; -} - -/* constants */ -#define NMI_INTERRUPT 0 -static inline int nmi_interrupt_read(void) { - return 0; -} -#define TIMER0_INTERRUPT 1 -static inline int timer0_interrupt_read(void) { - return 1; -} -#define UART_INTERRUPT 2 -static inline int uart_interrupt_read(void) { - return 2; -} -#define USB_INTERRUPT 3 -static inline int usb_interrupt_read(void) { - return 3; -} -#define CSR_DATA_WIDTH 8 -static inline int csr_data_width_read(void) { - return 8; -} -#define SYSTEM_CLOCK_FREQUENCY 12000000 -static inline int system_clock_frequency_read(void) { - return 12000000; -} -#define ROM_DISABLE 1 -static inline int rom_disable_read(void) { - return 1; -} -#define CONFIG_CLOCK_FREQUENCY 12000000 -static inline int config_clock_frequency_read(void) { - return 12000000; -} -#define CONFIG_CPU_RESET_ADDR 0 -static inline int config_cpu_reset_addr_read(void) { - return 0; -} -#define CONFIG_CPU_TYPE "VEXRISCV" -static inline const char * config_cpu_type_read(void) { - return "VEXRISCV"; -} -#define CONFIG_CPU_VARIANT "VEXRISCV" -static inline const char * config_cpu_variant_read(void) { - return "VEXRISCV"; -} -#define CONFIG_CSR_DATA_WIDTH 8 -static inline int config_csr_data_width_read(void) { - return 8; -} - -#endif +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include +#ifdef CSR_ACCESSORS_DEFINED +extern void csr_writeb(uint8_t value, uint32_t addr); +extern uint8_t csr_readb(uint32_t addr); +extern void csr_writew(uint16_t value, uint32_t addr); +extern uint16_t csr_readw(uint32_t addr); +extern void csr_writel(uint32_t value, uint32_t addr); +extern uint32_t csr_readl(uint32_t addr); +#else /* ! CSR_ACCESSORS_DEFINED */ +#include +#endif /* ! CSR_ACCESSORS_DEFINED */ + +/* ctrl */ +#define CSR_CTRL_BASE 0xe0000000 +#define CSR_CTRL_RESET_ADDR 0xe0000000 +#define CSR_CTRL_RESET_SIZE 1 +static inline unsigned char ctrl_reset_read(void) { + unsigned char r = csr_readl(0xe0000000); + return r; +} +static inline void ctrl_reset_write(unsigned char value) { + csr_writel(value, 0xe0000000); +} +#define CSR_CTRL_SCRATCH_ADDR 0xe0000004 +#define CSR_CTRL_SCRATCH_SIZE 4 +static inline unsigned int ctrl_scratch_read(void) { + unsigned int r = csr_readl(0xe0000004); + r <<= 8; + r |= csr_readl(0xe0000008); + r <<= 8; + r |= csr_readl(0xe000000c); + r <<= 8; + r |= csr_readl(0xe0000010); + return r; +} +static inline void ctrl_scratch_write(unsigned int value) { + csr_writel(value >> 24, 0xe0000004); + csr_writel(value >> 16, 0xe0000008); + csr_writel(value >> 8, 0xe000000c); + csr_writel(value, 0xe0000010); +} +#define CSR_CTRL_BUS_ERRORS_ADDR 0xe0000014 +#define CSR_CTRL_BUS_ERRORS_SIZE 4 +static inline unsigned int ctrl_bus_errors_read(void) { + unsigned int r = csr_readl(0xe0000014); + r <<= 8; + r |= csr_readl(0xe0000018); + r <<= 8; + r |= csr_readl(0xe000001c); + r <<= 8; + r |= csr_readl(0xe0000020); + return r; +} + +/* timer0 */ +#define CSR_TIMER0_BASE 0xe0002800 +#define CSR_TIMER0_LOAD_ADDR 0xe0002800 +#define CSR_TIMER0_LOAD_SIZE 4 +static inline unsigned int timer0_load_read(void) { + unsigned int r = csr_readl(0xe0002800); + r <<= 8; + r |= csr_readl(0xe0002804); + r <<= 8; + r |= csr_readl(0xe0002808); + r <<= 8; + r |= csr_readl(0xe000280c); + return r; +} +static inline void timer0_load_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002800); + csr_writel(value >> 16, 0xe0002804); + csr_writel(value >> 8, 0xe0002808); + csr_writel(value, 0xe000280c); +} +#define CSR_TIMER0_RELOAD_ADDR 0xe0002810 +#define CSR_TIMER0_RELOAD_SIZE 4 +static inline unsigned int timer0_reload_read(void) { + unsigned int r = csr_readl(0xe0002810); + r <<= 8; + r |= csr_readl(0xe0002814); + r <<= 8; + r |= csr_readl(0xe0002818); + r <<= 8; + r |= csr_readl(0xe000281c); + return r; +} +static inline void timer0_reload_write(unsigned int value) { + csr_writel(value >> 24, 0xe0002810); + csr_writel(value >> 16, 0xe0002814); + csr_writel(value >> 8, 0xe0002818); + csr_writel(value, 0xe000281c); +} +#define CSR_TIMER0_EN_ADDR 0xe0002820 +#define CSR_TIMER0_EN_SIZE 1 +static inline unsigned char timer0_en_read(void) { + unsigned char r = csr_readl(0xe0002820); + return r; +} +static inline void timer0_en_write(unsigned char value) { + csr_writel(value, 0xe0002820); +} +#define CSR_TIMER0_UPDATE_VALUE_ADDR 0xe0002824 +#define CSR_TIMER0_UPDATE_VALUE_SIZE 1 +static inline unsigned char timer0_update_value_read(void) { + unsigned char r = csr_readl(0xe0002824); + return r; +} +static inline void timer0_update_value_write(unsigned char value) { + csr_writel(value, 0xe0002824); +} +#define CSR_TIMER0_VALUE_ADDR 0xe0002828 +#define CSR_TIMER0_VALUE_SIZE 4 +static inline unsigned int timer0_value_read(void) { + unsigned int r = csr_readl(0xe0002828); + r <<= 8; + r |= csr_readl(0xe000282c); + r <<= 8; + r |= csr_readl(0xe0002830); + r <<= 8; + r |= csr_readl(0xe0002834); + return r; +} +#define CSR_TIMER0_EV_STATUS_ADDR 0xe0002838 +#define CSR_TIMER0_EV_STATUS_SIZE 1 +static inline unsigned char timer0_ev_status_read(void) { + unsigned char r = csr_readl(0xe0002838); + return r; +} +static inline void timer0_ev_status_write(unsigned char value) { + csr_writel(value, 0xe0002838); +} +#define CSR_TIMER0_EV_PENDING_ADDR 0xe000283c +#define CSR_TIMER0_EV_PENDING_SIZE 1 +static inline unsigned char timer0_ev_pending_read(void) { + unsigned char r = csr_readl(0xe000283c); + return r; +} +static inline void timer0_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe000283c); +} +#define CSR_TIMER0_EV_ENABLE_ADDR 0xe0002840 +#define CSR_TIMER0_EV_ENABLE_SIZE 1 +static inline unsigned char timer0_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0002840); + return r; +} +static inline void timer0_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0002840); +} + +/* uart */ +#define CSR_UART_BASE 0xe0001800 +#define CSR_UART_RXTX_ADDR 0xe0001800 +#define CSR_UART_RXTX_SIZE 1 +static inline unsigned char uart_rxtx_read(void) { + unsigned char r = csr_readl(0xe0001800); + return r; +} +static inline void uart_rxtx_write(unsigned char value) { + csr_writel(value, 0xe0001800); +} +#define CSR_UART_TXFULL_ADDR 0xe0001804 +#define CSR_UART_TXFULL_SIZE 1 +static inline unsigned char uart_txfull_read(void) { + unsigned char r = csr_readl(0xe0001804); + return r; +} +#define CSR_UART_RXEMPTY_ADDR 0xe0001808 +#define CSR_UART_RXEMPTY_SIZE 1 +static inline unsigned char uart_rxempty_read(void) { + unsigned char r = csr_readl(0xe0001808); + return r; +} +#define CSR_UART_EV_STATUS_ADDR 0xe000180c +#define CSR_UART_EV_STATUS_SIZE 1 +static inline unsigned char uart_ev_status_read(void) { + unsigned char r = csr_readl(0xe000180c); + return r; +} +static inline void uart_ev_status_write(unsigned char value) { + csr_writel(value, 0xe000180c); +} +#define CSR_UART_EV_PENDING_ADDR 0xe0001810 +#define CSR_UART_EV_PENDING_SIZE 1 +static inline unsigned char uart_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0001810); + return r; +} +static inline void uart_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0001810); +} +#define CSR_UART_EV_ENABLE_ADDR 0xe0001814 +#define CSR_UART_EV_ENABLE_SIZE 1 +static inline unsigned char uart_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0001814); + return r; +} +static inline void uart_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0001814); +} + +/* uart_phy */ +#define CSR_UART_PHY_BASE 0xe0001000 +#define CSR_UART_PHY_TUNING_WORD_ADDR 0xe0001000 +#define CSR_UART_PHY_TUNING_WORD_SIZE 4 +static inline unsigned int uart_phy_tuning_word_read(void) { + unsigned int r = csr_readl(0xe0001000); + r <<= 8; + r |= csr_readl(0xe0001004); + r <<= 8; + r |= csr_readl(0xe0001008); + r <<= 8; + r |= csr_readl(0xe000100c); + return r; +} +static inline void uart_phy_tuning_word_write(unsigned int value) { + csr_writel(value >> 24, 0xe0001000); + csr_writel(value >> 16, 0xe0001004); + csr_writel(value >> 8, 0xe0001008); + csr_writel(value, 0xe000100c); +} + +/* usb */ +#define CSR_USB_BASE 0xe0004800 +#define CSR_USB_BYTE_COUNT_ADDR 0xe0004800 +#define CSR_USB_BYTE_COUNT_SIZE 1 +static inline unsigned char usb_byte_count_read(void) { + unsigned char r = csr_readl(0xe0004800); + return r; +} +#define CSR_USB_OBUF_HEAD_ADDR 0xe0004804 +#define CSR_USB_OBUF_HEAD_SIZE 1 +static inline unsigned char usb_obuf_head_read(void) { + unsigned char r = csr_readl(0xe0004804); + return r; +} +static inline void usb_obuf_head_write(unsigned char value) { + csr_writel(value, 0xe0004804); +} +#define CSR_USB_OBUF_EMPTY_ADDR 0xe0004808 +#define CSR_USB_OBUF_EMPTY_SIZE 1 +static inline unsigned char usb_obuf_empty_read(void) { + unsigned char r = csr_readl(0xe0004808); + return r; +} +#define CSR_USB_ARM_ADDR 0xe000480c +#define CSR_USB_ARM_SIZE 1 +static inline unsigned char usb_arm_read(void) { + unsigned char r = csr_readl(0xe000480c); + return r; +} +static inline void usb_arm_write(unsigned char value) { + csr_writel(value, 0xe000480c); +} +#define CSR_USB_IBUF_HEAD_ADDR 0xe0004810 +#define CSR_USB_IBUF_HEAD_SIZE 1 +static inline unsigned char usb_ibuf_head_read(void) { + unsigned char r = csr_readl(0xe0004810); + return r; +} +static inline void usb_ibuf_head_write(unsigned char value) { + csr_writel(value, 0xe0004810); +} +#define CSR_USB_IBUF_EMPTY_ADDR 0xe0004814 +#define CSR_USB_IBUF_EMPTY_SIZE 1 +static inline unsigned char usb_ibuf_empty_read(void) { + unsigned char r = csr_readl(0xe0004814); + return r; +} +#define CSR_USB_PULLUP_OUT_ADDR 0xe0004818 +#define CSR_USB_PULLUP_OUT_SIZE 1 +static inline unsigned char usb_pullup_out_read(void) { + unsigned char r = csr_readl(0xe0004818); + return r; +} +static inline void usb_pullup_out_write(unsigned char value) { + csr_writel(value, 0xe0004818); +} +#define CSR_USB_EV_STATUS_ADDR 0xe000481c +#define CSR_USB_EV_STATUS_SIZE 1 +static inline unsigned char usb_ev_status_read(void) { + unsigned char r = csr_readl(0xe000481c); + return r; +} +static inline void usb_ev_status_write(unsigned char value) { + csr_writel(value, 0xe000481c); +} +#define CSR_USB_EV_PENDING_ADDR 0xe0004820 +#define CSR_USB_EV_PENDING_SIZE 1 +static inline unsigned char usb_ev_pending_read(void) { + unsigned char r = csr_readl(0xe0004820); + return r; +} +static inline void usb_ev_pending_write(unsigned char value) { + csr_writel(value, 0xe0004820); +} +#define CSR_USB_EV_ENABLE_ADDR 0xe0004824 +#define CSR_USB_EV_ENABLE_SIZE 1 +static inline unsigned char usb_ev_enable_read(void) { + unsigned char r = csr_readl(0xe0004824); + return r; +} +static inline void usb_ev_enable_write(unsigned char value) { + csr_writel(value, 0xe0004824); +} + +/* constants */ +#define NMI_INTERRUPT 0 +static inline int nmi_interrupt_read(void) { + return 0; +} +#define TIMER0_INTERRUPT 1 +static inline int timer0_interrupt_read(void) { + return 1; +} +#define UART_INTERRUPT 2 +static inline int uart_interrupt_read(void) { + return 2; +} +#define USB_INTERRUPT 3 +static inline int usb_interrupt_read(void) { + return 3; +} +#define CSR_DATA_WIDTH 8 +static inline int csr_data_width_read(void) { + return 8; +} +#define SYSTEM_CLOCK_FREQUENCY 12000000 +static inline int system_clock_frequency_read(void) { + return 12000000; +} +#define ROM_DISABLE 1 +static inline int rom_disable_read(void) { + return 1; +} +#define CONFIG_CLOCK_FREQUENCY 12000000 +static inline int config_clock_frequency_read(void) { + return 12000000; +} +#define CONFIG_CPU_RESET_ADDR 0 +static inline int config_cpu_reset_addr_read(void) { + return 0; +} +#define CONFIG_CPU_TYPE "VEXRISCV" +static inline const char * config_cpu_type_read(void) { + return "VEXRISCV"; +} +#define CONFIG_CPU_VARIANT "VEXRISCV" +static inline const char * config_cpu_variant_read(void) { + return "VEXRISCV"; +} +#define CONFIG_CSR_DATA_WIDTH 8 +static inline int config_csr_data_width_read(void) { + return 8; +} + +#endif diff --git a/sw/include/generated/mem.h b/sw/include/generated/mem.h index ca46e9f..1e2c605 100644 --- a/sw/include/generated/mem.h +++ b/sw/include/generated/mem.h @@ -1,10 +1,10 @@ -#ifndef __GENERATED_MEM_H -#define __GENERATED_MEM_H - -#define SRAM_BASE 0x10000000 -#define SRAM_SIZE 0x00020000 - -#define ROM_BASE 0x00000000 -#define ROM_SIZE 0x00002000 - -#endif +#ifndef __GENERATED_MEM_H +#define __GENERATED_MEM_H + +#define SRAM_BASE 0x10000000 +#define SRAM_SIZE 0x00020000 + +#define ROM_BASE 0x00000000 +#define ROM_SIZE 0x00002000 + +#endif diff --git a/sw/ld/output_format.ld b/sw/ld/output_format.ld index 5e76f5f..269cd64 100644 --- a/sw/ld/output_format.ld +++ b/sw/ld/output_format.ld @@ -1 +1 @@ -OUTPUT_FORMAT("elf32-littleriscv") +OUTPUT_FORMAT("elf32-littleriscv") diff --git a/sw/ld/regions.ld b/sw/ld/regions.ld index 605e8f9..6fcb9c8 100644 --- a/sw/ld/regions.ld +++ b/sw/ld/regions.ld @@ -1,4 +1,4 @@ -MEMORY { - sram : ORIGIN = 0x10000000, LENGTH = 0x00020000 - rom : ORIGIN = 0x00000000, LENGTH = 0x00002000 -} +MEMORY { + sram : ORIGIN = 0x10000000, LENGTH = 0x00020000 + rom : ORIGIN = 0x00000000, LENGTH = 0x00002000 +} diff --git a/sw/src/main.c b/sw/src/main.c index fdfb971..86ac993 100644 --- a/sw/src/main.c +++ b/sw/src/main.c @@ -73,6 +73,7 @@ int main(int argc, char **argv) printf("USB enabled, waiting for packet...\n"); // usb_print_status(); int last = 0; + static uint8_t bfr[12]; while (1) { if (usb_irq_happened() != last) { @@ -80,6 +81,14 @@ int main(int argc, char **argv) printf("USB %d IRQ happened\n", last); } usb_poll(); + printf("Press any key to send... "); + uart_read(); + printf("Sending... "); + bfr[0] = ~0; + bfr[1] = 0; + bfr[2] = 0; + usb_send(NULL, 0, bfr, 3); + printf("Sent\n"); } return 0; } \ No newline at end of file diff --git a/sw/src/usb-rawfifo.c b/sw/src/usb-rawfifo.c deleted file mode 100644 index 96393b8..0000000 --- a/sw/src/usb-rawfifo.c +++ /dev/null @@ -1,116 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#ifdef CSR_USB_OBUF_EMPTY_ADDR - -static inline unsigned char usb_obuf_head_read(void); -static inline void usb_obuf_head_write(unsigned char value); - -static inline unsigned char usb_obuf_empty_read(void); - -static inline unsigned char usb_arm_read(void); -static inline void usb_arm_write(unsigned char value); - -static inline unsigned char usb_ibuf_head_read(void); -static inline void usb_ibuf_head_write(unsigned char value); - -static inline unsigned char usb_ibuf_empty_read(void); - -static inline unsigned char usb_pullup_out_read(void); -static inline void usb_pullup_out_write(unsigned char value); - -static inline unsigned char usb_ev_status_read(void); -static inline void usb_ev_status_write(unsigned char value); - -static inline unsigned char usb_ev_pending_read(void); -static inline void usb_ev_pending_write(unsigned char value); - -static inline unsigned char usb_ev_enable_read(void); -static inline void usb_ev_enable_write(unsigned char value); - -static const char hex[] = "0123456789abcdef"; - -uint8_t usb_ep0out_wr_ptr; -uint8_t usb_ep0out_rd_ptr; -#define EP0OUT_BUFFERS 64 -static uint8_t usb_ep0out_buffer[EP0OUT_BUFFERS][128]; -void usb_print_status(void) -{ - static int loops; - loops++; - - while (usb_ep0out_rd_ptr != usb_ep0out_wr_ptr) { - uint8_t *obuf = usb_ep0out_buffer[usb_ep0out_rd_ptr]; - uint8_t cnt = obuf[0]; - unsigned int i; - if (cnt) { - for (i = 0; i < cnt; i++) { - uart_write(' '); - uart_write(hex[(obuf[i+1] >> 4) & 0xf]); - uart_write(hex[obuf[i+1] & (0xf)]); - // printf(" %02x", obufbuf[i]); - } - uart_write('\r'); - uart_write('\n'); - } - // printf("\n"); - usb_ep0out_rd_ptr = (usb_ep0out_rd_ptr + 1) & (EP0OUT_BUFFERS-1); - } - // if (!obe) { - // uint32_t obh = usb_obuf_head_read(); - // usb_obuf_head_write(1); - // if (i < 300) - // printf("i: %8d obe: %d obh: %02x\n", i, obe, obh); - // } -} - -int irq_happened; - -void usb_init(void) { - return; -} - -void usb_isr(void) { - uint8_t pending = usb_ev_pending_read(); - - // Advance the obuf head, which will reset the obuf_empty bit - if (pending & 1) { - int byte_count = 0; - uint8_t *obuf = usb_ep0out_buffer[usb_ep0out_wr_ptr]; - while (1) { - if (usb_obuf_empty_read()) - break; - obuf[++byte_count] = usb_obuf_head_read(); - usb_obuf_head_write(0); - } - usb_ev_pending_write(1); - obuf[0] = byte_count; - usb_ep0out_wr_ptr = (usb_ep0out_wr_ptr + 1) & (EP0OUT_BUFFERS-1); - } - - return; -} - -void usb_connect(void) { - usb_pullup_out_write(1); - - usb_ev_pending_write(usb_ev_pending_read()); - usb_ev_enable_write(0xff); - - irq_setmask(irq_getmask() | (1 << USB_INTERRUPT)); -} - -void usb_wait(void) { - while (!irq_happened) - ; -} - -int usb_irq_happened(void) { - return irq_happened; -} - -#endif /* CSR_USB_OBUF_EMPTY_ADDR */ \ No newline at end of file diff --git a/sw/src/usb-unififo.c b/sw/src/usb-unififo.c index 63c7238..ca23627 100644 --- a/sw/src/usb-unififo.c +++ b/sw/src/usb-unififo.c @@ -178,10 +178,14 @@ void usb_init(void) { int usb_send(struct usb_device *dev, int epnum, const void *data, int total_count) { unsigned int i; const uint8_t *data_bfr = data; + while (!usb_ibuf_empty_read()) + printf("."); + usb_arm_write(0); for (i = 0; i < total_count; i++) { + printf("Writing %02x ", data_bfr[i]); usb_ibuf_head_write(data_bfr[i]); } - usb_arm_write(0); + usb_arm_write(1); } void usb_isr(void) {