From 2139317530f881ef2994725f196cf8f8a2611f40 Mon Sep 17 00:00:00 2001
From: Sean Cross <sean@xobs.io>
Date: Wed, 20 Mar 2019 13:14:57 +0800
Subject: [PATCH] sw: include: sync csr.h and mem.h

Signed-off-by: Sean Cross <sean@xobs.io>
---
 sw/include/generated/csr.h | 90 ++++++++++++++++++++++++++++++++++++++
 sw/include/generated/mem.h |  3 ++
 2 files changed, 93 insertions(+)

diff --git a/sw/include/generated/csr.h b/sw/include/generated/csr.h
index 7a44d60..46fa44f 100644
--- a/sw/include/generated/csr.h
+++ b/sw/include/generated/csr.h
@@ -54,6 +54,96 @@ static inline unsigned int ctrl_bus_errors_read(void) {
 	return r;
 }
 
+/* spi */
+#define CSR_SPI_BASE 0xe0006000
+#define CSR_SPI_CONFIG_ADDR 0xe0006000
+#define CSR_SPI_CONFIG_SIZE 4
+static inline unsigned int spi_config_read(void) {
+	unsigned int r = csr_readl(0xe0006000);
+	r <<= 8;
+	r |= csr_readl(0xe0006004);
+	r <<= 8;
+	r |= csr_readl(0xe0006008);
+	r <<= 8;
+	r |= csr_readl(0xe000600c);
+	return r;
+}
+static inline void spi_config_write(unsigned int value) {
+	csr_writel(value >> 24, 0xe0006000);
+	csr_writel(value >> 16, 0xe0006004);
+	csr_writel(value >> 8, 0xe0006008);
+	csr_writel(value, 0xe000600c);
+}
+#define CSR_SPI_XFER_ADDR 0xe0006010
+#define CSR_SPI_XFER_SIZE 4
+static inline unsigned int spi_xfer_read(void) {
+	unsigned int r = csr_readl(0xe0006010);
+	r <<= 8;
+	r |= csr_readl(0xe0006014);
+	r <<= 8;
+	r |= csr_readl(0xe0006018);
+	r <<= 8;
+	r |= csr_readl(0xe000601c);
+	return r;
+}
+static inline void spi_xfer_write(unsigned int value) {
+	csr_writel(value >> 24, 0xe0006010);
+	csr_writel(value >> 16, 0xe0006014);
+	csr_writel(value >> 8, 0xe0006018);
+	csr_writel(value, 0xe000601c);
+}
+#define CSR_SPI_START_ADDR 0xe0006020
+#define CSR_SPI_START_SIZE 1
+static inline unsigned char spi_start_read(void) {
+	unsigned char r = csr_readl(0xe0006020);
+	return r;
+}
+static inline void spi_start_write(unsigned char value) {
+	csr_writel(value, 0xe0006020);
+}
+#define CSR_SPI_ACTIVE_ADDR 0xe0006024
+#define CSR_SPI_ACTIVE_SIZE 1
+static inline unsigned char spi_active_read(void) {
+	unsigned char r = csr_readl(0xe0006024);
+	return r;
+}
+#define CSR_SPI_PENDING_ADDR 0xe0006028
+#define CSR_SPI_PENDING_SIZE 1
+static inline unsigned char spi_pending_read(void) {
+	unsigned char r = csr_readl(0xe0006028);
+	return r;
+}
+#define CSR_SPI_MOSI_DATA_ADDR 0xe000602c
+#define CSR_SPI_MOSI_DATA_SIZE 4
+static inline unsigned int spi_mosi_data_read(void) {
+	unsigned int r = csr_readl(0xe000602c);
+	r <<= 8;
+	r |= csr_readl(0xe0006030);
+	r <<= 8;
+	r |= csr_readl(0xe0006034);
+	r <<= 8;
+	r |= csr_readl(0xe0006038);
+	return r;
+}
+static inline void spi_mosi_data_write(unsigned int value) {
+	csr_writel(value >> 24, 0xe000602c);
+	csr_writel(value >> 16, 0xe0006030);
+	csr_writel(value >> 8, 0xe0006034);
+	csr_writel(value, 0xe0006038);
+}
+#define CSR_SPI_MISO_DATA_ADDR 0xe000603c
+#define CSR_SPI_MISO_DATA_SIZE 4
+static inline unsigned int spi_miso_data_read(void) {
+	unsigned int r = csr_readl(0xe000603c);
+	r <<= 8;
+	r |= csr_readl(0xe0006040);
+	r <<= 8;
+	r |= csr_readl(0xe0006044);
+	r <<= 8;
+	r |= csr_readl(0xe0006048);
+	return r;
+}
+
 /* timer0 */
 #define CSR_TIMER0_BASE 0xe0002800
 #define CSR_TIMER0_LOAD_ADDR 0xe0002800
diff --git a/sw/include/generated/mem.h b/sw/include/generated/mem.h
index 1e2c605..880c8f6 100644
--- a/sw/include/generated/mem.h
+++ b/sw/include/generated/mem.h
@@ -1,6 +1,9 @@
 #ifndef __GENERATED_MEM_H
 #define __GENERATED_MEM_H
 
+#define VEXRISCV_DEBUG_BASE 0xf00f0000
+#define VEXRISCV_DEBUG_SIZE 0x00000010
+
 #define SRAM_BASE 0x10000000
 #define SRAM_SIZE 0x00020000