3395 lines
134 KiB
Coq
3395 lines
134 KiB
Coq
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// Generator : SpinalHDL v1.3.2 git head : 41815ceafff4e72c2e3a3e1ff7e9ada5202a0d26
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// Date : 29/03/2019, 05:39:18
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// Component : VexRiscv
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`define Src1CtrlEnum_defaultEncoding_type [1:0]
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`define Src1CtrlEnum_defaultEncoding_RS 2'b00
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`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
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`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
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`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
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`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
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`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
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`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
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`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
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`define AluBitwiseCtrlEnum_defaultEncoding_SRC1 2'b11
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`define ShiftCtrlEnum_defaultEncoding_type [1:0]
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`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
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`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
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`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
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`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
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`define BranchCtrlEnum_defaultEncoding_type [1:0]
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`define BranchCtrlEnum_defaultEncoding_INC 2'b00
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`define BranchCtrlEnum_defaultEncoding_B 2'b01
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`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
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`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
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`define EnvCtrlEnum_defaultEncoding_type [1:0]
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`define EnvCtrlEnum_defaultEncoding_NONE 2'b00
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`define EnvCtrlEnum_defaultEncoding_XRET 2'b01
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`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10
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`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11
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`define Src2CtrlEnum_defaultEncoding_type [1:0]
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`define Src2CtrlEnum_defaultEncoding_RS 2'b00
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`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
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`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
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`define Src2CtrlEnum_defaultEncoding_PC 2'b11
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`define AluCtrlEnum_defaultEncoding_type [1:0]
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`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
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`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
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`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
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module InstructionCache (
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input io_flush_cmd_valid,
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output io_flush_cmd_ready,
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output io_flush_rsp,
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input io_cpu_prefetch_isValid,
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output reg io_cpu_prefetch_haltIt,
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input [31:0] io_cpu_prefetch_pc,
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input io_cpu_fetch_isValid,
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input io_cpu_fetch_isStuck,
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input io_cpu_fetch_isRemoved,
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input [31:0] io_cpu_fetch_pc,
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output [31:0] io_cpu_fetch_data,
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input io_cpu_fetch_dataBypassValid,
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input [31:0] io_cpu_fetch_dataBypass,
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output io_cpu_fetch_mmuBus_cmd_isValid,
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output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress,
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output io_cpu_fetch_mmuBus_cmd_bypassTranslation,
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input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress,
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input io_cpu_fetch_mmuBus_rsp_isIoAccess,
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input io_cpu_fetch_mmuBus_rsp_allowRead,
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input io_cpu_fetch_mmuBus_rsp_allowWrite,
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input io_cpu_fetch_mmuBus_rsp_allowExecute,
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input io_cpu_fetch_mmuBus_rsp_allowUser,
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input io_cpu_fetch_mmuBus_rsp_miss,
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input io_cpu_fetch_mmuBus_rsp_hit,
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output io_cpu_fetch_mmuBus_end,
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output [31:0] io_cpu_fetch_physicalAddress,
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input io_cpu_decode_isValid,
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input io_cpu_decode_isStuck,
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input [31:0] io_cpu_decode_pc,
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output [31:0] io_cpu_decode_physicalAddress,
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output [31:0] io_cpu_decode_data,
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output io_cpu_decode_cacheMiss,
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output io_cpu_decode_error,
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output io_cpu_decode_mmuMiss,
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output io_cpu_decode_illegalAccess,
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input io_cpu_decode_isUser,
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input io_cpu_fill_valid,
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input [31:0] io_cpu_fill_payload,
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output io_mem_cmd_valid,
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input io_mem_cmd_ready,
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output [31:0] io_mem_cmd_payload_address,
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output [2:0] io_mem_cmd_payload_size,
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input io_mem_rsp_valid,
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input [31:0] io_mem_rsp_payload_data,
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input io_mem_rsp_payload_error,
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input clk,
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input reset);
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reg [23:0] _zz_12_;
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reg [31:0] _zz_13_;
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wire _zz_14_;
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wire [0:0] _zz_15_;
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wire [0:0] _zz_16_;
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wire [23:0] _zz_17_;
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reg _zz_1_;
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reg _zz_2_;
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reg lineLoader_fire;
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reg lineLoader_valid;
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reg [31:0] lineLoader_address;
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reg lineLoader_hadError;
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reg [5:0] lineLoader_flushCounter;
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reg _zz_3_;
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reg lineLoader_flushFromInterface;
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wire _zz_4_;
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reg _zz_4__regNext;
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reg lineLoader_cmdSent;
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reg lineLoader_wayToAllocate_willIncrement;
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wire lineLoader_wayToAllocate_willClear;
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wire lineLoader_wayToAllocate_willOverflowIfInc;
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wire lineLoader_wayToAllocate_willOverflow;
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reg [2:0] lineLoader_wordIndex;
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wire lineLoader_write_tag_0_valid;
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wire [4:0] lineLoader_write_tag_0_payload_address;
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wire lineLoader_write_tag_0_payload_data_valid;
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wire lineLoader_write_tag_0_payload_data_error;
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wire [21:0] lineLoader_write_tag_0_payload_data_address;
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wire lineLoader_write_data_0_valid;
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wire [7:0] lineLoader_write_data_0_payload_address;
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wire [31:0] lineLoader_write_data_0_payload_data;
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wire _zz_5_;
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wire [4:0] _zz_6_;
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wire _zz_7_;
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wire fetchStage_read_waysValues_0_tag_valid;
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wire fetchStage_read_waysValues_0_tag_error;
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wire [21:0] fetchStage_read_waysValues_0_tag_address;
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wire [23:0] _zz_8_;
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wire [7:0] _zz_9_;
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wire _zz_10_;
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wire [31:0] fetchStage_read_waysValues_0_data;
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reg [31:0] decodeStage_mmuRsp_physicalAddress;
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reg decodeStage_mmuRsp_isIoAccess;
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reg decodeStage_mmuRsp_allowRead;
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reg decodeStage_mmuRsp_allowWrite;
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reg decodeStage_mmuRsp_allowExecute;
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reg decodeStage_mmuRsp_allowUser;
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reg decodeStage_mmuRsp_miss;
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reg decodeStage_mmuRsp_hit;
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reg decodeStage_hit_tags_0_valid;
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reg decodeStage_hit_tags_0_error;
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reg [21:0] decodeStage_hit_tags_0_address;
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wire decodeStage_hit_hits_0;
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wire decodeStage_hit_valid;
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wire decodeStage_hit_error;
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reg [31:0] _zz_11_;
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wire [31:0] decodeStage_hit_data;
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reg [31:0] decodeStage_hit_word;
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reg io_cpu_fetch_dataBypassValid_regNextWhen;
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reg [31:0] io_cpu_fetch_dataBypass_regNextWhen;
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reg [23:0] ways_0_tags [0:31];
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reg [31:0] ways_0_datas [0:255];
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assign _zz_14_ = (! lineLoader_flushCounter[5]);
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assign _zz_15_ = _zz_8_[0 : 0];
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assign _zz_16_ = _zz_8_[1 : 1];
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assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
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always @ (posedge clk) begin
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if(_zz_2_) begin
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ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_;
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end
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end
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always @ (posedge clk) begin
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if(_zz_7_) begin
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_zz_12_ <= ways_0_tags[_zz_6_];
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end
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end
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always @ (posedge clk) begin
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if(_zz_1_) begin
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ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
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end
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end
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always @ (posedge clk) begin
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if(_zz_10_) begin
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_zz_13_ <= ways_0_datas[_zz_9_];
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end
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end
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always @ (*) begin
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_zz_1_ = 1'b0;
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if(lineLoader_write_data_0_valid)begin
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_zz_1_ = 1'b1;
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end
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end
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always @ (*) begin
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_zz_2_ = 1'b0;
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if(lineLoader_write_tag_0_valid)begin
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_zz_2_ = 1'b1;
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end
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end
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always @ (*) begin
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io_cpu_prefetch_haltIt = 1'b0;
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if(lineLoader_valid)begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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if(_zz_14_)begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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if((! _zz_3_))begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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if(io_flush_cmd_valid)begin
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io_cpu_prefetch_haltIt = 1'b1;
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end
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end
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always @ (*) begin
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lineLoader_fire = 1'b0;
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if(io_mem_rsp_valid)begin
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if((lineLoader_wordIndex == (3'b111)))begin
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lineLoader_fire = 1'b1;
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end
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end
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end
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assign io_flush_cmd_ready = (! (lineLoader_valid || io_cpu_fetch_isValid));
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assign _zz_4_ = lineLoader_flushCounter[5];
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assign io_flush_rsp = ((_zz_4_ && (! _zz_4__regNext)) && lineLoader_flushFromInterface);
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assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
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assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)};
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assign io_mem_cmd_payload_size = (3'b101);
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always @ (*) begin
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lineLoader_wayToAllocate_willIncrement = 1'b0;
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if(lineLoader_fire)begin
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lineLoader_wayToAllocate_willIncrement = 1'b1;
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end
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end
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assign lineLoader_wayToAllocate_willClear = 1'b0;
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assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
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assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
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assign _zz_5_ = 1'b1;
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assign lineLoader_write_tag_0_valid = ((_zz_5_ && lineLoader_fire) || (! lineLoader_flushCounter[5]));
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assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]);
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assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5];
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assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
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assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10];
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assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_5_);
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assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex};
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assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
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assign _zz_6_ = io_cpu_prefetch_pc[9 : 5];
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assign _zz_7_ = (! io_cpu_fetch_isStuck);
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assign _zz_8_ = _zz_12_;
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assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0];
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assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0];
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assign fetchStage_read_waysValues_0_tag_address = _zz_8_[23 : 2];
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assign _zz_9_ = io_cpu_prefetch_pc[9 : 2];
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assign _zz_10_ = (! io_cpu_fetch_isStuck);
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assign fetchStage_read_waysValues_0_data = _zz_13_;
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assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_read_waysValues_0_data[31 : 0]);
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assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid;
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assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc;
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assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0;
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assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
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assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
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assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 10]));
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assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0));
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assign decodeStage_hit_error = decodeStage_hit_tags_0_error;
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assign decodeStage_hit_data = _zz_11_;
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always @ (*) begin
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decodeStage_hit_word = decodeStage_hit_data[31 : 0];
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if(io_cpu_fetch_dataBypassValid_regNextWhen)begin
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decodeStage_hit_word = io_cpu_fetch_dataBypass_regNextWhen;
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end
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end
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assign io_cpu_decode_data = decodeStage_hit_word;
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assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
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assign io_cpu_decode_error = decodeStage_hit_error;
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assign io_cpu_decode_mmuMiss = decodeStage_mmuRsp_miss;
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assign io_cpu_decode_illegalAccess = ((! decodeStage_mmuRsp_allowExecute) || (io_cpu_decode_isUser && (! decodeStage_mmuRsp_allowUser)));
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assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
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always @ (posedge clk) begin
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if(reset) begin
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lineLoader_valid <= 1'b0;
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lineLoader_hadError <= 1'b0;
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lineLoader_flushCounter <= (6'b000000);
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lineLoader_flushFromInterface <= 1'b0;
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lineLoader_cmdSent <= 1'b0;
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lineLoader_wordIndex <= (3'b000);
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end else begin
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if(lineLoader_fire)begin
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lineLoader_valid <= 1'b0;
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end
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if(lineLoader_fire)begin
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lineLoader_hadError <= 1'b0;
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end
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if(io_cpu_fill_valid)begin
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lineLoader_valid <= 1'b1;
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end
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if(_zz_14_)begin
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lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001));
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end
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if(io_flush_cmd_valid)begin
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if(io_flush_cmd_ready)begin
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lineLoader_flushCounter <= (6'b000000);
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lineLoader_flushFromInterface <= 1'b1;
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end
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|
|
end
|
||
|
|
if((io_mem_cmd_valid && io_mem_cmd_ready))begin
|
||
|
|
lineLoader_cmdSent <= 1'b1;
|
||
|
|
end
|
||
|
|
if(lineLoader_fire)begin
|
||
|
|
lineLoader_cmdSent <= 1'b0;
|
||
|
|
end
|
||
|
|
if(io_mem_rsp_valid)begin
|
||
|
|
lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001));
|
||
|
|
if(io_mem_rsp_payload_error)begin
|
||
|
|
lineLoader_hadError <= 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(io_cpu_fill_valid)begin
|
||
|
|
lineLoader_address <= io_cpu_fill_payload;
|
||
|
|
end
|
||
|
|
_zz_3_ <= lineLoader_flushCounter[5];
|
||
|
|
_zz_4__regNext <= _zz_4_;
|
||
|
|
if((! io_cpu_decode_isStuck))begin
|
||
|
|
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress;
|
||
|
|
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess;
|
||
|
|
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead;
|
||
|
|
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite;
|
||
|
|
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute;
|
||
|
|
decodeStage_mmuRsp_allowUser <= io_cpu_fetch_mmuBus_rsp_allowUser;
|
||
|
|
decodeStage_mmuRsp_miss <= io_cpu_fetch_mmuBus_rsp_miss;
|
||
|
|
decodeStage_mmuRsp_hit <= io_cpu_fetch_mmuBus_rsp_hit;
|
||
|
|
end
|
||
|
|
if((! io_cpu_decode_isStuck))begin
|
||
|
|
decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid;
|
||
|
|
decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error;
|
||
|
|
decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address;
|
||
|
|
end
|
||
|
|
if((! io_cpu_decode_isStuck))begin
|
||
|
|
_zz_11_ <= fetchStage_read_waysValues_0_data;
|
||
|
|
end
|
||
|
|
if((! io_cpu_decode_isStuck))begin
|
||
|
|
io_cpu_fetch_dataBypassValid_regNextWhen <= io_cpu_fetch_dataBypassValid;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if((! io_cpu_decode_isStuck))begin
|
||
|
|
io_cpu_fetch_dataBypass_regNextWhen <= io_cpu_fetch_dataBypass;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module VexRiscv (
|
||
|
|
input [31:0] externalResetVector,
|
||
|
|
input timerInterrupt,
|
||
|
|
input [31:0] externalInterruptArray,
|
||
|
|
output reg iBusWishbone_CYC,
|
||
|
|
output reg iBusWishbone_STB,
|
||
|
|
input iBusWishbone_ACK,
|
||
|
|
output iBusWishbone_WE,
|
||
|
|
output [29:0] iBusWishbone_ADR,
|
||
|
|
input [31:0] iBusWishbone_DAT_MISO,
|
||
|
|
output [31:0] iBusWishbone_DAT_MOSI,
|
||
|
|
output [3:0] iBusWishbone_SEL,
|
||
|
|
input iBusWishbone_ERR,
|
||
|
|
output [1:0] iBusWishbone_BTE,
|
||
|
|
output [2:0] iBusWishbone_CTI,
|
||
|
|
output dBusWishbone_CYC,
|
||
|
|
output dBusWishbone_STB,
|
||
|
|
input dBusWishbone_ACK,
|
||
|
|
output dBusWishbone_WE,
|
||
|
|
output [29:0] dBusWishbone_ADR,
|
||
|
|
input [31:0] dBusWishbone_DAT_MISO,
|
||
|
|
output [31:0] dBusWishbone_DAT_MOSI,
|
||
|
|
output reg [3:0] dBusWishbone_SEL,
|
||
|
|
input dBusWishbone_ERR,
|
||
|
|
output [1:0] dBusWishbone_BTE,
|
||
|
|
output [2:0] dBusWishbone_CTI,
|
||
|
|
input clk,
|
||
|
|
input reset);
|
||
|
|
reg _zz_158_;
|
||
|
|
wire _zz_159_;
|
||
|
|
wire _zz_160_;
|
||
|
|
wire _zz_161_;
|
||
|
|
wire _zz_162_;
|
||
|
|
wire [31:0] _zz_163_;
|
||
|
|
wire _zz_164_;
|
||
|
|
wire _zz_165_;
|
||
|
|
wire _zz_166_;
|
||
|
|
wire _zz_167_;
|
||
|
|
wire _zz_168_;
|
||
|
|
wire _zz_169_;
|
||
|
|
wire _zz_170_;
|
||
|
|
wire _zz_171_;
|
||
|
|
wire _zz_172_;
|
||
|
|
wire _zz_173_;
|
||
|
|
reg [31:0] _zz_174_;
|
||
|
|
reg [31:0] _zz_175_;
|
||
|
|
reg [31:0] _zz_176_;
|
||
|
|
reg [3:0] _zz_177_;
|
||
|
|
reg [31:0] _zz_178_;
|
||
|
|
wire IBusCachedPlugin_cache_io_flush_cmd_ready;
|
||
|
|
wire IBusCachedPlugin_cache_io_flush_rsp;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
|
||
|
|
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
|
||
|
|
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
|
||
|
|
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_decode_error;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_decode_mmuMiss;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_decode_illegalAccess;
|
||
|
|
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
|
||
|
|
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
|
||
|
|
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
|
||
|
|
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
|
||
|
|
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
|
||
|
|
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
|
||
|
|
wire _zz_179_;
|
||
|
|
wire _zz_180_;
|
||
|
|
wire _zz_181_;
|
||
|
|
wire _zz_182_;
|
||
|
|
wire _zz_183_;
|
||
|
|
wire _zz_184_;
|
||
|
|
wire _zz_185_;
|
||
|
|
wire [1:0] _zz_186_;
|
||
|
|
wire [1:0] _zz_187_;
|
||
|
|
wire _zz_188_;
|
||
|
|
wire [3:0] _zz_189_;
|
||
|
|
wire [2:0] _zz_190_;
|
||
|
|
wire [31:0] _zz_191_;
|
||
|
|
wire [11:0] _zz_192_;
|
||
|
|
wire [31:0] _zz_193_;
|
||
|
|
wire [19:0] _zz_194_;
|
||
|
|
wire [11:0] _zz_195_;
|
||
|
|
wire [0:0] _zz_196_;
|
||
|
|
wire [0:0] _zz_197_;
|
||
|
|
wire [0:0] _zz_198_;
|
||
|
|
wire [0:0] _zz_199_;
|
||
|
|
wire [0:0] _zz_200_;
|
||
|
|
wire [0:0] _zz_201_;
|
||
|
|
wire [0:0] _zz_202_;
|
||
|
|
wire [2:0] _zz_203_;
|
||
|
|
wire [4:0] _zz_204_;
|
||
|
|
wire [11:0] _zz_205_;
|
||
|
|
wire [11:0] _zz_206_;
|
||
|
|
wire [31:0] _zz_207_;
|
||
|
|
wire [31:0] _zz_208_;
|
||
|
|
wire [31:0] _zz_209_;
|
||
|
|
wire [31:0] _zz_210_;
|
||
|
|
wire [1:0] _zz_211_;
|
||
|
|
wire [31:0] _zz_212_;
|
||
|
|
wire [1:0] _zz_213_;
|
||
|
|
wire [1:0] _zz_214_;
|
||
|
|
wire [31:0] _zz_215_;
|
||
|
|
wire [32:0] _zz_216_;
|
||
|
|
wire [11:0] _zz_217_;
|
||
|
|
wire [19:0] _zz_218_;
|
||
|
|
wire [11:0] _zz_219_;
|
||
|
|
wire [31:0] _zz_220_;
|
||
|
|
wire [31:0] _zz_221_;
|
||
|
|
wire [31:0] _zz_222_;
|
||
|
|
wire [11:0] _zz_223_;
|
||
|
|
wire [19:0] _zz_224_;
|
||
|
|
wire [11:0] _zz_225_;
|
||
|
|
wire [2:0] _zz_226_;
|
||
|
|
wire [2:0] _zz_227_;
|
||
|
|
wire [2:0] _zz_228_;
|
||
|
|
wire [3:0] _zz_229_;
|
||
|
|
wire [0:0] _zz_230_;
|
||
|
|
wire [0:0] _zz_231_;
|
||
|
|
wire [0:0] _zz_232_;
|
||
|
|
wire [0:0] _zz_233_;
|
||
|
|
wire [0:0] _zz_234_;
|
||
|
|
wire [0:0] _zz_235_;
|
||
|
|
wire [26:0] _zz_236_;
|
||
|
|
wire [6:0] _zz_237_;
|
||
|
|
wire [1:0] _zz_238_;
|
||
|
|
wire [0:0] _zz_239_;
|
||
|
|
wire [7:0] _zz_240_;
|
||
|
|
wire _zz_241_;
|
||
|
|
wire [0:0] _zz_242_;
|
||
|
|
wire [0:0] _zz_243_;
|
||
|
|
wire [31:0] _zz_244_;
|
||
|
|
wire [31:0] _zz_245_;
|
||
|
|
wire [31:0] _zz_246_;
|
||
|
|
wire [31:0] _zz_247_;
|
||
|
|
wire [31:0] _zz_248_;
|
||
|
|
wire [31:0] _zz_249_;
|
||
|
|
wire [0:0] _zz_250_;
|
||
|
|
wire [2:0] _zz_251_;
|
||
|
|
wire [1:0] _zz_252_;
|
||
|
|
wire [1:0] _zz_253_;
|
||
|
|
wire _zz_254_;
|
||
|
|
wire [0:0] _zz_255_;
|
||
|
|
wire [18:0] _zz_256_;
|
||
|
|
wire [31:0] _zz_257_;
|
||
|
|
wire [31:0] _zz_258_;
|
||
|
|
wire [31:0] _zz_259_;
|
||
|
|
wire _zz_260_;
|
||
|
|
wire _zz_261_;
|
||
|
|
wire [31:0] _zz_262_;
|
||
|
|
wire [31:0] _zz_263_;
|
||
|
|
wire [31:0] _zz_264_;
|
||
|
|
wire [31:0] _zz_265_;
|
||
|
|
wire _zz_266_;
|
||
|
|
wire _zz_267_;
|
||
|
|
wire [2:0] _zz_268_;
|
||
|
|
wire [2:0] _zz_269_;
|
||
|
|
wire _zz_270_;
|
||
|
|
wire [0:0] _zz_271_;
|
||
|
|
wire [15:0] _zz_272_;
|
||
|
|
wire [31:0] _zz_273_;
|
||
|
|
wire [31:0] _zz_274_;
|
||
|
|
wire _zz_275_;
|
||
|
|
wire _zz_276_;
|
||
|
|
wire [31:0] _zz_277_;
|
||
|
|
wire [31:0] _zz_278_;
|
||
|
|
wire _zz_279_;
|
||
|
|
wire [0:0] _zz_280_;
|
||
|
|
wire [0:0] _zz_281_;
|
||
|
|
wire _zz_282_;
|
||
|
|
wire [0:0] _zz_283_;
|
||
|
|
wire [12:0] _zz_284_;
|
||
|
|
wire [31:0] _zz_285_;
|
||
|
|
wire _zz_286_;
|
||
|
|
wire [0:0] _zz_287_;
|
||
|
|
wire [0:0] _zz_288_;
|
||
|
|
wire [0:0] _zz_289_;
|
||
|
|
wire [0:0] _zz_290_;
|
||
|
|
wire [2:0] _zz_291_;
|
||
|
|
wire [2:0] _zz_292_;
|
||
|
|
wire _zz_293_;
|
||
|
|
wire [0:0] _zz_294_;
|
||
|
|
wire [9:0] _zz_295_;
|
||
|
|
wire [31:0] _zz_296_;
|
||
|
|
wire [31:0] _zz_297_;
|
||
|
|
wire [31:0] _zz_298_;
|
||
|
|
wire _zz_299_;
|
||
|
|
wire _zz_300_;
|
||
|
|
wire [31:0] _zz_301_;
|
||
|
|
wire [31:0] _zz_302_;
|
||
|
|
wire [0:0] _zz_303_;
|
||
|
|
wire [0:0] _zz_304_;
|
||
|
|
wire [5:0] _zz_305_;
|
||
|
|
wire [5:0] _zz_306_;
|
||
|
|
wire _zz_307_;
|
||
|
|
wire [0:0] _zz_308_;
|
||
|
|
wire [6:0] _zz_309_;
|
||
|
|
wire [31:0] _zz_310_;
|
||
|
|
wire [31:0] _zz_311_;
|
||
|
|
wire _zz_312_;
|
||
|
|
wire [0:0] _zz_313_;
|
||
|
|
wire [2:0] _zz_314_;
|
||
|
|
wire [31:0] _zz_315_;
|
||
|
|
wire [31:0] _zz_316_;
|
||
|
|
wire [0:0] _zz_317_;
|
||
|
|
wire [0:0] _zz_318_;
|
||
|
|
wire [1:0] _zz_319_;
|
||
|
|
wire [1:0] _zz_320_;
|
||
|
|
wire _zz_321_;
|
||
|
|
wire [0:0] _zz_322_;
|
||
|
|
wire [3:0] _zz_323_;
|
||
|
|
wire [31:0] _zz_324_;
|
||
|
|
wire _zz_325_;
|
||
|
|
wire _zz_326_;
|
||
|
|
wire [31:0] _zz_327_;
|
||
|
|
wire [31:0] _zz_328_;
|
||
|
|
wire [31:0] _zz_329_;
|
||
|
|
wire [31:0] _zz_330_;
|
||
|
|
wire [31:0] _zz_331_;
|
||
|
|
wire [0:0] _zz_332_;
|
||
|
|
wire [0:0] _zz_333_;
|
||
|
|
wire [1:0] _zz_334_;
|
||
|
|
wire [1:0] _zz_335_;
|
||
|
|
wire _zz_336_;
|
||
|
|
wire [0:0] _zz_337_;
|
||
|
|
wire [0:0] _zz_338_;
|
||
|
|
wire [31:0] _zz_339_;
|
||
|
|
wire [31:0] _zz_340_;
|
||
|
|
wire [31:0] _zz_341_;
|
||
|
|
wire [31:0] _zz_342_;
|
||
|
|
wire [31:0] _zz_343_;
|
||
|
|
wire [31:0] _zz_344_;
|
||
|
|
wire _zz_345_;
|
||
|
|
wire [0:0] _zz_346_;
|
||
|
|
wire [0:0] _zz_347_;
|
||
|
|
wire _zz_348_;
|
||
|
|
wire _zz_349_;
|
||
|
|
wire _zz_350_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_1_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_2_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_3_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_7_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_9_;
|
||
|
|
wire [31:0] execute_FORMAL_PC_NEXT;
|
||
|
|
wire [31:0] decode_FORMAL_PC_NEXT;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_10_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_11_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_12_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_13_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_14_;
|
||
|
|
wire decode_FLUSH_ALL;
|
||
|
|
wire decode_PREDICTION_HAD_BRANCHED2;
|
||
|
|
wire decode_MEMORY_ENABLE;
|
||
|
|
wire execute_REGFILE_WRITE_VALID;
|
||
|
|
wire decode_IS_CSR;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_15_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_16_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_17_;
|
||
|
|
wire decode_CSR_WRITE_OPCODE;
|
||
|
|
wire decode_CSR_READ_OPCODE;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_18_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_19_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_20_;
|
||
|
|
wire decode_SRC_USE_SUB_LESS;
|
||
|
|
wire decode_SRC_LESS_UNSIGNED;
|
||
|
|
wire execute_CSR_READ_OPCODE;
|
||
|
|
wire execute_CSR_WRITE_OPCODE;
|
||
|
|
wire execute_IS_CSR;
|
||
|
|
wire _zz_21_;
|
||
|
|
wire _zz_22_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_23_;
|
||
|
|
wire [31:0] execute_BRANCH_CALC;
|
||
|
|
wire execute_BRANCH_DO;
|
||
|
|
wire [31:0] _zz_24_;
|
||
|
|
wire [31:0] execute_PC;
|
||
|
|
wire execute_PREDICTION_HAD_BRANCHED2;
|
||
|
|
wire _zz_25_;
|
||
|
|
wire [31:0] execute_RS1;
|
||
|
|
wire execute_BRANCH_COND_RESULT;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_26_;
|
||
|
|
wire _zz_27_;
|
||
|
|
wire _zz_28_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_29_;
|
||
|
|
wire _zz_30_;
|
||
|
|
wire [31:0] _zz_31_;
|
||
|
|
wire [31:0] _zz_32_;
|
||
|
|
wire execute_SRC_LESS_UNSIGNED;
|
||
|
|
wire execute_SRC_USE_SUB_LESS;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_33_;
|
||
|
|
wire [31:0] _zz_34_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_35_;
|
||
|
|
wire [31:0] _zz_36_;
|
||
|
|
wire [31:0] execute_SRC_ADD_SUB;
|
||
|
|
wire execute_SRC_LESS;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_37_;
|
||
|
|
wire [31:0] _zz_38_;
|
||
|
|
wire [31:0] execute_SRC2;
|
||
|
|
wire [31:0] execute_SRC1;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39_;
|
||
|
|
reg _zz_40_;
|
||
|
|
wire [31:0] _zz_41_;
|
||
|
|
wire [31:0] _zz_42_;
|
||
|
|
reg decode_REGFILE_WRITE_VALID;
|
||
|
|
wire _zz_43_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_44_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_45_;
|
||
|
|
wire _zz_46_;
|
||
|
|
wire _zz_47_;
|
||
|
|
wire _zz_48_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_49_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_50_;
|
||
|
|
wire _zz_51_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_52_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_53_;
|
||
|
|
wire _zz_54_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_55_;
|
||
|
|
reg [31:0] _zz_56_;
|
||
|
|
wire [1:0] execute_MEMORY_ADDRESS_LOW;
|
||
|
|
wire [31:0] execute_MEMORY_READ_DATA;
|
||
|
|
wire [31:0] execute_REGFILE_WRITE_DATA;
|
||
|
|
wire [31:0] _zz_57_;
|
||
|
|
wire [1:0] _zz_58_;
|
||
|
|
wire [31:0] execute_RS2;
|
||
|
|
wire [31:0] execute_SRC_ADD;
|
||
|
|
wire [31:0] execute_INSTRUCTION;
|
||
|
|
wire execute_ALIGNEMENT_FAULT;
|
||
|
|
wire execute_MEMORY_ENABLE;
|
||
|
|
wire _zz_59_;
|
||
|
|
wire execute_FLUSH_ALL;
|
||
|
|
reg IBusCachedPlugin_rsp_issueDetected;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_60_;
|
||
|
|
reg [31:0] _zz_61_;
|
||
|
|
wire [31:0] _zz_62_;
|
||
|
|
wire [31:0] _zz_63_;
|
||
|
|
wire [31:0] _zz_64_;
|
||
|
|
wire [31:0] decode_PC /* verilator public */ ;
|
||
|
|
wire [31:0] decode_INSTRUCTION /* verilator public */ ;
|
||
|
|
wire decode_arbitration_haltItself /* verilator public */ ;
|
||
|
|
reg decode_arbitration_haltByOther;
|
||
|
|
reg decode_arbitration_removeIt;
|
||
|
|
reg decode_arbitration_flushAll /* verilator public */ ;
|
||
|
|
wire decode_arbitration_redoIt;
|
||
|
|
wire decode_arbitration_isValid /* verilator public */ ;
|
||
|
|
wire decode_arbitration_isStuck;
|
||
|
|
wire decode_arbitration_isStuckByOthers;
|
||
|
|
wire decode_arbitration_isFlushed;
|
||
|
|
wire decode_arbitration_isMoving;
|
||
|
|
wire decode_arbitration_isFiring;
|
||
|
|
reg execute_arbitration_haltItself;
|
||
|
|
wire execute_arbitration_haltByOther;
|
||
|
|
reg execute_arbitration_removeIt;
|
||
|
|
wire execute_arbitration_flushAll;
|
||
|
|
wire execute_arbitration_redoIt;
|
||
|
|
reg execute_arbitration_isValid;
|
||
|
|
wire execute_arbitration_isStuck;
|
||
|
|
wire execute_arbitration_isStuckByOthers;
|
||
|
|
wire execute_arbitration_isFlushed;
|
||
|
|
wire execute_arbitration_isMoving;
|
||
|
|
wire execute_arbitration_isFiring;
|
||
|
|
reg _zz_65_;
|
||
|
|
wire _zz_66_;
|
||
|
|
wire _zz_67_;
|
||
|
|
wire [31:0] _zz_68_;
|
||
|
|
wire _zz_69_;
|
||
|
|
wire _zz_70_;
|
||
|
|
wire [31:0] _zz_71_;
|
||
|
|
wire [31:0] _zz_72_;
|
||
|
|
reg _zz_73_;
|
||
|
|
wire _zz_74_;
|
||
|
|
reg _zz_75_;
|
||
|
|
reg _zz_76_;
|
||
|
|
reg [31:0] _zz_77_;
|
||
|
|
wire externalInterrupt;
|
||
|
|
wire contextSwitching;
|
||
|
|
reg [1:0] CsrPlugin_privilege;
|
||
|
|
reg _zz_78_;
|
||
|
|
reg [3:0] _zz_79_;
|
||
|
|
wire IBusCachedPlugin_jump_pcLoad_valid;
|
||
|
|
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
|
||
|
|
wire [3:0] _zz_80_;
|
||
|
|
wire [3:0] _zz_81_;
|
||
|
|
wire _zz_82_;
|
||
|
|
wire _zz_83_;
|
||
|
|
wire _zz_84_;
|
||
|
|
wire IBusCachedPlugin_fetchPc_preOutput_valid;
|
||
|
|
wire IBusCachedPlugin_fetchPc_preOutput_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload;
|
||
|
|
wire _zz_85_;
|
||
|
|
wire IBusCachedPlugin_fetchPc_output_valid;
|
||
|
|
wire IBusCachedPlugin_fetchPc_output_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
|
||
|
|
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
|
||
|
|
reg IBusCachedPlugin_fetchPc_inc;
|
||
|
|
reg IBusCachedPlugin_fetchPc_propagatePc;
|
||
|
|
reg [31:0] IBusCachedPlugin_fetchPc_pc;
|
||
|
|
reg IBusCachedPlugin_fetchPc_samplePcNext;
|
||
|
|
reg _zz_86_;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
|
||
|
|
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_0_inputSample;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
|
||
|
|
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_stages_1_inputSample;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
|
||
|
|
reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample;
|
||
|
|
wire _zz_87_;
|
||
|
|
wire _zz_88_;
|
||
|
|
wire _zz_89_;
|
||
|
|
wire _zz_90_;
|
||
|
|
wire _zz_91_;
|
||
|
|
reg _zz_92_;
|
||
|
|
wire _zz_93_;
|
||
|
|
reg _zz_94_;
|
||
|
|
reg [31:0] _zz_95_;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_readyForError;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_valid;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_ready;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error;
|
||
|
|
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
|
||
|
|
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc;
|
||
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
|
||
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
|
||
|
|
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
|
||
|
|
reg IBusCachedPlugin_injector_decodeRemoved;
|
||
|
|
wire _zz_96_;
|
||
|
|
reg [18:0] _zz_97_;
|
||
|
|
wire _zz_98_;
|
||
|
|
reg [10:0] _zz_99_;
|
||
|
|
wire _zz_100_;
|
||
|
|
reg [18:0] _zz_101_;
|
||
|
|
wire iBus_cmd_valid;
|
||
|
|
wire iBus_cmd_ready;
|
||
|
|
reg [31:0] iBus_cmd_payload_address;
|
||
|
|
wire [2:0] iBus_cmd_payload_size;
|
||
|
|
wire iBus_rsp_valid;
|
||
|
|
wire [31:0] iBus_rsp_payload_data;
|
||
|
|
wire iBus_rsp_payload_error;
|
||
|
|
wire IBusCachedPlugin_s0_tightlyCoupledHit;
|
||
|
|
reg IBusCachedPlugin_s1_tightlyCoupledHit;
|
||
|
|
reg IBusCachedPlugin_s2_tightlyCoupledHit;
|
||
|
|
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
|
||
|
|
reg IBusCachedPlugin_rsp_redoFetch;
|
||
|
|
wire dBus_cmd_valid;
|
||
|
|
wire dBus_cmd_ready;
|
||
|
|
wire dBus_cmd_payload_wr;
|
||
|
|
wire [31:0] dBus_cmd_payload_address;
|
||
|
|
wire [31:0] dBus_cmd_payload_data;
|
||
|
|
wire [1:0] dBus_cmd_payload_size;
|
||
|
|
wire dBus_rsp_ready;
|
||
|
|
wire dBus_rsp_error;
|
||
|
|
wire [31:0] dBus_rsp_data;
|
||
|
|
reg execute_DBusSimplePlugin_cmdSent;
|
||
|
|
reg [31:0] _zz_102_;
|
||
|
|
reg [3:0] _zz_103_;
|
||
|
|
wire [3:0] execute_DBusSimplePlugin_formalMask;
|
||
|
|
reg [31:0] execute_DBusSimplePlugin_rspShifted;
|
||
|
|
wire _zz_104_;
|
||
|
|
reg [31:0] _zz_105_;
|
||
|
|
wire _zz_106_;
|
||
|
|
reg [31:0] _zz_107_;
|
||
|
|
reg [31:0] execute_DBusSimplePlugin_rspFormated;
|
||
|
|
wire [24:0] _zz_108_;
|
||
|
|
wire _zz_109_;
|
||
|
|
wire _zz_110_;
|
||
|
|
wire _zz_111_;
|
||
|
|
wire _zz_112_;
|
||
|
|
wire `Src2CtrlEnum_defaultEncoding_type _zz_113_;
|
||
|
|
wire `EnvCtrlEnum_defaultEncoding_type _zz_114_;
|
||
|
|
wire `Src1CtrlEnum_defaultEncoding_type _zz_115_;
|
||
|
|
wire `ShiftCtrlEnum_defaultEncoding_type _zz_116_;
|
||
|
|
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_117_;
|
||
|
|
wire `AluCtrlEnum_defaultEncoding_type _zz_118_;
|
||
|
|
wire `BranchCtrlEnum_defaultEncoding_type _zz_119_;
|
||
|
|
wire [4:0] execute_RegFilePlugin_regFileReadAddress1;
|
||
|
|
wire [4:0] execute_RegFilePlugin_regFileReadAddress2;
|
||
|
|
wire _zz_120_;
|
||
|
|
wire [31:0] execute_RegFilePlugin_rs1Data;
|
||
|
|
wire [31:0] execute_RegFilePlugin_rs2Data;
|
||
|
|
wire execute_RegFilePlugin_regFileWrite_valid /* verilator public */ ;
|
||
|
|
wire [4:0] execute_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ;
|
||
|
|
wire [31:0] execute_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ;
|
||
|
|
reg [31:0] execute_IntAluPlugin_bitwise;
|
||
|
|
reg [31:0] _zz_121_;
|
||
|
|
reg [31:0] _zz_122_;
|
||
|
|
wire _zz_123_;
|
||
|
|
reg [19:0] _zz_124_;
|
||
|
|
wire _zz_125_;
|
||
|
|
reg [19:0] _zz_126_;
|
||
|
|
reg [31:0] _zz_127_;
|
||
|
|
wire [31:0] execute_SrcPlugin_addSub;
|
||
|
|
wire execute_SrcPlugin_less;
|
||
|
|
reg execute_LightShifterPlugin_isActive;
|
||
|
|
wire execute_LightShifterPlugin_isShift;
|
||
|
|
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
|
||
|
|
wire [4:0] execute_LightShifterPlugin_amplitude;
|
||
|
|
reg [31:0] execute_LightShifterPlugin_shiftReg;
|
||
|
|
wire [31:0] execute_LightShifterPlugin_shiftInput;
|
||
|
|
wire execute_LightShifterPlugin_done;
|
||
|
|
reg [31:0] _zz_128_;
|
||
|
|
wire execute_BranchPlugin_eq;
|
||
|
|
wire [2:0] _zz_129_;
|
||
|
|
reg _zz_130_;
|
||
|
|
reg _zz_131_;
|
||
|
|
wire _zz_132_;
|
||
|
|
reg [19:0] _zz_133_;
|
||
|
|
wire _zz_134_;
|
||
|
|
reg [10:0] _zz_135_;
|
||
|
|
wire _zz_136_;
|
||
|
|
reg [18:0] _zz_137_;
|
||
|
|
reg _zz_138_;
|
||
|
|
wire execute_BranchPlugin_missAlignedTarget;
|
||
|
|
reg [31:0] execute_BranchPlugin_branch_src1;
|
||
|
|
reg [31:0] execute_BranchPlugin_branch_src2;
|
||
|
|
wire _zz_139_;
|
||
|
|
reg [19:0] _zz_140_;
|
||
|
|
wire _zz_141_;
|
||
|
|
reg [10:0] _zz_142_;
|
||
|
|
wire _zz_143_;
|
||
|
|
reg [18:0] _zz_144_;
|
||
|
|
wire [31:0] execute_BranchPlugin_branchAdder;
|
||
|
|
wire [1:0] CsrPlugin_misa_base;
|
||
|
|
wire [25:0] CsrPlugin_misa_extensions;
|
||
|
|
reg [1:0] CsrPlugin_mtvec_mode;
|
||
|
|
reg [29:0] CsrPlugin_mtvec_base;
|
||
|
|
reg [31:0] CsrPlugin_mepc;
|
||
|
|
reg CsrPlugin_mstatus_MIE;
|
||
|
|
reg CsrPlugin_mstatus_MPIE;
|
||
|
|
reg [1:0] CsrPlugin_mstatus_MPP;
|
||
|
|
reg CsrPlugin_mip_MEIP;
|
||
|
|
reg CsrPlugin_mip_MTIP;
|
||
|
|
reg CsrPlugin_mip_MSIP;
|
||
|
|
reg CsrPlugin_mie_MEIE;
|
||
|
|
reg CsrPlugin_mie_MTIE;
|
||
|
|
reg CsrPlugin_mie_MSIE;
|
||
|
|
reg [31:0] CsrPlugin_mscratch;
|
||
|
|
reg CsrPlugin_mcause_interrupt;
|
||
|
|
reg [3:0] CsrPlugin_mcause_exceptionCode;
|
||
|
|
reg [31:0] CsrPlugin_mtval;
|
||
|
|
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
||
|
|
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
|
||
|
|
wire [31:0] CsrPlugin_medeleg;
|
||
|
|
wire [31:0] CsrPlugin_mideleg;
|
||
|
|
wire _zz_145_;
|
||
|
|
wire _zz_146_;
|
||
|
|
wire _zz_147_;
|
||
|
|
wire CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
|
||
|
|
wire CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
||
|
|
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
||
|
|
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
||
|
|
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
||
|
|
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
||
|
|
wire execute_exception_agregat_valid;
|
||
|
|
wire [3:0] execute_exception_agregat_payload_code;
|
||
|
|
wire [31:0] execute_exception_agregat_payload_badAddr;
|
||
|
|
wire [2:0] _zz_148_;
|
||
|
|
wire [2:0] _zz_149_;
|
||
|
|
wire _zz_150_;
|
||
|
|
wire _zz_151_;
|
||
|
|
wire [1:0] _zz_152_;
|
||
|
|
reg CsrPlugin_interrupt;
|
||
|
|
reg [3:0] CsrPlugin_interruptCode /* verilator public */ ;
|
||
|
|
wire [1:0] CsrPlugin_interruptTargetPrivilege;
|
||
|
|
wire CsrPlugin_exception;
|
||
|
|
wire CsrPlugin_lastStageWasWfi;
|
||
|
|
reg CsrPlugin_pipelineLiberator_done;
|
||
|
|
wire CsrPlugin_interruptJump /* verilator public */ ;
|
||
|
|
reg CsrPlugin_hadException;
|
||
|
|
reg [1:0] CsrPlugin_targetPrivilege;
|
||
|
|
reg [3:0] CsrPlugin_trapCause;
|
||
|
|
wire execute_CsrPlugin_blockedBySideEffects;
|
||
|
|
reg execute_CsrPlugin_illegalAccess;
|
||
|
|
reg execute_CsrPlugin_illegalInstruction;
|
||
|
|
reg [31:0] execute_CsrPlugin_readData;
|
||
|
|
wire execute_CsrPlugin_writeInstruction;
|
||
|
|
wire execute_CsrPlugin_readInstruction;
|
||
|
|
wire execute_CsrPlugin_writeEnable;
|
||
|
|
wire execute_CsrPlugin_readEnable;
|
||
|
|
reg [31:0] execute_CsrPlugin_writeData;
|
||
|
|
wire [11:0] execute_CsrPlugin_csrAddress;
|
||
|
|
reg [31:0] _zz_153_;
|
||
|
|
reg [31:0] externalInterruptArray_regNext;
|
||
|
|
wire [31:0] _zz_154_;
|
||
|
|
reg decode_to_execute_SRC_LESS_UNSIGNED;
|
||
|
|
reg decode_to_execute_SRC_USE_SUB_LESS;
|
||
|
|
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
|
||
|
|
reg [31:0] decode_to_execute_INSTRUCTION;
|
||
|
|
reg decode_to_execute_CSR_READ_OPCODE;
|
||
|
|
reg decode_to_execute_CSR_WRITE_OPCODE;
|
||
|
|
reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
|
||
|
|
reg decode_to_execute_IS_CSR;
|
||
|
|
reg decode_to_execute_REGFILE_WRITE_VALID;
|
||
|
|
reg decode_to_execute_MEMORY_ENABLE;
|
||
|
|
reg [31:0] decode_to_execute_PC;
|
||
|
|
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
|
||
|
|
reg decode_to_execute_FLUSH_ALL;
|
||
|
|
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
|
||
|
|
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
|
||
|
|
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
|
||
|
|
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
|
||
|
|
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
|
||
|
|
reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
|
||
|
|
reg [2:0] _zz_155_;
|
||
|
|
reg _zz_156_;
|
||
|
|
reg [31:0] iBusWishbone_DAT_MISO_regNext;
|
||
|
|
wire dBus_cmd_halfPipe_valid;
|
||
|
|
wire dBus_cmd_halfPipe_ready;
|
||
|
|
wire dBus_cmd_halfPipe_payload_wr;
|
||
|
|
wire [31:0] dBus_cmd_halfPipe_payload_address;
|
||
|
|
wire [31:0] dBus_cmd_halfPipe_payload_data;
|
||
|
|
wire [1:0] dBus_cmd_halfPipe_payload_size;
|
||
|
|
reg dBus_cmd_halfPipe_regs_valid;
|
||
|
|
reg dBus_cmd_halfPipe_regs_ready;
|
||
|
|
reg dBus_cmd_halfPipe_regs_payload_wr;
|
||
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
|
||
|
|
reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
|
||
|
|
reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
|
||
|
|
reg [3:0] _zz_157_;
|
||
|
|
`ifndef SYNTHESIS
|
||
|
|
reg [95:0] decode_SRC1_CTRL_string;
|
||
|
|
reg [95:0] _zz_1__string;
|
||
|
|
reg [95:0] _zz_2__string;
|
||
|
|
reg [95:0] _zz_3__string;
|
||
|
|
reg [39:0] decode_ALU_BITWISE_CTRL_string;
|
||
|
|
reg [39:0] _zz_4__string;
|
||
|
|
reg [39:0] _zz_5__string;
|
||
|
|
reg [39:0] _zz_6__string;
|
||
|
|
reg [71:0] decode_SHIFT_CTRL_string;
|
||
|
|
reg [71:0] _zz_7__string;
|
||
|
|
reg [71:0] _zz_8__string;
|
||
|
|
reg [71:0] _zz_9__string;
|
||
|
|
reg [31:0] _zz_10__string;
|
||
|
|
reg [31:0] _zz_11__string;
|
||
|
|
reg [47:0] decode_ENV_CTRL_string;
|
||
|
|
reg [47:0] _zz_12__string;
|
||
|
|
reg [47:0] _zz_13__string;
|
||
|
|
reg [47:0] _zz_14__string;
|
||
|
|
reg [23:0] decode_SRC2_CTRL_string;
|
||
|
|
reg [23:0] _zz_15__string;
|
||
|
|
reg [23:0] _zz_16__string;
|
||
|
|
reg [23:0] _zz_17__string;
|
||
|
|
reg [63:0] decode_ALU_CTRL_string;
|
||
|
|
reg [63:0] _zz_18__string;
|
||
|
|
reg [63:0] _zz_19__string;
|
||
|
|
reg [63:0] _zz_20__string;
|
||
|
|
reg [47:0] execute_ENV_CTRL_string;
|
||
|
|
reg [47:0] _zz_23__string;
|
||
|
|
reg [31:0] execute_BRANCH_CTRL_string;
|
||
|
|
reg [31:0] _zz_26__string;
|
||
|
|
reg [71:0] execute_SHIFT_CTRL_string;
|
||
|
|
reg [71:0] _zz_29__string;
|
||
|
|
reg [23:0] execute_SRC2_CTRL_string;
|
||
|
|
reg [23:0] _zz_33__string;
|
||
|
|
reg [95:0] execute_SRC1_CTRL_string;
|
||
|
|
reg [95:0] _zz_35__string;
|
||
|
|
reg [63:0] execute_ALU_CTRL_string;
|
||
|
|
reg [63:0] _zz_37__string;
|
||
|
|
reg [39:0] execute_ALU_BITWISE_CTRL_string;
|
||
|
|
reg [39:0] _zz_39__string;
|
||
|
|
reg [31:0] _zz_44__string;
|
||
|
|
reg [63:0] _zz_45__string;
|
||
|
|
reg [39:0] _zz_49__string;
|
||
|
|
reg [71:0] _zz_50__string;
|
||
|
|
reg [95:0] _zz_52__string;
|
||
|
|
reg [47:0] _zz_53__string;
|
||
|
|
reg [23:0] _zz_55__string;
|
||
|
|
reg [31:0] decode_BRANCH_CTRL_string;
|
||
|
|
reg [31:0] _zz_60__string;
|
||
|
|
reg [23:0] _zz_113__string;
|
||
|
|
reg [47:0] _zz_114__string;
|
||
|
|
reg [95:0] _zz_115__string;
|
||
|
|
reg [71:0] _zz_116__string;
|
||
|
|
reg [39:0] _zz_117__string;
|
||
|
|
reg [63:0] _zz_118__string;
|
||
|
|
reg [31:0] _zz_119__string;
|
||
|
|
reg [63:0] decode_to_execute_ALU_CTRL_string;
|
||
|
|
reg [23:0] decode_to_execute_SRC2_CTRL_string;
|
||
|
|
reg [47:0] decode_to_execute_ENV_CTRL_string;
|
||
|
|
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
|
||
|
|
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
|
||
|
|
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
|
||
|
|
reg [95:0] decode_to_execute_SRC1_CTRL_string;
|
||
|
|
`endif
|
||
|
|
|
||
|
|
reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
|
||
|
|
assign _zz_179_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
|
||
|
|
assign _zz_180_ = (! execute_arbitration_isStuckByOthers);
|
||
|
|
assign _zz_181_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
|
||
|
|
assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
|
||
|
|
assign _zz_183_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready);
|
||
|
|
assign _zz_184_ = (iBus_cmd_valid || (_zz_155_ != (3'b000)));
|
||
|
|
assign _zz_185_ = (! dBus_cmd_halfPipe_regs_valid);
|
||
|
|
assign _zz_186_ = execute_INSTRUCTION[13 : 12];
|
||
|
|
assign _zz_187_ = execute_INSTRUCTION[29 : 28];
|
||
|
|
assign _zz_188_ = execute_INSTRUCTION[13];
|
||
|
|
assign _zz_189_ = (_zz_80_ - (4'b0001));
|
||
|
|
assign _zz_190_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)};
|
||
|
|
assign _zz_191_ = {29'd0, _zz_190_};
|
||
|
|
assign _zz_192_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
|
||
|
|
assign _zz_193_ = {{_zz_97_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
|
||
|
|
assign _zz_194_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
|
||
|
|
assign _zz_195_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
|
||
|
|
assign _zz_196_ = _zz_108_[3 : 3];
|
||
|
|
assign _zz_197_ = _zz_108_[9 : 9];
|
||
|
|
assign _zz_198_ = _zz_108_[14 : 14];
|
||
|
|
assign _zz_199_ = _zz_108_[15 : 15];
|
||
|
|
assign _zz_200_ = _zz_108_[16 : 16];
|
||
|
|
assign _zz_201_ = _zz_108_[24 : 24];
|
||
|
|
assign _zz_202_ = execute_SRC_LESS;
|
||
|
|
assign _zz_203_ = (3'b100);
|
||
|
|
assign _zz_204_ = execute_INSTRUCTION[19 : 15];
|
||
|
|
assign _zz_205_ = execute_INSTRUCTION[31 : 20];
|
||
|
|
assign _zz_206_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
|
||
|
|
assign _zz_207_ = ($signed(_zz_208_) + $signed(_zz_212_));
|
||
|
|
assign _zz_208_ = ($signed(_zz_209_) + $signed(_zz_210_));
|
||
|
|
assign _zz_209_ = execute_SRC1;
|
||
|
|
assign _zz_210_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
|
||
|
|
assign _zz_211_ = (execute_SRC_USE_SUB_LESS ? _zz_213_ : _zz_214_);
|
||
|
|
assign _zz_212_ = {{30{_zz_211_[1]}}, _zz_211_};
|
||
|
|
assign _zz_213_ = (2'b01);
|
||
|
|
assign _zz_214_ = (2'b00);
|
||
|
|
assign _zz_215_ = (_zz_216_ >>> 1);
|
||
|
|
assign _zz_216_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
|
||
|
|
assign _zz_217_ = execute_INSTRUCTION[31 : 20];
|
||
|
|
assign _zz_218_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
|
||
|
|
assign _zz_219_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
|
||
|
|
assign _zz_220_ = {_zz_133_,execute_INSTRUCTION[31 : 20]};
|
||
|
|
assign _zz_221_ = {{_zz_135_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
|
||
|
|
assign _zz_222_ = {{_zz_137_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
|
||
|
|
assign _zz_223_ = execute_INSTRUCTION[31 : 20];
|
||
|
|
assign _zz_224_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
|
||
|
|
assign _zz_225_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
|
||
|
|
assign _zz_226_ = (3'b100);
|
||
|
|
assign _zz_227_ = (_zz_148_ - (3'b001));
|
||
|
|
assign _zz_228_ = (execute_INSTRUCTION[5] ? (3'b110) : (3'b100));
|
||
|
|
assign _zz_229_ = {1'd0, _zz_228_};
|
||
|
|
assign _zz_230_ = execute_CsrPlugin_writeData[7 : 7];
|
||
|
|
assign _zz_231_ = execute_CsrPlugin_writeData[3 : 3];
|
||
|
|
assign _zz_232_ = execute_CsrPlugin_writeData[3 : 3];
|
||
|
|
assign _zz_233_ = execute_CsrPlugin_writeData[11 : 11];
|
||
|
|
assign _zz_234_ = execute_CsrPlugin_writeData[7 : 7];
|
||
|
|
assign _zz_235_ = execute_CsrPlugin_writeData[3 : 3];
|
||
|
|
assign _zz_236_ = (iBus_cmd_payload_address >>> 5);
|
||
|
|
assign _zz_237_ = ({3'd0,_zz_157_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
|
||
|
|
assign _zz_238_ = {_zz_84_,_zz_83_};
|
||
|
|
assign _zz_239_ = decode_INSTRUCTION[31];
|
||
|
|
assign _zz_240_ = decode_INSTRUCTION[19 : 12];
|
||
|
|
assign _zz_241_ = decode_INSTRUCTION[20];
|
||
|
|
assign _zz_242_ = decode_INSTRUCTION[31];
|
||
|
|
assign _zz_243_ = decode_INSTRUCTION[7];
|
||
|
|
assign _zz_244_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000));
|
||
|
|
assign _zz_245_ = (32'b00000000000000000001000001010000);
|
||
|
|
assign _zz_246_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000));
|
||
|
|
assign _zz_247_ = (32'b00000000000000000010000001010000);
|
||
|
|
assign _zz_248_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010000));
|
||
|
|
assign _zz_249_ = (32'b00000000000000000000000000010000);
|
||
|
|
assign _zz_250_ = ((decode_INSTRUCTION & _zz_257_) == (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_251_ = {(_zz_258_ == _zz_259_),{_zz_260_,_zz_261_}};
|
||
|
|
assign _zz_252_ = {(_zz_262_ == _zz_263_),(_zz_264_ == _zz_265_)};
|
||
|
|
assign _zz_253_ = (2'b00);
|
||
|
|
assign _zz_254_ = ({_zz_112_,_zz_266_} != (2'b00));
|
||
|
|
assign _zz_255_ = (_zz_267_ != (1'b0));
|
||
|
|
assign _zz_256_ = {(_zz_268_ != _zz_269_),{_zz_270_,{_zz_271_,_zz_272_}}};
|
||
|
|
assign _zz_257_ = (32'b00000000000000000000000001000100);
|
||
|
|
assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000));
|
||
|
|
assign _zz_259_ = (32'b00000000000000000000000000000000);
|
||
|
|
assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000));
|
||
|
|
assign _zz_261_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000));
|
||
|
|
assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100));
|
||
|
|
assign _zz_263_ = (32'b00000000000000000000000000100000);
|
||
|
|
assign _zz_264_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
|
||
|
|
assign _zz_265_ = (32'b00000000000000000000000000100000);
|
||
|
|
assign _zz_266_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000000000000000100));
|
||
|
|
assign _zz_267_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000));
|
||
|
|
assign _zz_268_ = {(_zz_273_ == _zz_274_),{_zz_275_,_zz_276_}};
|
||
|
|
assign _zz_269_ = (3'b000);
|
||
|
|
assign _zz_270_ = ((_zz_277_ == _zz_278_) != (1'b0));
|
||
|
|
assign _zz_271_ = (_zz_279_ != (1'b0));
|
||
|
|
assign _zz_272_ = {(_zz_280_ != _zz_281_),{_zz_282_,{_zz_283_,_zz_284_}}};
|
||
|
|
assign _zz_273_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100));
|
||
|
|
assign _zz_274_ = (32'b00000000000000000000000000100100);
|
||
|
|
assign _zz_275_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000));
|
||
|
|
assign _zz_276_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000010100)) == (32'b00000000000000000001000000010000));
|
||
|
|
assign _zz_277_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100));
|
||
|
|
assign _zz_278_ = (32'b00000000000000000010000000010000);
|
||
|
|
assign _zz_279_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_280_ = ((decode_INSTRUCTION & _zz_285_) == (32'b00000000000000000000000000001000));
|
||
|
|
assign _zz_281_ = (1'b0);
|
||
|
|
assign _zz_282_ = ({_zz_286_,{_zz_287_,_zz_288_}} != (3'b000));
|
||
|
|
assign _zz_283_ = ({_zz_289_,_zz_290_} != (2'b00));
|
||
|
|
assign _zz_284_ = {(_zz_291_ != _zz_292_),{_zz_293_,{_zz_294_,_zz_295_}}};
|
||
|
|
assign _zz_285_ = (32'b00000000000000000001000001001000);
|
||
|
|
assign _zz_286_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000));
|
||
|
|
assign _zz_287_ = ((decode_INSTRUCTION & _zz_296_) == (32'b01000000000000000000000000110000));
|
||
|
|
assign _zz_288_ = ((decode_INSTRUCTION & _zz_297_) == (32'b00000000000000000010000000010000));
|
||
|
|
assign _zz_289_ = ((decode_INSTRUCTION & _zz_298_) == (32'b00000000000000000001000000000000));
|
||
|
|
assign _zz_290_ = _zz_110_;
|
||
|
|
assign _zz_291_ = {_zz_110_,{_zz_299_,_zz_300_}};
|
||
|
|
assign _zz_292_ = (3'b000);
|
||
|
|
assign _zz_293_ = ((_zz_301_ == _zz_302_) != (1'b0));
|
||
|
|
assign _zz_294_ = ({_zz_303_,_zz_304_} != (2'b00));
|
||
|
|
assign _zz_295_ = {(_zz_305_ != _zz_306_),{_zz_307_,{_zz_308_,_zz_309_}}};
|
||
|
|
assign _zz_296_ = (32'b01000000000000000000000000110000);
|
||
|
|
assign _zz_297_ = (32'b00000000000000000010000000010100);
|
||
|
|
assign _zz_298_ = (32'b00000000000000000001000000000000);
|
||
|
|
assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000001000000000000));
|
||
|
|
assign _zz_300_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
|
||
|
|
assign _zz_301_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100));
|
||
|
|
assign _zz_302_ = (32'b00000000000000000101000000010000);
|
||
|
|
assign _zz_303_ = ((decode_INSTRUCTION & _zz_310_) == (32'b01000000000000000001000000010000));
|
||
|
|
assign _zz_304_ = ((decode_INSTRUCTION & _zz_311_) == (32'b00000000000000000001000000010000));
|
||
|
|
assign _zz_305_ = {_zz_112_,{_zz_312_,{_zz_313_,_zz_314_}}};
|
||
|
|
assign _zz_306_ = (6'b000000);
|
||
|
|
assign _zz_307_ = ((_zz_315_ == _zz_316_) != (1'b0));
|
||
|
|
assign _zz_308_ = ({_zz_317_,_zz_318_} != (2'b00));
|
||
|
|
assign _zz_309_ = {(_zz_319_ != _zz_320_),{_zz_321_,{_zz_322_,_zz_323_}}};
|
||
|
|
assign _zz_310_ = (32'b01000000000000000011000001010100);
|
||
|
|
assign _zz_311_ = (32'b00000000000000000111000001010100);
|
||
|
|
assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000));
|
||
|
|
assign _zz_313_ = ((decode_INSTRUCTION & _zz_324_) == (32'b00000000000000000010000000010000));
|
||
|
|
assign _zz_314_ = {_zz_109_,{_zz_325_,_zz_326_}};
|
||
|
|
assign _zz_315_ = (decode_INSTRUCTION & (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_316_ = (32'b00000000000000000000000000000000);
|
||
|
|
assign _zz_317_ = ((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000000000000000100));
|
||
|
|
assign _zz_318_ = _zz_111_;
|
||
|
|
assign _zz_319_ = {(_zz_328_ == _zz_329_),_zz_111_};
|
||
|
|
assign _zz_320_ = (2'b00);
|
||
|
|
assign _zz_321_ = ((_zz_330_ == _zz_331_) != (1'b0));
|
||
|
|
assign _zz_322_ = ({_zz_332_,_zz_333_} != (2'b00));
|
||
|
|
assign _zz_323_ = {(_zz_334_ != _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}};
|
||
|
|
assign _zz_324_ = (32'b00000000000000000010000000010000);
|
||
|
|
assign _zz_325_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_326_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000000000000000100));
|
||
|
|
assign _zz_327_ = (32'b00000000000000000000000000010100);
|
||
|
|
assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100));
|
||
|
|
assign _zz_329_ = (32'b00000000000000000000000000000100);
|
||
|
|
assign _zz_330_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000));
|
||
|
|
assign _zz_331_ = (32'b00000000000000000000000001010000);
|
||
|
|
assign _zz_332_ = ((decode_INSTRUCTION & _zz_339_) == (32'b00000000000100000000000001010000));
|
||
|
|
assign _zz_333_ = ((decode_INSTRUCTION & _zz_340_) == (32'b00010000000000000000000001010000));
|
||
|
|
assign _zz_334_ = {(_zz_341_ == _zz_342_),(_zz_343_ == _zz_344_)};
|
||
|
|
assign _zz_335_ = (2'b00);
|
||
|
|
assign _zz_336_ = ({_zz_110_,_zz_345_} != (2'b00));
|
||
|
|
assign _zz_337_ = ({_zz_346_,_zz_347_} != (2'b00));
|
||
|
|
assign _zz_338_ = (_zz_109_ != (1'b0));
|
||
|
|
assign _zz_339_ = (32'b00010000000100000011000001010000);
|
||
|
|
assign _zz_340_ = (32'b00010000010000000011000001010000);
|
||
|
|
assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
|
||
|
|
assign _zz_342_ = (32'b00000000000000000010000000000000);
|
||
|
|
assign _zz_343_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000));
|
||
|
|
assign _zz_344_ = (32'b00000000000000000001000000000000);
|
||
|
|
assign _zz_345_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000));
|
||
|
|
assign _zz_346_ = _zz_110_;
|
||
|
|
assign _zz_347_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_348_ = execute_INSTRUCTION[31];
|
||
|
|
assign _zz_349_ = execute_INSTRUCTION[31];
|
||
|
|
assign _zz_350_ = execute_INSTRUCTION[7];
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(_zz_40_) begin
|
||
|
|
RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(_zz_120_) begin
|
||
|
|
_zz_174_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(_zz_120_) begin
|
||
|
|
_zz_175_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
InstructionCache IBusCachedPlugin_cache (
|
||
|
|
.io_flush_cmd_valid(_zz_158_),
|
||
|
|
.io_flush_cmd_ready(IBusCachedPlugin_cache_io_flush_cmd_ready),
|
||
|
|
.io_flush_rsp(IBusCachedPlugin_cache_io_flush_rsp),
|
||
|
|
.io_cpu_prefetch_isValid(_zz_159_),
|
||
|
|
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
|
||
|
|
.io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload),
|
||
|
|
.io_cpu_fetch_isValid(_zz_160_),
|
||
|
|
.io_cpu_fetch_isStuck(_zz_161_),
|
||
|
|
.io_cpu_fetch_isRemoved(_zz_162_),
|
||
|
|
.io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload),
|
||
|
|
.io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data),
|
||
|
|
.io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit),
|
||
|
|
.io_cpu_fetch_dataBypass(_zz_163_),
|
||
|
|
.io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid),
|
||
|
|
.io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress),
|
||
|
|
.io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_physicalAddress(_zz_72_),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_164_),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_allowRead(_zz_165_),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_166_),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_167_),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_allowUser(_zz_168_),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_miss(_zz_169_),
|
||
|
|
.io_cpu_fetch_mmuBus_rsp_hit(_zz_170_),
|
||
|
|
.io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end),
|
||
|
|
.io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
|
||
|
|
.io_cpu_decode_isValid(_zz_171_),
|
||
|
|
.io_cpu_decode_isStuck(_zz_172_),
|
||
|
|
.io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload),
|
||
|
|
.io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
|
||
|
|
.io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data),
|
||
|
|
.io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss),
|
||
|
|
.io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error),
|
||
|
|
.io_cpu_decode_mmuMiss(IBusCachedPlugin_cache_io_cpu_decode_mmuMiss),
|
||
|
|
.io_cpu_decode_illegalAccess(IBusCachedPlugin_cache_io_cpu_decode_illegalAccess),
|
||
|
|
.io_cpu_decode_isUser(_zz_173_),
|
||
|
|
.io_cpu_fill_valid(IBusCachedPlugin_rsp_redoFetch),
|
||
|
|
.io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
|
||
|
|
.io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid),
|
||
|
|
.io_mem_cmd_ready(iBus_cmd_ready),
|
||
|
|
.io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address),
|
||
|
|
.io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size),
|
||
|
|
.io_mem_rsp_valid(iBus_rsp_valid),
|
||
|
|
.io_mem_rsp_payload_data(iBus_rsp_payload_data),
|
||
|
|
.io_mem_rsp_payload_error(iBus_rsp_payload_error),
|
||
|
|
.clk(clk),
|
||
|
|
.reset(reset)
|
||
|
|
);
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_238_)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_176_ = execute_BRANCH_CALC;
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_176_ = _zz_77_;
|
||
|
|
end
|
||
|
|
2'b10 : begin
|
||
|
|
_zz_176_ = _zz_71_;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_176_ = _zz_68_;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_152_)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_177_ = _zz_229_;
|
||
|
|
_zz_178_ = execute_REGFILE_WRITE_DATA;
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_177_ = (4'b0000);
|
||
|
|
_zz_178_ = execute_BRANCH_CALC;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_177_ = _zz_79_;
|
||
|
|
_zz_178_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
`ifndef SYNTHESIS
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
|
||
|
|
default : decode_SRC1_CTRL_string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_1_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 ";
|
||
|
|
default : _zz_1__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_2_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 ";
|
||
|
|
default : _zz_2__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_3_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 ";
|
||
|
|
default : _zz_3__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_ALU_BITWISE_CTRL_string = "SRC1 ";
|
||
|
|
default : decode_ALU_BITWISE_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_4_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_4__string = "SRC1 ";
|
||
|
|
default : _zz_4__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_5_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_5__string = "SRC1 ";
|
||
|
|
default : _zz_5__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_6_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_6__string = "SRC1 ";
|
||
|
|
default : _zz_6__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
|
||
|
|
default : decode_SHIFT_CTRL_string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_7_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7__string = "SRA_1 ";
|
||
|
|
default : _zz_7__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_8_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 ";
|
||
|
|
default : _zz_8__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_9_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9__string = "SRA_1 ";
|
||
|
|
default : _zz_9__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_10_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_10__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_10__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_10__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_10__string = "JALR";
|
||
|
|
default : _zz_10__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_11_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR";
|
||
|
|
default : _zz_11__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK";
|
||
|
|
default : decode_ENV_CTRL_string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_12_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_12__string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_12__string = "EBREAK";
|
||
|
|
default : _zz_12__string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_13_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_13__string = "EBREAK";
|
||
|
|
default : _zz_13__string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_14_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_14__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_14__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_14__string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_14__string = "EBREAK";
|
||
|
|
default : _zz_14__string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
|
||
|
|
default : decode_SRC2_CTRL_string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_15_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC ";
|
||
|
|
default : _zz_15__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_16_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_16__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_16__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_16__string = "PC ";
|
||
|
|
default : _zz_16__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_17_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC ";
|
||
|
|
default : _zz_17__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
|
||
|
|
default : decode_ALU_CTRL_string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_18_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE ";
|
||
|
|
default : _zz_18__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_19_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE ";
|
||
|
|
default : _zz_19__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_20_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_20__string = "BITWISE ";
|
||
|
|
default : _zz_20__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK";
|
||
|
|
default : execute_ENV_CTRL_string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_23_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_23__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_23__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_23__string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_23__string = "EBREAK";
|
||
|
|
default : _zz_23__string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
|
||
|
|
default : execute_BRANCH_CTRL_string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_26_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_26__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_26__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_26__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_26__string = "JALR";
|
||
|
|
default : _zz_26__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
|
||
|
|
default : execute_SHIFT_CTRL_string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_29_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_29__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_29__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_29__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_29__string = "SRA_1 ";
|
||
|
|
default : _zz_29__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
|
||
|
|
default : execute_SRC2_CTRL_string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_33_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_33__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_33__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_33__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_33__string = "PC ";
|
||
|
|
default : _zz_33__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
|
||
|
|
default : execute_SRC1_CTRL_string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_35_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_35__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_35__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_35__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_35__string = "URS1 ";
|
||
|
|
default : _zz_35__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
|
||
|
|
default : execute_ALU_CTRL_string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_37_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_37__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_37__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_37__string = "BITWISE ";
|
||
|
|
default : _zz_37__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(execute_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : execute_ALU_BITWISE_CTRL_string = "SRC1 ";
|
||
|
|
default : execute_ALU_BITWISE_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_39_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39__string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_39__string = "SRC1 ";
|
||
|
|
default : _zz_39__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_44_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_44__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_44__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_44__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_44__string = "JALR";
|
||
|
|
default : _zz_44__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_45_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE ";
|
||
|
|
default : _zz_45__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_49_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_49__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_49__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_49__string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_49__string = "SRC1 ";
|
||
|
|
default : _zz_49__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_50_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50__string = "SRA_1 ";
|
||
|
|
default : _zz_50__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_52_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_52__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_52__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_52__string = "URS1 ";
|
||
|
|
default : _zz_52__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_53_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_53__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_53__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_53__string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_53__string = "EBREAK";
|
||
|
|
default : _zz_53__string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_55_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_55__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_55__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_55__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_55__string = "PC ";
|
||
|
|
default : _zz_55__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
|
||
|
|
default : decode_BRANCH_CTRL_string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_60_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_60__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_60__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_60__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_60__string = "JALR";
|
||
|
|
default : _zz_60__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_113_)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : _zz_113__string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : _zz_113__string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : _zz_113__string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : _zz_113__string = "PC ";
|
||
|
|
default : _zz_113__string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_114_)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : _zz_114__string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : _zz_114__string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : _zz_114__string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : _zz_114__string = "EBREAK";
|
||
|
|
default : _zz_114__string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_115_)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : _zz_115__string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : _zz_115__string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_115__string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_115__string = "URS1 ";
|
||
|
|
default : _zz_115__string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_116_)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_116__string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_116__string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_116__string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_116__string = "SRA_1 ";
|
||
|
|
default : _zz_116__string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_117_)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_117__string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_117__string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_117__string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : _zz_117__string = "SRC1 ";
|
||
|
|
default : _zz_117__string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_118_)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_118__string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_118__string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_118__string = "BITWISE ";
|
||
|
|
default : _zz_118__string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(_zz_119_)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : _zz_119__string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : _zz_119__string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : _zz_119__string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : _zz_119__string = "JALR";
|
||
|
|
default : _zz_119__string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
|
||
|
|
default : decode_to_execute_ALU_CTRL_string = "????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
|
||
|
|
`Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
|
||
|
|
default : decode_to_execute_SRC2_CTRL_string = "???";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_ENV_CTRL)
|
||
|
|
`EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL ";
|
||
|
|
`EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK";
|
||
|
|
default : decode_to_execute_ENV_CTRL_string = "??????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
|
||
|
|
default : decode_to_execute_BRANCH_CTRL_string = "????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
|
||
|
|
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_SRC1 : decode_to_execute_ALU_BITWISE_CTRL_string = "SRC1 ";
|
||
|
|
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
always @(*) begin
|
||
|
|
case(decode_to_execute_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
|
||
|
|
`Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
|
||
|
|
default : decode_to_execute_SRC1_CTRL_string = "????????????";
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
`endif
|
||
|
|
|
||
|
|
assign decode_SRC1_CTRL = _zz_1_;
|
||
|
|
assign _zz_2_ = _zz_3_;
|
||
|
|
assign decode_ALU_BITWISE_CTRL = _zz_4_;
|
||
|
|
assign _zz_5_ = _zz_6_;
|
||
|
|
assign decode_SHIFT_CTRL = _zz_7_;
|
||
|
|
assign _zz_8_ = _zz_9_;
|
||
|
|
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
|
||
|
|
assign decode_FORMAL_PC_NEXT = _zz_62_;
|
||
|
|
assign _zz_10_ = _zz_11_;
|
||
|
|
assign decode_ENV_CTRL = _zz_12_;
|
||
|
|
assign _zz_13_ = _zz_14_;
|
||
|
|
assign decode_FLUSH_ALL = _zz_47_;
|
||
|
|
assign decode_PREDICTION_HAD_BRANCHED2 = _zz_28_;
|
||
|
|
assign decode_MEMORY_ENABLE = _zz_46_;
|
||
|
|
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
|
||
|
|
assign decode_IS_CSR = _zz_43_;
|
||
|
|
assign decode_SRC2_CTRL = _zz_15_;
|
||
|
|
assign _zz_16_ = _zz_17_;
|
||
|
|
assign decode_CSR_WRITE_OPCODE = _zz_22_;
|
||
|
|
assign decode_CSR_READ_OPCODE = _zz_21_;
|
||
|
|
assign decode_ALU_CTRL = _zz_18_;
|
||
|
|
assign _zz_19_ = _zz_20_;
|
||
|
|
assign decode_SRC_USE_SUB_LESS = _zz_48_;
|
||
|
|
assign decode_SRC_LESS_UNSIGNED = _zz_54_;
|
||
|
|
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
|
||
|
|
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
|
||
|
|
assign execute_IS_CSR = decode_to_execute_IS_CSR;
|
||
|
|
assign execute_ENV_CTRL = _zz_23_;
|
||
|
|
assign execute_BRANCH_CALC = _zz_24_;
|
||
|
|
assign execute_BRANCH_DO = _zz_25_;
|
||
|
|
assign execute_PC = decode_to_execute_PC;
|
||
|
|
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
|
||
|
|
assign execute_RS1 = _zz_42_;
|
||
|
|
assign execute_BRANCH_COND_RESULT = _zz_27_;
|
||
|
|
assign execute_BRANCH_CTRL = _zz_26_;
|
||
|
|
assign execute_SHIFT_CTRL = _zz_29_;
|
||
|
|
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
|
||
|
|
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
|
||
|
|
assign execute_SRC2_CTRL = _zz_33_;
|
||
|
|
assign execute_SRC1_CTRL = _zz_35_;
|
||
|
|
assign execute_SRC_ADD_SUB = _zz_32_;
|
||
|
|
assign execute_SRC_LESS = _zz_30_;
|
||
|
|
assign execute_ALU_CTRL = _zz_37_;
|
||
|
|
assign execute_SRC2 = _zz_34_;
|
||
|
|
assign execute_SRC1 = _zz_36_;
|
||
|
|
assign execute_ALU_BITWISE_CTRL = _zz_39_;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_40_ = 1'b0;
|
||
|
|
if(execute_RegFilePlugin_regFileWrite_valid)begin
|
||
|
|
_zz_40_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
decode_REGFILE_WRITE_VALID = _zz_51_;
|
||
|
|
if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
|
||
|
|
decode_REGFILE_WRITE_VALID = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_56_ = execute_REGFILE_WRITE_DATA;
|
||
|
|
execute_arbitration_haltItself = 1'b0;
|
||
|
|
_zz_158_ = 1'b0;
|
||
|
|
if((execute_arbitration_isValid && execute_FLUSH_ALL))begin
|
||
|
|
_zz_158_ = 1'b1;
|
||
|
|
if((! IBusCachedPlugin_cache_io_flush_cmd_ready))begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent)))begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_INSTRUCTION[5])) && (! dBus_rsp_ready)))begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin
|
||
|
|
_zz_56_ = execute_DBusSimplePlugin_rspFormated;
|
||
|
|
end
|
||
|
|
if(_zz_179_)begin
|
||
|
|
_zz_56_ = _zz_128_;
|
||
|
|
if(_zz_180_)begin
|
||
|
|
if(! execute_LightShifterPlugin_done) begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if((execute_arbitration_isValid && execute_IS_CSR))begin
|
||
|
|
_zz_56_ = execute_CsrPlugin_readData;
|
||
|
|
if(execute_CsrPlugin_blockedBySideEffects)begin
|
||
|
|
execute_arbitration_haltItself = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_MEMORY_ADDRESS_LOW = _zz_58_;
|
||
|
|
assign execute_MEMORY_READ_DATA = _zz_57_;
|
||
|
|
assign execute_REGFILE_WRITE_DATA = _zz_38_;
|
||
|
|
assign execute_RS2 = _zz_41_;
|
||
|
|
assign execute_SRC_ADD = _zz_31_;
|
||
|
|
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
|
||
|
|
assign execute_ALIGNEMENT_FAULT = _zz_59_;
|
||
|
|
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
|
||
|
|
assign execute_FLUSH_ALL = decode_to_execute_FLUSH_ALL;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusCachedPlugin_rsp_issueDetected = 1'b0;
|
||
|
|
IBusCachedPlugin_rsp_redoFetch = 1'b0;
|
||
|
|
if(((_zz_171_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! 1'b0)))begin
|
||
|
|
IBusCachedPlugin_rsp_issueDetected = 1'b1;
|
||
|
|
IBusCachedPlugin_rsp_redoFetch = IBusCachedPlugin_iBusRsp_readyForError;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign decode_BRANCH_CTRL = _zz_60_;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_61_ = decode_FORMAL_PC_NEXT;
|
||
|
|
if(_zz_67_)begin
|
||
|
|
_zz_61_ = _zz_68_;
|
||
|
|
end
|
||
|
|
if(_zz_70_)begin
|
||
|
|
_zz_61_ = _zz_71_;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign decode_PC = _zz_64_;
|
||
|
|
assign decode_INSTRUCTION = _zz_63_;
|
||
|
|
assign decode_arbitration_haltItself = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_haltByOther = 1'b0;
|
||
|
|
if((CsrPlugin_interrupt && decode_arbitration_isValid))begin
|
||
|
|
decode_arbitration_haltByOther = 1'b1;
|
||
|
|
end
|
||
|
|
if(1'b0)begin
|
||
|
|
decode_arbitration_haltByOther = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_removeIt = 1'b0;
|
||
|
|
if(decode_arbitration_isFlushed)begin
|
||
|
|
decode_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
decode_arbitration_flushAll = 1'b0;
|
||
|
|
execute_arbitration_removeIt = 1'b0;
|
||
|
|
_zz_76_ = 1'b0;
|
||
|
|
_zz_77_ = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
||
|
|
if(_zz_74_)begin
|
||
|
|
decode_arbitration_flushAll = 1'b1;
|
||
|
|
end
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
|
||
|
|
if(execute_exception_agregat_valid)begin
|
||
|
|
decode_arbitration_flushAll = 1'b1;
|
||
|
|
execute_arbitration_removeIt = 1'b1;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_181_)begin
|
||
|
|
_zz_76_ = 1'b1;
|
||
|
|
_zz_77_ = {CsrPlugin_mtvec_base,(2'b00)};
|
||
|
|
decode_arbitration_flushAll = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_182_)begin
|
||
|
|
_zz_77_ = CsrPlugin_mepc;
|
||
|
|
_zz_76_ = 1'b1;
|
||
|
|
decode_arbitration_flushAll = 1'b1;
|
||
|
|
end
|
||
|
|
if(execute_arbitration_isFlushed)begin
|
||
|
|
execute_arbitration_removeIt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign decode_arbitration_redoIt = 1'b0;
|
||
|
|
assign execute_arbitration_haltByOther = 1'b0;
|
||
|
|
assign execute_arbitration_flushAll = 1'b0;
|
||
|
|
assign execute_arbitration_redoIt = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_65_ = 1'b0;
|
||
|
|
if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin
|
||
|
|
_zz_65_ = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_66_ = 1'b0;
|
||
|
|
assign IBusCachedPlugin_jump_pcLoad_valid = ({_zz_76_,{_zz_74_,{_zz_70_,_zz_67_}}} != (4'b0000));
|
||
|
|
assign _zz_80_ = {_zz_67_,{_zz_70_,{_zz_76_,_zz_74_}}};
|
||
|
|
assign _zz_81_ = (_zz_80_ & (~ _zz_189_));
|
||
|
|
assign _zz_82_ = _zz_81_[3];
|
||
|
|
assign _zz_83_ = (_zz_81_[1] || _zz_82_);
|
||
|
|
assign _zz_84_ = (_zz_81_[2] || _zz_82_);
|
||
|
|
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_176_;
|
||
|
|
assign _zz_85_ = (! _zz_65_);
|
||
|
|
assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_85_);
|
||
|
|
assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_85_);
|
||
|
|
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusCachedPlugin_fetchPc_propagatePc = 1'b0;
|
||
|
|
if((IBusCachedPlugin_iBusRsp_stages_1_input_valid && IBusCachedPlugin_iBusRsp_stages_1_input_ready))begin
|
||
|
|
IBusCachedPlugin_fetchPc_propagatePc = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_191_);
|
||
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b0;
|
||
|
|
if(IBusCachedPlugin_fetchPc_propagatePc)begin
|
||
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b1;
|
||
|
|
end
|
||
|
|
if(IBusCachedPlugin_jump_pcLoad_valid)begin
|
||
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b1;
|
||
|
|
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
|
||
|
|
end
|
||
|
|
if(_zz_183_)begin
|
||
|
|
IBusCachedPlugin_fetchPc_samplePcNext = 1'b1;
|
||
|
|
end
|
||
|
|
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
|
||
|
|
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_86_;
|
||
|
|
assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
|
||
|
|
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
|
||
|
|
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin
|
||
|
|
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_87_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_87_);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_87_);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
|
||
|
|
if(((IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid && (! 1'b1)) && (! 1'b0)))begin
|
||
|
|
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_88_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_88_);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_88_);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
|
||
|
|
always @ (*) begin
|
||
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0;
|
||
|
|
if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin
|
||
|
|
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_89_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_89_);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_89_);
|
||
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_90_;
|
||
|
|
assign _zz_90_ = ((1'b0 && (! _zz_91_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
|
||
|
|
assign _zz_91_ = _zz_92_;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_91_;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_93_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
|
||
|
|
assign _zz_93_ = _zz_94_;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_93_;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_95_;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck);
|
||
|
|
assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved));
|
||
|
|
assign _zz_64_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
|
||
|
|
assign _zz_63_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
|
||
|
|
assign _zz_62_ = (decode_PC + (32'b00000000000000000000000000000100));
|
||
|
|
assign _zz_96_ = _zz_192_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_97_[18] = _zz_96_;
|
||
|
|
_zz_97_[17] = _zz_96_;
|
||
|
|
_zz_97_[16] = _zz_96_;
|
||
|
|
_zz_97_[15] = _zz_96_;
|
||
|
|
_zz_97_[14] = _zz_96_;
|
||
|
|
_zz_97_[13] = _zz_96_;
|
||
|
|
_zz_97_[12] = _zz_96_;
|
||
|
|
_zz_97_[11] = _zz_96_;
|
||
|
|
_zz_97_[10] = _zz_96_;
|
||
|
|
_zz_97_[9] = _zz_96_;
|
||
|
|
_zz_97_[8] = _zz_96_;
|
||
|
|
_zz_97_[7] = _zz_96_;
|
||
|
|
_zz_97_[6] = _zz_96_;
|
||
|
|
_zz_97_[5] = _zz_96_;
|
||
|
|
_zz_97_[4] = _zz_96_;
|
||
|
|
_zz_97_[3] = _zz_96_;
|
||
|
|
_zz_97_[2] = _zz_96_;
|
||
|
|
_zz_97_[1] = _zz_96_;
|
||
|
|
_zz_97_[0] = _zz_96_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_69_ = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_193_[31]));
|
||
|
|
assign _zz_67_ = (_zz_69_ && decode_arbitration_isFiring);
|
||
|
|
assign _zz_98_ = _zz_194_[19];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_99_[10] = _zz_98_;
|
||
|
|
_zz_99_[9] = _zz_98_;
|
||
|
|
_zz_99_[8] = _zz_98_;
|
||
|
|
_zz_99_[7] = _zz_98_;
|
||
|
|
_zz_99_[6] = _zz_98_;
|
||
|
|
_zz_99_[5] = _zz_98_;
|
||
|
|
_zz_99_[4] = _zz_98_;
|
||
|
|
_zz_99_[3] = _zz_98_;
|
||
|
|
_zz_99_[2] = _zz_98_;
|
||
|
|
_zz_99_[1] = _zz_98_;
|
||
|
|
_zz_99_[0] = _zz_98_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_100_ = _zz_195_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_101_[18] = _zz_100_;
|
||
|
|
_zz_101_[17] = _zz_100_;
|
||
|
|
_zz_101_[16] = _zz_100_;
|
||
|
|
_zz_101_[15] = _zz_100_;
|
||
|
|
_zz_101_[14] = _zz_100_;
|
||
|
|
_zz_101_[13] = _zz_100_;
|
||
|
|
_zz_101_[12] = _zz_100_;
|
||
|
|
_zz_101_[11] = _zz_100_;
|
||
|
|
_zz_101_[10] = _zz_100_;
|
||
|
|
_zz_101_[9] = _zz_100_;
|
||
|
|
_zz_101_[8] = _zz_100_;
|
||
|
|
_zz_101_[7] = _zz_100_;
|
||
|
|
_zz_101_[6] = _zz_100_;
|
||
|
|
_zz_101_[5] = _zz_100_;
|
||
|
|
_zz_101_[4] = _zz_100_;
|
||
|
|
_zz_101_[3] = _zz_100_;
|
||
|
|
_zz_101_[2] = _zz_100_;
|
||
|
|
_zz_101_[1] = _zz_100_;
|
||
|
|
_zz_101_[0] = _zz_100_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_68_ = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_99_,{{{_zz_239_,_zz_240_},_zz_241_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_101_,{{{_zz_242_,_zz_243_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
|
||
|
|
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
|
||
|
|
always @ (*) begin
|
||
|
|
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
|
||
|
|
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
|
||
|
|
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
|
||
|
|
assign _zz_159_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
|
||
|
|
assign _zz_162_ = (IBusCachedPlugin_jump_pcLoad_valid || _zz_66_);
|
||
|
|
assign _zz_163_ = (32'b00000000000000000000000000000000);
|
||
|
|
assign _zz_160_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
|
||
|
|
assign _zz_161_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
|
||
|
|
assign _zz_171_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
|
||
|
|
assign _zz_172_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
|
||
|
|
assign _zz_173_ = (CsrPlugin_privilege == (2'b00));
|
||
|
|
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
|
||
|
|
assign _zz_70_ = IBusCachedPlugin_rsp_redoFetch;
|
||
|
|
assign _zz_71_ = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
|
||
|
|
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
|
||
|
|
assign _zz_164_ = _zz_72_[31];
|
||
|
|
assign _zz_165_ = 1'b1;
|
||
|
|
assign _zz_166_ = 1'b1;
|
||
|
|
assign _zz_167_ = 1'b1;
|
||
|
|
assign _zz_168_ = 1'b1;
|
||
|
|
assign _zz_169_ = 1'b0;
|
||
|
|
assign _zz_170_ = 1'b1;
|
||
|
|
assign _zz_59_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
|
||
|
|
assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_ALIGNEMENT_FAULT)) && (! execute_DBusSimplePlugin_cmdSent));
|
||
|
|
assign dBus_cmd_payload_wr = execute_INSTRUCTION[5];
|
||
|
|
assign dBus_cmd_payload_address = execute_SRC_ADD;
|
||
|
|
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
|
||
|
|
always @ (*) begin
|
||
|
|
case(dBus_cmd_payload_size)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_102_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_102_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_102_ = execute_RS2[31 : 0];
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign dBus_cmd_payload_data = _zz_102_;
|
||
|
|
assign _zz_58_ = dBus_cmd_payload_address[1 : 0];
|
||
|
|
always @ (*) begin
|
||
|
|
case(dBus_cmd_payload_size)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_103_ = (4'b0001);
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_103_ = (4'b0011);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_103_ = (4'b1111);
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_DBusSimplePlugin_formalMask = (_zz_103_ <<< dBus_cmd_payload_address[1 : 0]);
|
||
|
|
assign _zz_57_ = dBus_rsp_data;
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_73_ = execute_ALIGNEMENT_FAULT;
|
||
|
|
if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers))))begin
|
||
|
|
_zz_73_ = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA;
|
||
|
|
case(execute_MEMORY_ADDRESS_LOW)
|
||
|
|
2'b01 : begin
|
||
|
|
execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8];
|
||
|
|
end
|
||
|
|
2'b10 : begin
|
||
|
|
execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16];
|
||
|
|
end
|
||
|
|
2'b11 : begin
|
||
|
|
execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24];
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_104_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14]));
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_105_[31] = _zz_104_;
|
||
|
|
_zz_105_[30] = _zz_104_;
|
||
|
|
_zz_105_[29] = _zz_104_;
|
||
|
|
_zz_105_[28] = _zz_104_;
|
||
|
|
_zz_105_[27] = _zz_104_;
|
||
|
|
_zz_105_[26] = _zz_104_;
|
||
|
|
_zz_105_[25] = _zz_104_;
|
||
|
|
_zz_105_[24] = _zz_104_;
|
||
|
|
_zz_105_[23] = _zz_104_;
|
||
|
|
_zz_105_[22] = _zz_104_;
|
||
|
|
_zz_105_[21] = _zz_104_;
|
||
|
|
_zz_105_[20] = _zz_104_;
|
||
|
|
_zz_105_[19] = _zz_104_;
|
||
|
|
_zz_105_[18] = _zz_104_;
|
||
|
|
_zz_105_[17] = _zz_104_;
|
||
|
|
_zz_105_[16] = _zz_104_;
|
||
|
|
_zz_105_[15] = _zz_104_;
|
||
|
|
_zz_105_[14] = _zz_104_;
|
||
|
|
_zz_105_[13] = _zz_104_;
|
||
|
|
_zz_105_[12] = _zz_104_;
|
||
|
|
_zz_105_[11] = _zz_104_;
|
||
|
|
_zz_105_[10] = _zz_104_;
|
||
|
|
_zz_105_[9] = _zz_104_;
|
||
|
|
_zz_105_[8] = _zz_104_;
|
||
|
|
_zz_105_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0];
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_106_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14]));
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_107_[31] = _zz_106_;
|
||
|
|
_zz_107_[30] = _zz_106_;
|
||
|
|
_zz_107_[29] = _zz_106_;
|
||
|
|
_zz_107_[28] = _zz_106_;
|
||
|
|
_zz_107_[27] = _zz_106_;
|
||
|
|
_zz_107_[26] = _zz_106_;
|
||
|
|
_zz_107_[25] = _zz_106_;
|
||
|
|
_zz_107_[24] = _zz_106_;
|
||
|
|
_zz_107_[23] = _zz_106_;
|
||
|
|
_zz_107_[22] = _zz_106_;
|
||
|
|
_zz_107_[21] = _zz_106_;
|
||
|
|
_zz_107_[20] = _zz_106_;
|
||
|
|
_zz_107_[19] = _zz_106_;
|
||
|
|
_zz_107_[18] = _zz_106_;
|
||
|
|
_zz_107_[17] = _zz_106_;
|
||
|
|
_zz_107_[16] = _zz_106_;
|
||
|
|
_zz_107_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0];
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(_zz_186_)
|
||
|
|
2'b00 : begin
|
||
|
|
execute_DBusSimplePlugin_rspFormated = _zz_105_;
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
execute_DBusSimplePlugin_rspFormated = _zz_107_;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_72_ = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
|
||
|
|
assign _zz_109_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000));
|
||
|
|
assign _zz_110_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
|
||
|
|
assign _zz_111_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
|
||
|
|
assign _zz_112_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
|
||
|
|
assign _zz_108_ = {({(_zz_244_ == _zz_245_),(_zz_246_ == _zz_247_)} != (2'b00)),{((_zz_248_ == _zz_249_) != (1'b0)),{({_zz_250_,_zz_251_} != (4'b0000)),{(_zz_252_ != _zz_253_),{_zz_254_,{_zz_255_,_zz_256_}}}}}};
|
||
|
|
assign _zz_113_ = _zz_108_[2 : 1];
|
||
|
|
assign _zz_55_ = _zz_113_;
|
||
|
|
assign _zz_54_ = _zz_196_[0];
|
||
|
|
assign _zz_114_ = _zz_108_[5 : 4];
|
||
|
|
assign _zz_53_ = _zz_114_;
|
||
|
|
assign _zz_115_ = _zz_108_[7 : 6];
|
||
|
|
assign _zz_52_ = _zz_115_;
|
||
|
|
assign _zz_51_ = _zz_197_[0];
|
||
|
|
assign _zz_116_ = _zz_108_[11 : 10];
|
||
|
|
assign _zz_50_ = _zz_116_;
|
||
|
|
assign _zz_117_ = _zz_108_[13 : 12];
|
||
|
|
assign _zz_49_ = _zz_117_;
|
||
|
|
assign _zz_48_ = _zz_198_[0];
|
||
|
|
assign _zz_47_ = _zz_199_[0];
|
||
|
|
assign _zz_46_ = _zz_200_[0];
|
||
|
|
assign _zz_118_ = _zz_108_[18 : 17];
|
||
|
|
assign _zz_45_ = _zz_118_;
|
||
|
|
assign _zz_119_ = _zz_108_[20 : 19];
|
||
|
|
assign _zz_44_ = _zz_119_;
|
||
|
|
assign _zz_43_ = _zz_201_[0];
|
||
|
|
assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15];
|
||
|
|
assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20];
|
||
|
|
assign _zz_120_ = (! execute_arbitration_isStuck);
|
||
|
|
assign execute_RegFilePlugin_rs1Data = _zz_174_;
|
||
|
|
assign execute_RegFilePlugin_rs2Data = _zz_175_;
|
||
|
|
assign _zz_42_ = execute_RegFilePlugin_rs1Data;
|
||
|
|
assign _zz_41_ = execute_RegFilePlugin_rs2Data;
|
||
|
|
assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring);
|
||
|
|
assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7];
|
||
|
|
assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_56_;
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_ALU_BITWISE_CTRL)
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
|
||
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
|
||
|
|
end
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
|
||
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
|
||
|
|
end
|
||
|
|
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin
|
||
|
|
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
execute_IntAluPlugin_bitwise = execute_SRC1;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_ALU_CTRL)
|
||
|
|
`AluCtrlEnum_defaultEncoding_BITWISE : begin
|
||
|
|
_zz_121_ = execute_IntAluPlugin_bitwise;
|
||
|
|
end
|
||
|
|
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
|
||
|
|
_zz_121_ = {31'd0, _zz_202_};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_121_ = execute_SRC_ADD_SUB;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_38_ = _zz_121_;
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_SRC1_CTRL)
|
||
|
|
`Src1CtrlEnum_defaultEncoding_RS : begin
|
||
|
|
_zz_122_ = execute_RS1;
|
||
|
|
end
|
||
|
|
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
|
||
|
|
_zz_122_ = {29'd0, _zz_203_};
|
||
|
|
end
|
||
|
|
`Src1CtrlEnum_defaultEncoding_IMU : begin
|
||
|
|
_zz_122_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_122_ = {27'd0, _zz_204_};
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_36_ = _zz_122_;
|
||
|
|
assign _zz_123_ = _zz_205_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_124_[19] = _zz_123_;
|
||
|
|
_zz_124_[18] = _zz_123_;
|
||
|
|
_zz_124_[17] = _zz_123_;
|
||
|
|
_zz_124_[16] = _zz_123_;
|
||
|
|
_zz_124_[15] = _zz_123_;
|
||
|
|
_zz_124_[14] = _zz_123_;
|
||
|
|
_zz_124_[13] = _zz_123_;
|
||
|
|
_zz_124_[12] = _zz_123_;
|
||
|
|
_zz_124_[11] = _zz_123_;
|
||
|
|
_zz_124_[10] = _zz_123_;
|
||
|
|
_zz_124_[9] = _zz_123_;
|
||
|
|
_zz_124_[8] = _zz_123_;
|
||
|
|
_zz_124_[7] = _zz_123_;
|
||
|
|
_zz_124_[6] = _zz_123_;
|
||
|
|
_zz_124_[5] = _zz_123_;
|
||
|
|
_zz_124_[4] = _zz_123_;
|
||
|
|
_zz_124_[3] = _zz_123_;
|
||
|
|
_zz_124_[2] = _zz_123_;
|
||
|
|
_zz_124_[1] = _zz_123_;
|
||
|
|
_zz_124_[0] = _zz_123_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_125_ = _zz_206_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_126_[19] = _zz_125_;
|
||
|
|
_zz_126_[18] = _zz_125_;
|
||
|
|
_zz_126_[17] = _zz_125_;
|
||
|
|
_zz_126_[16] = _zz_125_;
|
||
|
|
_zz_126_[15] = _zz_125_;
|
||
|
|
_zz_126_[14] = _zz_125_;
|
||
|
|
_zz_126_[13] = _zz_125_;
|
||
|
|
_zz_126_[12] = _zz_125_;
|
||
|
|
_zz_126_[11] = _zz_125_;
|
||
|
|
_zz_126_[10] = _zz_125_;
|
||
|
|
_zz_126_[9] = _zz_125_;
|
||
|
|
_zz_126_[8] = _zz_125_;
|
||
|
|
_zz_126_[7] = _zz_125_;
|
||
|
|
_zz_126_[6] = _zz_125_;
|
||
|
|
_zz_126_[5] = _zz_125_;
|
||
|
|
_zz_126_[4] = _zz_125_;
|
||
|
|
_zz_126_[3] = _zz_125_;
|
||
|
|
_zz_126_[2] = _zz_125_;
|
||
|
|
_zz_126_[1] = _zz_125_;
|
||
|
|
_zz_126_[0] = _zz_125_;
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_SRC2_CTRL)
|
||
|
|
`Src2CtrlEnum_defaultEncoding_RS : begin
|
||
|
|
_zz_127_ = execute_RS2;
|
||
|
|
end
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMI : begin
|
||
|
|
_zz_127_ = {_zz_124_,execute_INSTRUCTION[31 : 20]};
|
||
|
|
end
|
||
|
|
`Src2CtrlEnum_defaultEncoding_IMS : begin
|
||
|
|
_zz_127_ = {_zz_126_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_127_ = execute_PC;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_34_ = _zz_127_;
|
||
|
|
assign execute_SrcPlugin_addSub = _zz_207_;
|
||
|
|
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
|
||
|
|
assign _zz_32_ = execute_SrcPlugin_addSub;
|
||
|
|
assign _zz_31_ = execute_SrcPlugin_addSub;
|
||
|
|
assign _zz_30_ = execute_SrcPlugin_less;
|
||
|
|
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
|
||
|
|
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
|
||
|
|
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1);
|
||
|
|
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_SHIFT_CTRL)
|
||
|
|
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
|
||
|
|
_zz_128_ = (execute_LightShifterPlugin_shiftInput <<< 1);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_128_ = _zz_215_;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_28_ = _zz_69_;
|
||
|
|
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
|
||
|
|
assign _zz_129_ = execute_INSTRUCTION[14 : 12];
|
||
|
|
always @ (*) begin
|
||
|
|
if((_zz_129_ == (3'b000))) begin
|
||
|
|
_zz_130_ = execute_BranchPlugin_eq;
|
||
|
|
end else if((_zz_129_ == (3'b001))) begin
|
||
|
|
_zz_130_ = (! execute_BranchPlugin_eq);
|
||
|
|
end else if((((_zz_129_ & (3'b101)) == (3'b101)))) begin
|
||
|
|
_zz_130_ = (! execute_SRC_LESS);
|
||
|
|
end else begin
|
||
|
|
_zz_130_ = execute_SRC_LESS;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_INC : begin
|
||
|
|
_zz_131_ = 1'b0;
|
||
|
|
end
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
||
|
|
_zz_131_ = 1'b1;
|
||
|
|
end
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
||
|
|
_zz_131_ = 1'b1;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_131_ = _zz_130_;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_27_ = _zz_131_;
|
||
|
|
assign _zz_132_ = _zz_217_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_133_[19] = _zz_132_;
|
||
|
|
_zz_133_[18] = _zz_132_;
|
||
|
|
_zz_133_[17] = _zz_132_;
|
||
|
|
_zz_133_[16] = _zz_132_;
|
||
|
|
_zz_133_[15] = _zz_132_;
|
||
|
|
_zz_133_[14] = _zz_132_;
|
||
|
|
_zz_133_[13] = _zz_132_;
|
||
|
|
_zz_133_[12] = _zz_132_;
|
||
|
|
_zz_133_[11] = _zz_132_;
|
||
|
|
_zz_133_[10] = _zz_132_;
|
||
|
|
_zz_133_[9] = _zz_132_;
|
||
|
|
_zz_133_[8] = _zz_132_;
|
||
|
|
_zz_133_[7] = _zz_132_;
|
||
|
|
_zz_133_[6] = _zz_132_;
|
||
|
|
_zz_133_[5] = _zz_132_;
|
||
|
|
_zz_133_[4] = _zz_132_;
|
||
|
|
_zz_133_[3] = _zz_132_;
|
||
|
|
_zz_133_[2] = _zz_132_;
|
||
|
|
_zz_133_[1] = _zz_132_;
|
||
|
|
_zz_133_[0] = _zz_132_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_134_ = _zz_218_[19];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_135_[10] = _zz_134_;
|
||
|
|
_zz_135_[9] = _zz_134_;
|
||
|
|
_zz_135_[8] = _zz_134_;
|
||
|
|
_zz_135_[7] = _zz_134_;
|
||
|
|
_zz_135_[6] = _zz_134_;
|
||
|
|
_zz_135_[5] = _zz_134_;
|
||
|
|
_zz_135_[4] = _zz_134_;
|
||
|
|
_zz_135_[3] = _zz_134_;
|
||
|
|
_zz_135_[2] = _zz_134_;
|
||
|
|
_zz_135_[1] = _zz_134_;
|
||
|
|
_zz_135_[0] = _zz_134_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_136_ = _zz_219_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_137_[18] = _zz_136_;
|
||
|
|
_zz_137_[17] = _zz_136_;
|
||
|
|
_zz_137_[16] = _zz_136_;
|
||
|
|
_zz_137_[15] = _zz_136_;
|
||
|
|
_zz_137_[14] = _zz_136_;
|
||
|
|
_zz_137_[13] = _zz_136_;
|
||
|
|
_zz_137_[12] = _zz_136_;
|
||
|
|
_zz_137_[11] = _zz_136_;
|
||
|
|
_zz_137_[10] = _zz_136_;
|
||
|
|
_zz_137_[9] = _zz_136_;
|
||
|
|
_zz_137_[8] = _zz_136_;
|
||
|
|
_zz_137_[7] = _zz_136_;
|
||
|
|
_zz_137_[6] = _zz_136_;
|
||
|
|
_zz_137_[5] = _zz_136_;
|
||
|
|
_zz_137_[4] = _zz_136_;
|
||
|
|
_zz_137_[3] = _zz_136_;
|
||
|
|
_zz_137_[2] = _zz_136_;
|
||
|
|
_zz_137_[1] = _zz_136_;
|
||
|
|
_zz_137_[0] = _zz_136_;
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
||
|
|
_zz_138_ = (_zz_220_[1] ^ execute_RS1[1]);
|
||
|
|
end
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JAL : begin
|
||
|
|
_zz_138_ = _zz_221_[1];
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_138_ = _zz_222_[1];
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138_);
|
||
|
|
assign _zz_25_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
|
||
|
|
always @ (*) begin
|
||
|
|
case(execute_BRANCH_CTRL)
|
||
|
|
`BranchCtrlEnum_defaultEncoding_JALR : begin
|
||
|
|
execute_BranchPlugin_branch_src1 = execute_RS1;
|
||
|
|
execute_BranchPlugin_branch_src2 = {_zz_140_,execute_INSTRUCTION[31 : 20]};
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
execute_BranchPlugin_branch_src1 = execute_PC;
|
||
|
|
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142_,{{{_zz_348_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144_,{{{_zz_349_,_zz_350_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
|
||
|
|
if((execute_PREDICTION_HAD_BRANCHED2 && (! execute_BranchPlugin_missAlignedTarget)))begin
|
||
|
|
execute_BranchPlugin_branch_src2 = {29'd0, _zz_226_};
|
||
|
|
end
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_139_ = _zz_223_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_140_[19] = _zz_139_;
|
||
|
|
_zz_140_[18] = _zz_139_;
|
||
|
|
_zz_140_[17] = _zz_139_;
|
||
|
|
_zz_140_[16] = _zz_139_;
|
||
|
|
_zz_140_[15] = _zz_139_;
|
||
|
|
_zz_140_[14] = _zz_139_;
|
||
|
|
_zz_140_[13] = _zz_139_;
|
||
|
|
_zz_140_[12] = _zz_139_;
|
||
|
|
_zz_140_[11] = _zz_139_;
|
||
|
|
_zz_140_[10] = _zz_139_;
|
||
|
|
_zz_140_[9] = _zz_139_;
|
||
|
|
_zz_140_[8] = _zz_139_;
|
||
|
|
_zz_140_[7] = _zz_139_;
|
||
|
|
_zz_140_[6] = _zz_139_;
|
||
|
|
_zz_140_[5] = _zz_139_;
|
||
|
|
_zz_140_[4] = _zz_139_;
|
||
|
|
_zz_140_[3] = _zz_139_;
|
||
|
|
_zz_140_[2] = _zz_139_;
|
||
|
|
_zz_140_[1] = _zz_139_;
|
||
|
|
_zz_140_[0] = _zz_139_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_141_ = _zz_224_[19];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_142_[10] = _zz_141_;
|
||
|
|
_zz_142_[9] = _zz_141_;
|
||
|
|
_zz_142_[8] = _zz_141_;
|
||
|
|
_zz_142_[7] = _zz_141_;
|
||
|
|
_zz_142_[6] = _zz_141_;
|
||
|
|
_zz_142_[5] = _zz_141_;
|
||
|
|
_zz_142_[4] = _zz_141_;
|
||
|
|
_zz_142_[3] = _zz_141_;
|
||
|
|
_zz_142_[2] = _zz_141_;
|
||
|
|
_zz_142_[1] = _zz_141_;
|
||
|
|
_zz_142_[0] = _zz_141_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign _zz_143_ = _zz_225_[11];
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_144_[18] = _zz_143_;
|
||
|
|
_zz_144_[17] = _zz_143_;
|
||
|
|
_zz_144_[16] = _zz_143_;
|
||
|
|
_zz_144_[15] = _zz_143_;
|
||
|
|
_zz_144_[14] = _zz_143_;
|
||
|
|
_zz_144_[13] = _zz_143_;
|
||
|
|
_zz_144_[12] = _zz_143_;
|
||
|
|
_zz_144_[11] = _zz_143_;
|
||
|
|
_zz_144_[10] = _zz_143_;
|
||
|
|
_zz_144_[9] = _zz_143_;
|
||
|
|
_zz_144_[8] = _zz_143_;
|
||
|
|
_zz_144_[7] = _zz_143_;
|
||
|
|
_zz_144_[6] = _zz_143_;
|
||
|
|
_zz_144_[5] = _zz_143_;
|
||
|
|
_zz_144_[4] = _zz_143_;
|
||
|
|
_zz_144_[3] = _zz_143_;
|
||
|
|
_zz_144_[2] = _zz_143_;
|
||
|
|
_zz_144_[1] = _zz_143_;
|
||
|
|
_zz_144_[0] = _zz_143_;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
|
||
|
|
assign _zz_24_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
|
||
|
|
assign _zz_74_ = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO);
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_75_ = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
|
||
|
|
if(1'b0)begin
|
||
|
|
_zz_75_ = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_misa_base = (2'b01);
|
||
|
|
assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000);
|
||
|
|
assign CsrPlugin_medeleg = (32'b00000000000000000000000000000000);
|
||
|
|
assign CsrPlugin_mideleg = (32'b00000000000000000000000000000000);
|
||
|
|
assign _zz_145_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
|
||
|
|
assign _zz_146_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
|
||
|
|
assign _zz_147_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
|
||
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode = 1'b0;
|
||
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = (2'b11);
|
||
|
|
assign execute_exception_agregat_valid = ({_zz_78_,{_zz_75_,_zz_73_}} != (3'b000));
|
||
|
|
assign _zz_148_ = {_zz_78_,{_zz_75_,_zz_73_}};
|
||
|
|
assign _zz_149_ = (_zz_148_ & (~ _zz_227_));
|
||
|
|
assign _zz_150_ = _zz_149_[1];
|
||
|
|
assign _zz_151_ = _zz_149_[2];
|
||
|
|
assign _zz_152_ = {_zz_151_,_zz_150_};
|
||
|
|
assign execute_exception_agregat_payload_code = _zz_177_;
|
||
|
|
assign execute_exception_agregat_payload_badAddr = _zz_178_;
|
||
|
|
assign CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_interrupt = 1'b0;
|
||
|
|
CsrPlugin_interruptCode = (4'bxxxx);
|
||
|
|
if(CsrPlugin_mstatus_MIE)begin
|
||
|
|
if(({_zz_147_,{_zz_146_,_zz_145_}} != (3'b000)))begin
|
||
|
|
CsrPlugin_interrupt = 1'b1;
|
||
|
|
end
|
||
|
|
if(_zz_145_)begin
|
||
|
|
CsrPlugin_interruptCode = (4'b0111);
|
||
|
|
end
|
||
|
|
if(_zz_146_)begin
|
||
|
|
CsrPlugin_interruptCode = (4'b0011);
|
||
|
|
end
|
||
|
|
if(_zz_147_)begin
|
||
|
|
CsrPlugin_interruptCode = (4'b1011);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if((! 1'b1))begin
|
||
|
|
CsrPlugin_interrupt = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_interruptTargetPrivilege = (2'b11);
|
||
|
|
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && 1'b1);
|
||
|
|
assign CsrPlugin_lastStageWasWfi = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_injector_nextPcCalc_valids_2);
|
||
|
|
if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin
|
||
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
||
|
|
end
|
||
|
|
if(CsrPlugin_hadException)begin
|
||
|
|
CsrPlugin_pipelineLiberator_done = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done);
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege;
|
||
|
|
if(CsrPlugin_hadException)begin
|
||
|
|
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
CsrPlugin_trapCause = CsrPlugin_interruptCode;
|
||
|
|
if(CsrPlugin_hadException)begin
|
||
|
|
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign contextSwitching = _zz_76_;
|
||
|
|
assign _zz_22_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
|
||
|
|
assign _zz_21_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
|
||
|
|
assign execute_CsrPlugin_blockedBySideEffects = 1'b0;
|
||
|
|
always @ (*) begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
||
|
|
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
|
||
|
|
case(execute_CsrPlugin_csrAddress)
|
||
|
|
12'b101111000000 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_153_;
|
||
|
|
end
|
||
|
|
12'b001100000000 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
|
||
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
|
||
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
|
||
|
|
end
|
||
|
|
12'b001101000001 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
|
||
|
|
end
|
||
|
|
12'b001100000101 : begin
|
||
|
|
if(execute_CSR_WRITE_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000100 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
|
||
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
|
||
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
|
||
|
|
end
|
||
|
|
12'b001101000011 : begin
|
||
|
|
if(execute_CSR_READ_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
|
||
|
|
end
|
||
|
|
12'b111111000000 : begin
|
||
|
|
if(execute_CSR_READ_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = _zz_154_;
|
||
|
|
end
|
||
|
|
12'b001101000000 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch;
|
||
|
|
end
|
||
|
|
12'b001100000100 : begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
|
||
|
|
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
|
||
|
|
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
|
||
|
|
end
|
||
|
|
12'b001101000010 : begin
|
||
|
|
if(execute_CSR_READ_OPCODE)begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
|
||
|
|
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b1;
|
||
|
|
end
|
||
|
|
if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
|
||
|
|
execute_CsrPlugin_illegalAccess = 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
execute_CsrPlugin_illegalInstruction = 1'b0;
|
||
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
|
||
|
|
if((execute_INSTRUCTION[29 : 28] != CsrPlugin_privilege))begin
|
||
|
|
execute_CsrPlugin_illegalInstruction = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
_zz_78_ = 1'b0;
|
||
|
|
_zz_79_ = (4'bxxxx);
|
||
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin
|
||
|
|
_zz_78_ = 1'b1;
|
||
|
|
_zz_79_ = (4'b1011);
|
||
|
|
end
|
||
|
|
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin
|
||
|
|
_zz_78_ = 1'b1;
|
||
|
|
_zz_79_ = (4'b0011);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
|
||
|
|
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
|
||
|
|
assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
||
|
|
assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
|
||
|
|
always @ (*) begin
|
||
|
|
case(_zz_188_)
|
||
|
|
1'b0 : begin
|
||
|
|
execute_CsrPlugin_writeData = execute_SRC1;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readData & (~ execute_SRC1)) : (execute_CsrPlugin_readData | execute_SRC1));
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
|
||
|
|
assign _zz_154_ = (_zz_153_ & externalInterruptArray_regNext);
|
||
|
|
assign externalInterrupt = (_zz_154_ != (32'b00000000000000000000000000000000));
|
||
|
|
assign _zz_20_ = decode_ALU_CTRL;
|
||
|
|
assign _zz_18_ = _zz_45_;
|
||
|
|
assign _zz_37_ = decode_to_execute_ALU_CTRL;
|
||
|
|
assign _zz_17_ = decode_SRC2_CTRL;
|
||
|
|
assign _zz_15_ = _zz_55_;
|
||
|
|
assign _zz_33_ = decode_to_execute_SRC2_CTRL;
|
||
|
|
assign _zz_14_ = decode_ENV_CTRL;
|
||
|
|
assign _zz_12_ = _zz_53_;
|
||
|
|
assign _zz_23_ = decode_to_execute_ENV_CTRL;
|
||
|
|
assign _zz_11_ = decode_BRANCH_CTRL;
|
||
|
|
assign _zz_60_ = _zz_44_;
|
||
|
|
assign _zz_26_ = decode_to_execute_BRANCH_CTRL;
|
||
|
|
assign _zz_9_ = decode_SHIFT_CTRL;
|
||
|
|
assign _zz_7_ = _zz_50_;
|
||
|
|
assign _zz_29_ = decode_to_execute_SHIFT_CTRL;
|
||
|
|
assign _zz_6_ = decode_ALU_BITWISE_CTRL;
|
||
|
|
assign _zz_4_ = _zz_49_;
|
||
|
|
assign _zz_39_ = decode_to_execute_ALU_BITWISE_CTRL;
|
||
|
|
assign _zz_3_ = decode_SRC1_CTRL;
|
||
|
|
assign _zz_1_ = _zz_52_;
|
||
|
|
assign _zz_35_ = decode_to_execute_SRC1_CTRL;
|
||
|
|
assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00));
|
||
|
|
assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0));
|
||
|
|
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck));
|
||
|
|
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
|
||
|
|
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
|
||
|
|
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
|
||
|
|
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0);
|
||
|
|
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
|
||
|
|
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
|
||
|
|
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
|
||
|
|
assign iBusWishbone_ADR = {_zz_236_,_zz_155_};
|
||
|
|
assign iBusWishbone_CTI = ((_zz_155_ == (3'b111)) ? (3'b111) : (3'b010));
|
||
|
|
assign iBusWishbone_BTE = (2'b00);
|
||
|
|
assign iBusWishbone_SEL = (4'b1111);
|
||
|
|
assign iBusWishbone_WE = 1'b0;
|
||
|
|
assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
|
||
|
|
always @ (*) begin
|
||
|
|
iBusWishbone_CYC = 1'b0;
|
||
|
|
iBusWishbone_STB = 1'b0;
|
||
|
|
if(_zz_184_)begin
|
||
|
|
iBusWishbone_CYC = 1'b1;
|
||
|
|
iBusWishbone_STB = 1'b1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
|
||
|
|
assign iBus_rsp_valid = _zz_156_;
|
||
|
|
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
|
||
|
|
assign iBus_rsp_payload_error = 1'b0;
|
||
|
|
assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
|
||
|
|
assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
|
||
|
|
assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
|
||
|
|
assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
|
||
|
|
assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
|
||
|
|
assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
|
||
|
|
assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
|
||
|
|
assign dBusWishbone_CTI = (3'b000);
|
||
|
|
assign dBusWishbone_BTE = (2'b00);
|
||
|
|
always @ (*) begin
|
||
|
|
case(dBus_cmd_halfPipe_payload_size)
|
||
|
|
2'b00 : begin
|
||
|
|
_zz_157_ = (4'b0001);
|
||
|
|
end
|
||
|
|
2'b01 : begin
|
||
|
|
_zz_157_ = (4'b0011);
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
_zz_157_ = (4'b1111);
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (*) begin
|
||
|
|
dBusWishbone_SEL = _zz_237_[3:0];
|
||
|
|
if((! dBus_cmd_halfPipe_payload_wr))begin
|
||
|
|
dBusWishbone_SEL = (4'b1111);
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
|
||
|
|
assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
|
||
|
|
assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
|
||
|
|
assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
|
||
|
|
assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
|
||
|
|
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
|
||
|
|
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
|
||
|
|
assign dBus_rsp_error = 1'b0;
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(reset) begin
|
||
|
|
CsrPlugin_privilege <= (2'b11);
|
||
|
|
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
|
||
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
||
|
|
_zz_86_ <= 1'b0;
|
||
|
|
_zz_92_ <= 1'b0;
|
||
|
|
_zz_94_ <= 1'b0;
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
||
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
|
||
|
|
execute_DBusSimplePlugin_cmdSent <= 1'b0;
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MPIE <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MPP <= (2'b11);
|
||
|
|
CsrPlugin_mip_MEIP <= 1'b0;
|
||
|
|
CsrPlugin_mip_MTIP <= 1'b0;
|
||
|
|
CsrPlugin_mip_MSIP <= 1'b0;
|
||
|
|
CsrPlugin_mie_MEIE <= 1'b0;
|
||
|
|
CsrPlugin_mie_MTIE <= 1'b0;
|
||
|
|
CsrPlugin_mie_MSIE <= 1'b0;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
||
|
|
CsrPlugin_hadException <= 1'b0;
|
||
|
|
_zz_153_ <= (32'b00000000000000000000000000000000);
|
||
|
|
execute_arbitration_isValid <= 1'b0;
|
||
|
|
_zz_155_ <= (3'b000);
|
||
|
|
_zz_156_ <= 1'b0;
|
||
|
|
dBus_cmd_halfPipe_regs_valid <= 1'b0;
|
||
|
|
dBus_cmd_halfPipe_regs_ready <= 1'b1;
|
||
|
|
end else begin
|
||
|
|
if(IBusCachedPlugin_fetchPc_propagatePc)begin
|
||
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
||
|
|
end
|
||
|
|
if(IBusCachedPlugin_jump_pcLoad_valid)begin
|
||
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b0;
|
||
|
|
end
|
||
|
|
if(_zz_183_)begin
|
||
|
|
IBusCachedPlugin_fetchPc_inc <= 1'b1;
|
||
|
|
end
|
||
|
|
if(IBusCachedPlugin_fetchPc_samplePcNext)begin
|
||
|
|
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
|
||
|
|
end
|
||
|
|
_zz_86_ <= 1'b1;
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
_zz_92_ <= 1'b0;
|
||
|
|
end
|
||
|
|
if(_zz_90_)begin
|
||
|
|
_zz_92_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid;
|
||
|
|
end
|
||
|
|
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
|
||
|
|
_zz_94_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid;
|
||
|
|
end
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
_zz_94_ <= 1'b0;
|
||
|
|
end
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
|
||
|
|
end
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
|
||
|
|
end
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
|
||
|
|
end
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
|
||
|
|
end
|
||
|
|
if(decode_arbitration_removeIt)begin
|
||
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b1;
|
||
|
|
end
|
||
|
|
if((IBusCachedPlugin_jump_pcLoad_valid || _zz_66_))begin
|
||
|
|
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
|
||
|
|
end
|
||
|
|
if((dBus_cmd_valid && dBus_cmd_ready))begin
|
||
|
|
execute_DBusSimplePlugin_cmdSent <= 1'b1;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
execute_DBusSimplePlugin_cmdSent <= 1'b0;
|
||
|
|
end
|
||
|
|
if(_zz_179_)begin
|
||
|
|
if(_zz_180_)begin
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b1;
|
||
|
|
if(execute_LightShifterPlugin_done)begin
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
if(execute_arbitration_removeIt)begin
|
||
|
|
execute_LightShifterPlugin_isActive <= 1'b0;
|
||
|
|
end
|
||
|
|
CsrPlugin_mip_MEIP <= externalInterrupt;
|
||
|
|
CsrPlugin_mip_MTIP <= timerInterrupt;
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
||
|
|
end else begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
|
||
|
|
end
|
||
|
|
CsrPlugin_hadException <= CsrPlugin_exception;
|
||
|
|
if(_zz_181_)begin
|
||
|
|
CsrPlugin_privilege <= CsrPlugin_targetPrivilege;
|
||
|
|
case(CsrPlugin_targetPrivilege)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_mstatus_MIE <= 1'b0;
|
||
|
|
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
|
||
|
|
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
if(_zz_182_)begin
|
||
|
|
case(_zz_187_)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
|
||
|
|
CsrPlugin_mstatus_MPP <= (2'b00);
|
||
|
|
CsrPlugin_mstatus_MPIE <= 1'b1;
|
||
|
|
CsrPlugin_privilege <= CsrPlugin_mstatus_MPP;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
|
||
|
|
execute_arbitration_isValid <= 1'b0;
|
||
|
|
end
|
||
|
|
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
|
||
|
|
execute_arbitration_isValid <= decode_arbitration_isValid;
|
||
|
|
end
|
||
|
|
case(execute_CsrPlugin_csrAddress)
|
||
|
|
12'b101111000000 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
_zz_153_ <= execute_CsrPlugin_writeData[31 : 0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001100000000 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
|
||
|
|
CsrPlugin_mstatus_MPIE <= _zz_230_[0];
|
||
|
|
CsrPlugin_mstatus_MIE <= _zz_231_[0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000001 : begin
|
||
|
|
end
|
||
|
|
12'b001100000101 : begin
|
||
|
|
end
|
||
|
|
12'b001101000100 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mip_MSIP <= _zz_232_[0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000011 : begin
|
||
|
|
end
|
||
|
|
12'b111111000000 : begin
|
||
|
|
end
|
||
|
|
12'b001101000000 : begin
|
||
|
|
end
|
||
|
|
12'b001100000100 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mie_MEIE <= _zz_233_[0];
|
||
|
|
CsrPlugin_mie_MTIE <= _zz_234_[0];
|
||
|
|
CsrPlugin_mie_MSIE <= _zz_235_[0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000010 : begin
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
if(_zz_184_)begin
|
||
|
|
if(iBusWishbone_ACK)begin
|
||
|
|
_zz_155_ <= (_zz_155_ + (3'b001));
|
||
|
|
end
|
||
|
|
end
|
||
|
|
_zz_156_ <= (iBusWishbone_CYC && iBusWishbone_ACK);
|
||
|
|
if(_zz_185_)begin
|
||
|
|
dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
|
||
|
|
dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
|
||
|
|
end else begin
|
||
|
|
dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
|
||
|
|
dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
always @ (posedge clk) begin
|
||
|
|
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
|
||
|
|
_zz_95_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
|
||
|
|
end
|
||
|
|
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin
|
||
|
|
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
|
||
|
|
end
|
||
|
|
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin
|
||
|
|
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuckByOthers))begin
|
||
|
|
execute_LightShifterPlugin_shiftReg <= _zz_56_;
|
||
|
|
end
|
||
|
|
if(_zz_179_)begin
|
||
|
|
if(_zz_180_)begin
|
||
|
|
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
|
||
|
|
end
|
||
|
|
end
|
||
|
|
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
||
|
|
if(execute_arbitration_isFiring)begin
|
||
|
|
CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
|
||
|
|
end
|
||
|
|
if(execute_exception_agregat_valid)begin
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= execute_exception_agregat_payload_code;
|
||
|
|
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= execute_exception_agregat_payload_badAddr;
|
||
|
|
end
|
||
|
|
if((CsrPlugin_exception || CsrPlugin_interruptJump))begin
|
||
|
|
case(CsrPlugin_privilege)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_mepc <= execute_PC;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
if(_zz_181_)begin
|
||
|
|
case(CsrPlugin_targetPrivilege)
|
||
|
|
2'b11 : begin
|
||
|
|
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
|
||
|
|
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
|
||
|
|
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
externalInterruptArray_regNext <= externalInterruptArray;
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_ALU_CTRL <= _zz_19_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC2_CTRL <= _zz_16_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_IS_CSR <= decode_IS_CSR;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_PC <= decode_PC;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_FLUSH_ALL <= decode_FLUSH_ALL;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_ENV_CTRL <= _zz_13_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_BRANCH_CTRL <= _zz_10_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_FORMAL_PC_NEXT <= _zz_61_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SHIFT_CTRL <= _zz_8_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_;
|
||
|
|
end
|
||
|
|
if((! execute_arbitration_isStuck))begin
|
||
|
|
decode_to_execute_SRC1_CTRL <= _zz_2_;
|
||
|
|
end
|
||
|
|
case(execute_CsrPlugin_csrAddress)
|
||
|
|
12'b101111000000 : begin
|
||
|
|
end
|
||
|
|
12'b001100000000 : begin
|
||
|
|
end
|
||
|
|
12'b001101000001 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001100000101 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
|
||
|
|
CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001101000100 : begin
|
||
|
|
end
|
||
|
|
12'b001101000011 : begin
|
||
|
|
end
|
||
|
|
12'b111111000000 : begin
|
||
|
|
end
|
||
|
|
12'b001101000000 : begin
|
||
|
|
if(execute_CsrPlugin_writeEnable)begin
|
||
|
|
CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0];
|
||
|
|
end
|
||
|
|
end
|
||
|
|
12'b001100000100 : begin
|
||
|
|
end
|
||
|
|
12'b001101000010 : begin
|
||
|
|
end
|
||
|
|
default : begin
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
|
||
|
|
if(_zz_185_)begin
|
||
|
|
dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
|
||
|
|
dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
|
||
|
|
dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
|
||
|
|
dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|