2019-01-01 10:41:37 +00:00
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.global main
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.global isr
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2019-01-21 23:30:52 +00:00
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.section .text.start
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2019-01-01 10:41:37 +00:00
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.global _start
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_start:
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j crt_init
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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2019-01-21 23:30:52 +00:00
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.section .text
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2019-01-01 10:41:37 +00:00
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.global trap_entry
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trap_entry:
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sw x1, - 1*4(sp)
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sw x5, - 2*4(sp)
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sw x6, - 3*4(sp)
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sw x7, - 4*4(sp)
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sw x10, - 5*4(sp)
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sw x11, - 6*4(sp)
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sw x12, - 7*4(sp)
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sw x13, - 8*4(sp)
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sw x14, - 9*4(sp)
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sw x15, -10*4(sp)
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sw x16, -11*4(sp)
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sw x17, -12*4(sp)
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sw x28, -13*4(sp)
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sw x29, -14*4(sp)
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sw x30, -15*4(sp)
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sw x31, -16*4(sp)
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addi sp,sp,-16*4
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call isr
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lw x1 , 15*4(sp)
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lw x5, 14*4(sp)
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lw x6, 13*4(sp)
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lw x7, 12*4(sp)
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lw x10, 11*4(sp)
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lw x11, 10*4(sp)
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lw x12, 9*4(sp)
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lw x13, 8*4(sp)
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lw x14, 7*4(sp)
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lw x15, 6*4(sp)
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lw x16, 5*4(sp)
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lw x17, 4*4(sp)
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lw x28, 3*4(sp)
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lw x29, 2*4(sp)
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lw x30, 1*4(sp)
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lw x31, 0*4(sp)
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addi sp,sp,16*4
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mret
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.text
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crt_init:
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la sp, _fstack + 4
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la a0, trap_entry
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csrw mtvec, a0
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bss_init:
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la a0, _fbss
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la a1, _ebss
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bss_loop:
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beq a0,a1,bss_done
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sw zero,0(a0)
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add a0,a0,4
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j bss_loop
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bss_done:
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2019-01-25 01:27:43 +00:00
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/* Load DATA */
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la t0, _erodata
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la t1, _fdata
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la t2, _edata
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3:
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lw t3, 0(t0)
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sw t3, 0(t1)
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/* _edata is aligned to 16 bytes. Use word-xfers. */
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addi t0, t0, 4
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addi t1, t1, 4
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bltu t1, t2, 3b
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2019-01-01 10:41:37 +00:00
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li a0, 0x880 //880 enable timer + external interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
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csrw mie,a0
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call main
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infinit_loop:
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j infinit_loop
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