61 lines
1.9 KiB
Python
61 lines
1.9 KiB
Python
#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]
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# Import lxbuildenv to integrate the deps/ directory
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import lxbuildenv
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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#from migen import *
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from litex.build.xilinx import VivadoProgrammer, XilinxPlatform
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from litex.build.generic_platform import Pins, IOStandard
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from litex.soc.integration import SoCSDRAM
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import csr_map_update
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_io = [
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("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
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]
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class Platform(XilinxPlatform):
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def __init__(self, toolchain="vivado", programmer="vivado", part="35"):
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part = "xc7a" + part + "t-fgg484-2"
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def create_programmer(self):
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if self.programmer == "vivado":
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return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
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else:
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raise ValueError("{} programmer is not supported"
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.format(self.programmer))
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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class BaseSoC(SoCSDRAM):
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csr_peripherals = [
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"ddrphy",
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# "dna",
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"xadc",
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"cpu_or_bridge",
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]
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csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
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def __init__(self, platform, **kwargs):
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# clk_freq = int(100e6)
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self.integrated_main_ram_size = 8192
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self.add_memory()
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def main():
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platform = Platform()
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soc = BaseSoC(platform)
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builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
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vns = builder.build()
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soc.do_exit(vns)
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if __name__ == "__main__":
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main()
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