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foboot-bitstream: use crystal for 12 MHz clock

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This fixes heterodyning that was occurring in the USB block, as it
transitioned from the 48 MHz down to the 12 MHz domain.

Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross
2019-02-27 14:20:04 +08:00
parent dd7839cc68
commit cad2ae01d7
1 changed files with 23 additions and 11 deletions
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34
foboot-bitstream.py
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@@ -63,17 +63,17 @@ _connectors = []
class _CRG(Module): class _CRG(Module):
def __init__(self, platform): def __init__(self, platform):
clk12 = Signal() clk12 = Signal()
# "0b00" Sets 48MHz HFOSC output # # "0b00" Sets 48MHz HFOSC output
# "0b01" Sets 24MHz HFOSC output. # # "0b01" Sets 24MHz HFOSC output.
# "0b10" Sets 12MHz HFOSC output. # # "0b10" Sets 12MHz HFOSC output.
# "0b11" Sets 6MHz HFOSC output # # "0b11" Sets 6MHz HFOSC output
self.specials += Instance( # self.specials += Instance(
"SB_HFOSC", # "SB_HFOSC",
i_CLKHFEN=1, # i_CLKHFEN=1,
i_CLKHFPU=1, # i_CLKHFPU=1,
o_CLKHF=clk12, # o_CLKHF=clk12,
p_CLKHF_DIV="0b10", # 12MHz # p_CLKHF_DIV="0b10", # 12MHz
) # )
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_usb_12 = ClockDomain() self.clock_domains.cd_usb_12 = ClockDomain()
@@ -93,6 +93,18 @@ class _CRG(Module):
self.cd_sys.rst.eq(reset_delay != 0), self.cd_sys.rst.eq(reset_delay != 0),
self.cd_usb_12.rst.eq(reset_delay != 0) self.cd_usb_12.rst.eq(reset_delay != 0)
] ]
# Divide clk48 down to clk12, to ensure they're synchronized.
clk12_counter = Signal(2)
self.sync.usb_48 += [
clk12_counter.eq(clk12_counter + 1),
]
self.specials += Instance(
"SB_GB",
i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_counter[1],
o_GLOBAL_BUFFER_OUTPUT=clk12,
)
self.sync.por += \ self.sync.por += \
If(reset_delay != 0, If(reset_delay != 0,
reset_delay.eq(reset_delay - 1) reset_delay.eq(reset_delay - 1)