initial commit

Signed-off-by: Sean Cross <sean@xobs.io>

foboot-bitstream.py

@@ -0,0 +1,60 @@
+#!/usr/bin/env python3
+# This variable defines all the external programs that this module
+# relies on.  lxbuildenv reads this variable in order to ensure
+# the build will finish without exiting due to missing third-party
+# programs.
+LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]
+
+# Import lxbuildenv to integrate the deps/ directory
+import lxbuildenv
+
+# Disable pylint's E1101, which breaks completely on migen
+#pylint:disable=E1101
+
+#from migen import *
+from litex.build.xilinx import VivadoProgrammer, XilinxPlatform
+from litex.build.generic_platform import Pins, IOStandard
+from litex.soc.integration import SoCSDRAM
+from litex.soc.integration.builder import Builder
+from litex.soc.integration.soc_core import csr_map_update
+
+_io = [
+    ("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
+]
+
+class Platform(XilinxPlatform):
+    def __init__(self, toolchain="vivado", programmer="vivado", part="35"):
+        part = "xc7a" + part + "t-fgg484-2"
+    def create_programmer(self):
+        if self.programmer == "vivado":
+            return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
+        else:
+            raise ValueError("{} programmer is not supported"
+                             .format(self.programmer))
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+
+class BaseSoC(SoCSDRAM):
+    csr_peripherals = [
+        "ddrphy",
+#        "dna",
+        "xadc",
+        "cpu_or_bridge",
+    ]
+    csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
+
+    def __init__(self, platform, **kwargs):
+        # clk_freq = int(100e6)
+        self.integrated_main_ram_size = 8192
+        self.add_memory()
+
+def main():
+    platform = Platform()
+    soc = BaseSoC(platform)
+    builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
+    vns = builder.build()
+    soc.do_exit(vns)
+
+if __name__ == "__main__":
+    main()