The State of Open Silicon

About Me

Outline

  1. What does it mean to be "open"?
  2. What can we do today?
  3. What can't we do today?
  4. Where can we go from here?

What does it mean to be "open"?

  1. Manuals available
  2. Source available
  3. Tooling available
  4. GDSII available

Parts of chip design

  • Nondisclosure Agreements
  • Process Design Kit (PDK)
  • IP (libraries)
  • Tooling
  • Fabrication method

Nondisclosure Agreements

NDAs are required for using many packages

Process Design Kit

  • https://skywater-pdk.readthedocs.io/en/main/_images/metal_stack.svg
  • Process design kits (PDKs) are closed and under NDA
  • Mostly just a blank canvas

IP / Libraries

  • Memories
  • IO blocks
  • Standard cells

Digital design (In The Beginning)

  • [Picture of Z80 or 6502]
  • Magic
  • [Picture of Siliwiz]

Digital logic overview (Today)

  • Standard cells
  • Basic boolean logic

How can we use standard cells?

  • Manual synthesis
  • Automated synthesis
Almost all code is automatically synthesized from source code! [Example of live generation of cells]

Tooling

  • Synthesis
  • Power generation
  • Clock tree
  • Place and route
  • Verification
  • Industry tools cost $1mm plus per seat

Method to tape out

  • Shuttle runs
  • Full wafer
  • Turnaround time is in months

Where are we now (in open source)?

Things are looking pretty good!

Nondisclosure Agreements

NDAs are required for using many packages

Open PDKs

  • Real PDKs
    • SKY130
    • SKY90FD
    • GF180MCU
  • "Fake" PDKs
    • FreePDK45
    • ASAP5

Available IP

Projects that have been taped out

  • ADC
  • LDO
  • Bandgap
  • DAC
  • ...more...

Standard cells

  • SKY130
  • GF180MCU
  • OSU
  • LibreSilicon

What about tooling?

Hardware Synthesis

  • Yosys (Verilog)
  • Plugins:
    • GHDL (VHDL)
    • SystemVerilog

High level languages

  • LiteX Python
  • SpinalHDL Scala
  • Clash

Floorplanning, Placement, Routing, PDN, etc...

  • OpenROAD
  • Integrates other tools natively
  • Competitive with closed tools

Simulation

  • GHDL
  • Icarus Verilog
  • Verilator
  • GTKWave

Direct Cell Design and Inspection

  • Magic
  • KLayout

What about taping out chips?

  • Google OpenMPW shuttles
  • MPW shuttle runs

# What can't we do today?

PDKs are large nodes

  • Gamecube CPU "Gekko": 43 mm2 (2001)

Examples of 180 nm

  • Playstation 2 "Emotion Engine"

Memories are still hard

  • Density is constantly improving
  • Expect kilobytes of RAM on a chip
    • Compare to megabytes of cache
  • A ~4x increase is possible
  • Experimental ROM support

Nonvolatile storage is still hard

  • No EEPROM or flash
  • ReRAM is experimental on SKY130

Analogue IP is still difficult

  • Some tapeouts exist, but documentation is scarce
  • Need more integration examples

Where are we going from here?

And how you help

Boon for education

  • NDA-free design
  • Many more hobbyists
  • Zero-to-ASIC course

Smaller process nodes

  • OpenROAD has been tested on smaller nodes
  • No NDA-free PDKs yet

More analogue design

  • Siliwiz

More involvement

  • Tiny Tapeout
  • Siliwiz
  • OpenMPW

Thank you