- [What does it mean for silicon to be "Open"?](#what-does-it-mean-for-silicon-to-be-open)
  - [Parts of chip design](#parts-of-chip-design)
  - [Open tooling](#open-tooling)
  - [Manual design (In The Beginning)](#manual-design-in-the-beginning)
  - [Digital logic overview](#digital-logic-overview)
  - [How can we use standard cells?](#how-can-we-use-standard-cells)
  - [Digital design](#digital-design)
  - [Process Design Kits](#process-design-kits)
  - [What about blackboxes?](#what-about-blackboxes)
  - [Place and route](#place-and-route)
  - [Other tools](#other-tools)
- [What is the current state of the art?](#what-is-the-current-state-of-the-art)
  - [Things are looking pretty good!](#things-are-looking-pretty-good)
  - [End-to-end tool flow possible!](#end-to-end-tool-flow-possible)
  - [Current open PDKs are "ginormous"](#current-open-pdks-are-ginormous)
  - [Hardware synthesis](#hardware-synthesis)
  - [High level languages](#high-level-languages)
  - [Floorplanning, Placement, Routing](#floorplanning-placement-routing)
  - [Power and Clock generation](#power-and-clock-generation)
  - [Verification](#verification)
  - [Wide selection of existing chips](#wide-selection-of-existing-chips)
  - [Large selection of existing IP](#large-selection-of-existing-ip)
- [Where are we going from here?](#where-are-we-going-from-here)
  - [More open PDKs](#more-open-pdks)
  - [Improved analogue IP](#improved-analogue-ip)
  - [Better IP discoverability](#better-ip-discoverability)
  - [Better integration](#better-integration)
  - [Memories are still hard](#memories-are-still-hard)
  - [Flash is still hard](#flash-is-still-hard)
  - [EEPROM is still hard](#eeprom-is-still-hard)
  - [Exotic, non-digital IP is hard!](#exotic-non-digital-ip-is-hard)
- [Getting involved!](#getting-involved)
  - [Siliwiz for raw tapeout](#siliwiz-for-raw-tapeout)
  - [TinyTapeout](#tinytapeout)
  - [](#)

# What does it mean for silicon to be "Open"?

## Parts of chip design

* Tooling
* PDKs
* IP

## Open tooling

* Industry tools cost $1mm plus per seat
* Process design kits (PDKs) are closed and under NDA
* Tooling includes synthesis, placement, and routing
* Tooling also includes verification, clock generation, and power generation

## Manual design (In The Beginning)

* Rubylith
* Magic
* [Picture of Siliwiz]

## Digital logic overview

* Boolean values

## How can we use standard cells?

* Manual synthesis
* Automated synthesis

Almost all code is automatically synthesized from source code!

## Digital design

Source code can be in a Hardware Description Language. For example:

* Verilog
* SystemVerilog
* VHDL

[Example of live generation of cells]

## Process Design Kits

* Very low-level logic
* AND
* NOR
* NOT
* Diode
* Tie

Digital logic is, for the most part, a collection of these standard cells!

[Image of standard cells]

## What about blackboxes?

* Frequently called "IP"
* Blackboxes allow for more functionality, or higher performance
  * Memories, RF, ADC, etc.
* Usually have Verilog models that are non-synthesizable.
* Place-and-route tool wires up the ports
* Blackboxes are how we get analogue!

## Place and route

The tool will automatically place cells, and will add wires between them!

## Other tools

* Clock generation
* Power generation
* Reset inserters
* Parasitic extraction
* Layout-vs-Schematic

# What is the current state of the art?

## Things are looking pretty good!

## End-to-end tool flow possible!

* Open tooling, open PDK
* Chips have been produced using this flow
* Production is still an issue

## Current open PDKs are "ginormous"

* 180nm and 130nm are peak-1999 technology
   * Still can do interesting things at 180/130nm!
* "Fake" PDKs exist

## Hardware synthesis

* Yosys
* GHDL

Ingests Verilog or VHDL and generates basic netlists

## High level languages

* LiteX [Python]
* SpinalHDL [Scala]
* [Rust]

These all geneate Verilog, and are fully open!

## Floorplanning, Placement, Routing

* OpenROAD is the current gold-standard
* Compatitive with closed tools

## Power and Clock generation

* Setup and hold timing validation
* Basic power nets supported
* Straps are generated as expected

## Verification

* Parasitic extraction works
* Layout-versus-Schematics
* Simulation of extracted netlist
* Design Rule Checking

## Wide selection of existing chips

* Taped out
* Still being characterized

## Large selection of existing IP

* [Picture of MPW list]

# Where are we going from here?

## More open PDKs

* GF180MCU is relatively new
* ??? PDKs

## Improved analogue IP

* Each run adds even more designs

## Better IP discoverability

* Indexes of IP cores

## Better integration

* Wishbone is standard in open source
* AXI4 is common in industry

## Memories are still hard

## Flash is still hard

## EEPROM is still hard

## Exotic, non-digital IP is hard!

# Getting involved!

## Siliwiz for raw tapeout

## TinyTapeout

##