disassembler: implement disassembler
The disassembler will be useful in tracking down build errors. Signed-off-by: Sean Cross <sean@xobs.io>
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dccb088961
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@ -8,7 +8,8 @@ edition = "2018"
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[features]
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macro-debug = []
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default = []
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std = []
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default = ["std"]
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[dependencies]
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217
src/lib.rs
217
src/lib.rs
@ -1,7 +1,7 @@
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#![cfg_attr(feature="macro-debug",feature(trace_macros))]
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#![cfg_attr(feature="macro-debug",feature(log_syntax))]
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#[cfg(feature="macro-debug")]
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trace_macros!{true}
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#![cfg_attr(feature = "macro-debug", feature(trace_macros))]
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#![cfg_attr(feature = "macro-debug", feature(log_syntax))]
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#[cfg(feature = "macro-debug")]
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trace_macros! {true}
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/*
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opcodes
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@ -27,6 +27,19 @@ trace_macros!{true}
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BRZ 0x2, r1 // if r1 is 0, mpc = mpc + 0x2
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loop:
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BRZ loop, r2 // if r2 is 0, go to label "loop"
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Basic opcode format:
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0b_rrrrrrrrr_ddddd_y_bbbbb_x_aaaaa_oooooo
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Where:
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o: Opcode
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a: Source register a
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x: `1` if A is a constant rather than register
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b: Source register b
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y: `1` if B is a constant rather than a register
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d: Destination register index
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r: Reserved (set to 0)
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*/
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/// A compile-time map from identifiers to arbitrary (heterogeneous) expressions
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@ -44,7 +57,6 @@ macro_rules! ident_map {
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};
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}
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/// Returns the number of comma-separated expressions passed to it
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#[macro_export]
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#[doc(hidden)]
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@ -54,9 +66,6 @@ macro_rules! codelen {
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( $first:expr, $($rest:expr),+ ) => { 1 + codelen!($($rest),+) };
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}
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/// Replace elements of "arrays" of expressions with sorted replacements by
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/// seeking along a "positional array" containing n expressions, then replacing
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/// elements in the source array.
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@ -120,7 +129,6 @@ macro_rules! lockstep_replace {
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/// Relocation formats:
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/// { $label as ABS16 @ [$lockstepmcpos] }
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// $pos is
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#[macro_export]
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#[doc(hidden)]
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macro_rules! reloc {
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@ -149,13 +157,11 @@ macro_rules! reloc {
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};
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}
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// $attr is a label
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// $mcode is a list that contains the machine code opcodes
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// $ident is the identifier list
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// $reloc is the relocation list
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#[macro_export]
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#[doc(hidden)]
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macro_rules! asm_ {
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@ -180,33 +186,33 @@ macro_rules! asm_ {
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( { $($attr:tt)* } [ $($mcode:expr),* ], [ $($lbl:ident => $lblval:expr),* ], [ $($reloc:tt),* ],
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add % $wd:tt, % $ra:tt , % $rb:tt
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$($rest:tt)* ) => {
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 16 | 0 << 11 | $ra << 6 | 0 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 18 | 0 << 11 | $ra << 6 | 0 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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};
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( { $($attr:tt)* } [ $($mcode:expr),* ], [ $($lbl:ident => $lblval:expr),* ], [ $($reloc:tt),* ],
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add % $wd:tt, % $ra:tt , # $rb:tt
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$($rest:tt)* ) => {
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 16 | 0 << 11 | $ra << 6 | 1 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 18 | 0 << 11 | $ra << 6 | 1 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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};
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( { $($attr:tt)* } [ $($mcode:expr),* ], [ $($lbl:ident => $lblval:expr),* ], [ $($reloc:tt),* ],
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add % $wd:tt, # $ra:tt , % $rb:tt
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$($rest:tt)* ) => {
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 16 | 1 << 11 | $ra << 6 | 0 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 18 | 1 << 11 | $ra << 6 | 0 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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};
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( { $($attr:tt)* } [ $($mcode:expr),* ], [ $($lbl:ident => $lblval:expr),* ], [ $($reloc:tt),* ],
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add % $wd:tt, # $ra:tt , # $rb:tt
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$($rest:tt)* ) => {
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 16 | 1 << 11 | $ra << 6 | 1 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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asm_!({ $($attr)* } [ $($mcode,)* $wd << 18 | 1 << 11 | $ra << 6 | 1 << 17 | $rb << 12 | 0x5 ], [ $($lbl => $lblval),* ], [ $($reloc),* ], $($rest)*)
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};
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// BRZ
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// ( { $($attr:tt)* } [ $($mcode:expr),* ], [ $($lbl:ident => $lblval:expr),* ], [ $($reloc:tt),* ],
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// brz $label:ident , % $ra:tt
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// $($rest:tt)* ) => {
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// asm_!({ $($attr)* } [ $($mcode,)* 0x0 ],
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// [ $($lbl => $lblval),* ], [ $($reloc,)* { $label as PCREL @ [ $($mcode,)* ] } ], $($rest)*)
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// };
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( { $($attr:tt)* } [ $($mcode:expr),* ], [ $($lbl:ident => $lblval:expr),* ], [ $($reloc:tt),* ],
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brz $label:ident , % $ra:tt
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$($rest:tt)* ) => {
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asm_!({ $($attr)* } [ $($mcode,)* 0x0 ],
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[ $($lbl => $lblval),* ], [ $($reloc,)* { $label as PCREL @ [ $($mcode,)* ] } ], $($rest)*)
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};
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( { $($attr:tt)* } [ $($mcode:expr),* ], [ $($lbl:ident => $lblval:expr),* ], [ $($reloc:tt),* ],
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brz $label:ident , # $ra:tt
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brz $label:ident , #$ra:tt
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$($rest:tt)* ) => {
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asm_!({ $($attr)* } [ $($mcode,)* 0 << 23 | 1 << 11 | $ra << 6 | 0x9 ],
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[ $($lbl => $lblval),* ], [ $($reloc,)* { $label as PCREL @ [$($mcode,)* 0 << 23 | 1 << 11 | $ra << 6 | 0x9] } ], $($rest)*)
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@ -249,41 +255,154 @@ macro_rules! assemble_engine25519 {
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})
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};
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}
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/*
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/// Does anything work
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#[test]
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fn basic_syntax() {
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let mcode = assemble_engine25519!(
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start:
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add %0, %1, %2
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add %2, %3, #4
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add %5, #6, %7
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add %8, #9, #10
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brz start, %11
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);
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assert_eq!(mcode, [
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0 << 16 | 0 << 11 | 1 << 6 | 0 << 17 | 2 << 12 | 0x5,
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2 << 16 | 0 << 11 | 3 << 6 | 1 << 17 | 4 << 12 | 0x5,
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5 << 16 | 1 << 11 | 6 << 6 | 0 << 17 | 7 << 12 | 0x5,
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8 << 16 | 1 << 11 | 9 << 6 | 1 << 17 | 10 << 12 | 0x5,
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0x3FC << 23 | 0 << 11 | 11 << 6 | 0x9,
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]);
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// /// Does anything work
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// #[test]
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// fn basic_syntax() {
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// let mcode = assemble_engine25519!(
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// start:
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// add %0, %1, %2
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// add %2, %3, #4
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// add %5, #6, %7
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// add %8, #9, #10
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// brz start, #11
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// );
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// assert_eq!(
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// mcode,
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// [
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// 0 << 16 | 0 << 11 | 1 << 6 | 0 << 17 | 2 << 12 | 0x5,
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// 2 << 16 | 0 << 11 | 3 << 6 | 1 << 17 | 4 << 12 | 0x5,
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// 5 << 16 | 1 << 11 | 6 << 6 | 0 << 17 | 7 << 12 | 0x5,
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// 8 << 16 | 1 << 11 | 9 << 6 | 1 << 17 | 10 << 12 | 0x5,
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// 0x3FC << 23 | 0 << 11 | 11 << 6 | 0x9,
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// ]
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// );
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// }
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pub enum Operand {
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Register(i32),
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Constant(i32),
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}
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impl Operand {
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pub fn from_i32_r(op: i32) -> Operand {
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if (op >> 5) & 1 == 0 {
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Operand::Register(op & (32 - 1))
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} else {
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Operand::Constant(op & (32 - 1))
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}
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}
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pub fn from_i32_w(op: i32) -> Operand {
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Operand::Register(op & (32 - 1))
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}
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}
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#[cfg(feature = "std")]
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impl std::fmt::Display for Operand {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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use Operand::*;
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match self {
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Register(r) => write!(f, "%{}", r),
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Constant(c) => write!(f, "#{}", c),
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}
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}
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}
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pub enum Opcode {
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PSA(Operand, Operand),
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PSB(Operand, Operand),
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MSK(Operand, Operand),
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XOR,
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NOT,
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ADD(Operand, Operand, Operand),
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SUB,
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MUL,
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TRD,
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BRZ(Operand, i32),
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UDF,
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}
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impl Opcode {
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pub fn from_i32(op: i32) -> Opcode {
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match op & (32 - 1) {
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0 => Opcode::PSA(Operand::from_i32_r(op >> 6), Operand::from_i32_w(op >> 18)),
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1 => Opcode::PSB(Operand::from_i32_r(op >> 6), Operand::from_i32_w(op >> 18)),
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2 => Opcode::MSK(Operand::from_i32_r(op >> 6), Operand::from_i32_r(op >> 12)),
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3 => Opcode::XOR,
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4 => Opcode::NOT,
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5 => Opcode::ADD(Operand::from_i32_r(op >> 6), Operand::from_i32_r(op >> 12), Operand::from_i32_w(op >> 18)),
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6 => Opcode::SUB,
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7 => Opcode::MUL,
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8 => Opcode::TRD,
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9 => Opcode::BRZ(Operand::from_i32_r(op >> 6), op >> 23),
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_ => Opcode::UDF,
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}
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}
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}
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#[cfg(feature = "std")]
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impl std::fmt::Display for Opcode {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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use Opcode::*;
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match self {
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PSA(ra, rd) => write!(f, "PSA {}, {}", ra, rd),
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PSB(ra, rd) => write!(f, "PSB {}, {}", ra, rd),
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MSK(ra, rb) => write!(f, "MSK {}, {}", ra, rb),
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XOR => write!(f, "XOR"),
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NOT => write!(f, "NOT"),
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ADD(ra, rb, rd) => write!(f, "ADD {}, {}, {}", rd, ra, rb),
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SUB => write!(f, "SUB"),
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MUL => write!(f, "MUL"),
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TRD => write!(f, "TRD"),
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BRZ(ra, rb) => write!(f, "BRZ {}, {}", rb, ra),
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_ => write!(f, "invalid"),
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}
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}
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}
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#[cfg(test)]
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fn print_opcode(op: i32) {
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println!(
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"{:09b} {:05b} {:01b} {:05b} {:01b} {:05b} {:05b} | {}",
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(op >> 23) & (512 - 1),
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(op >> 18) & (32 - 1),
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(op >> 17) & 1,
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(op >> 12) & (32 - 1),
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(op >> 11) & 1,
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(op >> 6) & (32 - 1),
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op & (32 - 1),
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Opcode::from_i32(op),
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);
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}
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*/
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/// Simple jump
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#[test]
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fn simple_jmp() {
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let mcode = assemble_engine25519!(
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start:
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add %0, %1, %2
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brz start, %11
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start:
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add %8, #9, #11
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mid:
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brz start, #11
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add %8, #9, #12
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add %8, #9, #10
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);
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print!("{}", mcode);
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assert_eq!(mcode, [
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0 << 16 | 0 << 11 | 1 << 6 | 0 << 17 | 2 << 12 | 0x5,
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println!("Assembled output:");
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for op in &mcode {
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print_opcode(*op);
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}
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let target = [
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8 << 18 | 1 << 11 | 9 << 6 | 1 << 17 | 11 << 12 | 0x5,
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0x3FE << 23 | 0 << 11 | 11 << 6 | 0x9,
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]);
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8 << 18 | 1 << 11 | 9 << 6 | 1 << 17 | 12 << 12 | 0x5,
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8 << 18 | 1 << 11 | 9 << 6 | 1 << 17 | 10 << 12 | 0x5,
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];
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println!("Target output:");
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for op in &target {
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print_opcode(*op);
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}
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assert_eq!(mcode, target);
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}
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/*
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