// Derived from: Auto-generated config file peripheral_clk_config.h
// Boilerplate removed.

#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H

// ADC
#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_ADC0_FREQUENCY 120000000

// DAC
#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_DAC_FREQUENCY 120000000

// EVSYS
#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0

#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0

// CPU: 120 MHz
#define CONF_CPU_FREQUENCY 120000000

// RTC
#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
#define CONF_GCLK_RTC_FREQUENCY 1024


// SERCOM
// Use 48 MHz clock for CORE, and 32kHz clock for SLOW.
// 120 MHz is too fast for CORE.
// Slow is only needed for SMBus, it appears.

#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768

#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768

#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768

#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768

#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768

#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768

#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768

#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 48000000
#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768

// TC
#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#define CONF_GCLK_TC0_FREQUENCY 12000000

// USB
#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
#define CONF_GCLK_USB_FREQUENCY 48000000

#endif // PERIPHERAL_CLK_CONFIG_H