Refine iMX RT memory layout and add three boards
Introduces a way to place CircuitPython code and data into tightly coupled memory (TCM) which is accessible by the CPU in a single cycle. It also frees up room in the corresponding cache for intermittent data. Loading from external flash is slow! The data cache is also now enabled. Adds support for the iMX RT 1021 chip. Adds three new boards: * iMX RT 1020 EVK * iMX RT 1060 EVK * Teensy 4.0 Related to #2492, #2472 and #2477. Fixes #2475.crypto-aes
Scott Shawcroft
3 years ago
parent
85c731734a
commit
7d8dac9211
@ -1 +1 @@
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Subproject commit dda4c9a94b509238faa7b5ab5b9464c1d2e63ff0
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Subproject commit 1f95f439e11f519e69d75a4a8b7b9f28eaf5060e
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@ -0,0 +1,122 @@
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi_nor_boot.h"
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#include "fsl_flexspi_nor_config.h"
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__attribute__((section(".boot_hdr.ivt")))
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/*************************************
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* IVT Data
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*************************************/
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const ivt image_vector_table = {
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IVT_HEADER, /* IVT Header */
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IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
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IVT_RSVD, /* Reserved = 0 */
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(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
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(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
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(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
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(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
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IVT_RSVD /* Reserved = 0 */
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};
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__attribute__((section(".boot_hdr.boot_data")))
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/*************************************
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* Boot Data
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*************************************/
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const BOOT_DATA_T boot_data = {
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FLASH_BASE, /* boot start location */
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FLASH_SIZE, /* size */
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PLUGIN_FLAG, /* Plugin flag*/
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0xFFFFFFFF /* empty - extra data word */
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};
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__attribute__((section(".boot_hdr.conf")))
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// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 1u,
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.csSetupTime = 2u,
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// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
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.sflashA1Size = FLASH_SIZE,
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.lookupTable =
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{
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// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
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// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
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// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// Read LUTs
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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0,
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0,
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0x24040405,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000406,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x08180420,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x081804D8,
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0,
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0,
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0,
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0x08180402,
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0x00002004,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000460,
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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};
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@ -1,21 +1,8 @@
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LD_FILE = boards/mimxrt1011-bootloader-external-flash.ld
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USB_VID = 0x239A
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USB_PID = 0x8074
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USB_PRODUCT = "Feather MIMXRT1011"
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USB_MANUFACTURER = "arturo182"
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USB_DEVICES = "CDC,MSC,HID"
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CHIP_VARIANT = MIMXRT1011DAE5A
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CHIP_FAMILY = MIMXRT1011
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INTERNAL_FLASH_FILESYSTEM = 1
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CIRCUITPY_DISPLAYIO = 0
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CIRCUITPY_AUDIOIO = 0
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CIRCUITPY_AUDIOBUSIO = 0
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CIRCUITPY_FREQUENCYIO = 0
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CIRCUITPY_I2CSLAVE = 0
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CIRCUITPY_NVM = 0
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CIRCUITPY_ROTARYIO = 0
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LONGINT_IMPL = MPZ
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FLASH = W25Q64JV
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@ -0,0 +1,122 @@
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi_nor_boot.h"
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#include "fsl_flexspi_nor_config.h"
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__attribute__((section(".boot_hdr.ivt")))
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/*************************************
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* IVT Data
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*************************************/
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const ivt image_vector_table = {
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IVT_HEADER, /* IVT Header */
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IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
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IVT_RSVD, /* Reserved = 0 */
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(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
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(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
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(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
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(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
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IVT_RSVD /* Reserved = 0 */
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};
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__attribute__((section(".boot_hdr.boot_data")))
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/*************************************
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* Boot Data
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*************************************/
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const BOOT_DATA_T boot_data = {
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FLASH_BASE, /* boot start location */
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FLASH_SIZE, /* size */
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PLUGIN_FLAG, /* Plugin flag*/
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0xFFFFFFFF /* empty - extra data word */
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};
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__attribute__((section(".boot_hdr.conf")))
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// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 1u,
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.csSetupTime = 2u,
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// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
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.sflashA1Size = FLASH_SIZE,
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.lookupTable =
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{
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// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
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// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
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// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// Read LUTs
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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0,
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0,
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0x24040405,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000406,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x08180420,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x081804D8,
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0,
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0,
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0,
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0x08180402,
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0x00002004,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000460,
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
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.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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};
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@ -1,21 +1,8 @@
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LD_FILE = boards/mimxrt1062-bootloader-external-flash.ld
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USB_VID = 0x239A
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USB_PID = 0x8076
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USB_PRODUCT = "Feather MIMXRT1062"
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USB_MANUFACTURER = "arturo182"
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USB_DEVICES = "CDC,MSC,HID"
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CHIP_VARIANT = MIMXRT1062DVJ6A
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CHIP_FAMILY = MIMXRT1062
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INTERNAL_FLASH_FILESYSTEM = 1
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CIRCUITPY_DISPLAYIO = 0
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CIRCUITPY_AUDIOIO = 0
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CIRCUITPY_AUDIOBUSIO = 0
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CIRCUITPY_FREQUENCYIO = 0
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CIRCUITPY_I2CSLAVE = 0
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CIRCUITPY_NVM = 0
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CIRCUITPY_ROTARYIO = 0
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LONGINT_IMPL = MPZ
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FLASH = W25Q64JV
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@ -0,0 +1,141 @@
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexspi_nor_boot.h"
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#include "fsl_flexspi_nor_config.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xip_device"
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#endif
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.ivt")))
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#elif defined(__ICCARM__)
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#pragma location=".boot_hdr.ivt"
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#endif
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/*************************************
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* IVT Data
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*************************************/
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const ivt image_vector_table = {
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IVT_HEADER, /* IVT Header */
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IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
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IVT_RSVD, /* Reserved = 0 */
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(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
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(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
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(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
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(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
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IVT_RSVD /* Reserved = 0 */
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};
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.boot_data")))
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#elif defined(__ICCARM__)
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#pragma location=".boot_hdr.boot_data"
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#endif
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/*************************************
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* Boot Data
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*************************************/
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const BOOT_DATA_T boot_data = {
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FLASH_BASE, /* boot start location */
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FLASH_SIZE, /* size */
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PLUGIN_FLAG, /* Plugin flag*/
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0xFFFFFFFF /* empty - extra data word */
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};
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#endif
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
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const flexspi_nor_config_t qspiflash_config = {
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.memConfig =
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{
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.tag = FLEXSPI_CFG_BLK_TAG,
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.version = FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
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.csHoldTime = 1u,
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.csSetupTime = 2u,
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// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
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.deviceType = kFlexSpiDeviceType_SerialNOR,
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.sflashPadType = kSerialFlash_4Pads,
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.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
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.sflashA1Size = FLASH_SIZE,
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.lookupTable =
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{
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// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
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// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
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// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
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// Read LUTs
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FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
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FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
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0,
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0,
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0x24040405,
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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0x00000406,
|
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0,
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0,
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0,
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0,
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0,
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0,
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0,
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|
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0x08180420,
|
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0,
|
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0,
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0,
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||||
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0,
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0,
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0,
|
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0,
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|
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0,
|
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0,
|
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0,
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0,
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|
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0x081804D8,
|
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0,
|
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0,
|
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0,
|
||||
|
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0x08180402,
|
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0x00002004,
|
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0,
|
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0,
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|
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0,
|
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0,
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0,
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0,
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|
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0x00000460,
|
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},
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},
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.pageSize = 256u,
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.sectorSize = 4u * 1024u,
|
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.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
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.blockSize = 0x00010000,
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.isUniformBlockSize = false,
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};
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@ -1,22 +1,8 @@
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LD_FILE = boards/mimxrt1011-bootloader-external-flash.ld
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USB_VID = 0x239A
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USB_PID = 0x8078
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USB_PRODUCT = "IMXRT1010-EVK"
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USB_MANUFACTURER = "NXP"
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USB_DEVICES = "CDC,MSC,HID"
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CHIP_VARIANT = MIMXRT1011DAE5A
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CHIP_FAMILY = MIMXRT1011
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INTERNAL_FLASH_FILESYSTEM = 1
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CIRCUITPY_DISPLAYIO = 0
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CIRCUITPY_AUDIOIO = 0
|
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CIRCUITPY_AUDIOBUSIO = 0
|
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CIRCUITPY_FREQUENCYIO = 0
|
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CIRCUITPY_I2CSLAVE = 0
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CIRCUITPY_NEOPIXEL_WRITE = 0
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CIRCUITPY_NVM = 0
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CIRCUITPY_ROTARYIO = 0
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LONGINT_IMPL = MPZ
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FLASH = AT25SF128A
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@ -0,0 +1,39 @@
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
|
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*
|
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* Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
|
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* Copyright (c) 2019 Artur Pacholec
|
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*
|
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "boards/board.h"
|
||||
#include "mpconfigboard.h"
|
||||
|
||||
void board_init(void) {
|
||||
}
|
||||
|
||||
bool board_requests_safe_mode(void) {
|
||||
return false;
|
||||
}
|
||||
|
||||
void reset_board(void) {
|
||||
}
|
||||
@ -0,0 +1,122 @@
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_flexspi_nor_boot.h"
|
||||
#include "fsl_flexspi_nor_config.h"
|
||||
|
||||
|
||||
__attribute__((section(".boot_hdr.ivt")))
|
||||
/*************************************
|
||||
* IVT Data
|
||||
*************************************/
|
||||
const ivt image_vector_table = {
|
||||
IVT_HEADER, /* IVT Header */
|
||||
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
|
||||
IVT_RSVD, /* Reserved = 0 */
|
||||
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
|
||||
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
|
||||
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
|
||||
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
|
||||
IVT_RSVD /* Reserved = 0 */
|
||||
};
|
||||
|
||||
__attribute__((section(".boot_hdr.boot_data")))
|
||||
/*************************************
|
||||
* Boot Data
|
||||
*************************************/
|
||||
const BOOT_DATA_T boot_data = {
|
||||
FLASH_BASE, /* boot start location */
|
||||
FLASH_SIZE, /* size */
|
||||
PLUGIN_FLAG, /* Plugin flag*/
|
||||
0xFFFFFFFF /* empty - extra data word */
|
||||
};
|
||||
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 1u,
|
||||
.csSetupTime = 2u,
|
||||
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
|
||||
.sflashA1Size = FLASH_SIZE,
|
||||
.lookupTable =
|
||||
{
|
||||
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
|
||||
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
|
||||
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
// Read LUTs
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
0,
|
||||
0,
|
||||
|
||||
0x24040405,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x00000406,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x08180420,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x081804D8,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x08180402,
|
||||
0x00002004,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x00000460,
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
|
||||
.blockSize = 0x00010000,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
@ -0,0 +1,14 @@
|
||||
#define MICROPY_HW_BOARD_NAME "iMX RT 1020 EVK"
|
||||
#define MICROPY_HW_MCU_NAME "IMXRT1021DAG5A"
|
||||
|
||||
// If you change this, then make sure to update the linker scripts as well to
|
||||
// make sure you don't overwrite code
|
||||
#define CIRCUITPY_INTERNAL_NVM_SIZE 0
|
||||
|
||||
#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
|
||||
|
||||
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_SD_B1_03)
|
||||
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_SD_B1_02)
|
||||
|
||||
#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B1_09)
|
||||
#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B1_08)
|
||||
@ -0,0 +1,8 @@
|
||||
USB_VID = 0x16C0
|
||||
USB_PID = 0x8888
|
||||
USB_PRODUCT = "iMX RT 1020 EVK"
|
||||
USB_MANUFACTURER = "NXP"
|
||||
|
||||
CHIP_VARIANT = MIMXRT1021DAG5A
|
||||
CHIP_FAMILY = MIMXRT1021
|
||||
FLASH = IS25LP064A
|
||||
@ -0,0 +1,84 @@
|
||||
#include "shared-bindings/board/__init__.h"
|
||||
|
||||
#include "boards/board.h"
|
||||
|
||||
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_B0_07) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_AD_B0_06) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
|
||||
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
|
||||
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
|
||||
|
||||
// SD Card
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_GPIO_SD_B0_06) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_PWREN), MP_ROM_PTR(&pin_GPIO_SD_B1_04) },
|
||||
|
||||
// // Audio Interface
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
|
||||
|
||||
// // Ethernet
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDIO), MP_ROM_PTR(&pin_GPIO_EMC_40) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDC), MP_ROM_PTR(&pin_GPIO_EMC_41) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD0), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD1), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CRS_DV), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD0), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD1), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXEN), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CLK), MP_ROM_PTR(&pin_GPIO_AD_B0_08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXER), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
|
||||
|
||||
// // Freelink UART
|
||||
{ MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_07) },
|
||||
|
||||
// CAN
|
||||
{ MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_SD_B1_00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_SD_B1_01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_CAN_STBY), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
|
||||
|
||||
//
|
||||
{ MP_ROM_QSTR(MP_QSTR_ACCELEROMETER_SDA), MP_ROM_PTR(&pin_GPIO_SD_B1_03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ACCELEROMETER_SCL), MP_ROM_PTR(&pin_GPIO_SD_B1_02) },
|
||||
|
||||
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
|
||||
};
|
||||
MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
|
||||
@ -0,0 +1,39 @@
|
||||
/*
|
||||
* This file is part of the MicroPython project, http://micropython.org/
|
||||
*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2019 Scott Shawcroft for Adafruit Industries
|
||||
* Copyright (c) 2019 Artur Pacholec
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "boards/board.h"
|
||||
#include "mpconfigboard.h"
|
||||
|
||||
void board_init(void) {
|
||||
}
|
||||
|
||||
bool board_requests_safe_mode(void) {
|
||||
return false;
|
||||
}
|
||||
|
||||
void reset_board(void) {
|
||||
}
|
||||
@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright 2017 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "fsl_flexspi_nor_boot.h"
|
||||
#include "fsl_flexspi_nor_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_device"
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.ivt")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location=".boot_hdr.ivt"
|
||||
#endif
|
||||
/*************************************
|
||||
* IVT Data
|
||||
*************************************/
|
||||
const ivt image_vector_table = {
|
||||
IVT_HEADER, /* IVT Header */
|
||||
IMAGE_ENTRY_ADDRESS, /* Image Entry Function */
|
||||
IVT_RSVD, /* Reserved = 0 */
|
||||
(uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */
|
||||
(uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */
|
||||
(uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */
|
||||
(uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */
|
||||
IVT_RSVD /* Reserved = 0 */
|
||||
};
|
||||
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.boot_data")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location=".boot_hdr.boot_data"
|
||||
#endif
|
||||
/*************************************
|
||||
* Boot Data
|
||||
*************************************/
|
||||
const BOOT_DATA_T boot_data = {
|
||||
FLASH_BASE, /* boot start location */
|
||||
FLASH_SIZE, /* size */
|
||||
PLUGIN_FLAG, /* Plugin flag*/
|
||||
0xFFFFFFFF /* empty - extra data word */
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf")))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
// Values copied from https://github.com/PaulStoffregen/cores/blob/ddb23fa5d97dac763bc06e11b9b41f026bd51f0a/teensy4/bootdata.c#L39
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 1u,
|
||||
.csSetupTime = 2u,
|
||||
// Enable DDR mode, Wordaddressable, Safe configuration, Differential clock
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_60MHz, // 03
|
||||
.sflashA1Size = FLASH_SIZE,
|
||||
.lookupTable =
|
||||
{
|
||||
// FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
|
||||
// (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |
|
||||
// FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
// Read LUTs
|
||||
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
|
||||
FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
0,
|
||||
0,
|
||||
|
||||
0x24040405,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x00000406,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x08180420,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x081804D8,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x08180402,
|
||||
0x00002004,
|
||||
0,
|
||||
0,
|
||||
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
|
||||
0x00000460,
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.ipcmdSerialClkFreq = kFlexSpiSerialClk_30MHz,
|
||||
.blockSize = 0x00010000,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
@ -0,0 +1,14 @@
|
||||
#define MICROPY_HW_BOARD_NAME "iMX RT 1060 EVK"
|
||||
#define MICROPY_HW_MCU_NAME "IMXRT1062DVJ6A"
|
||||
|
||||
// If you change this, then make sure to update the linker scripts as well to
|
||||
// make sure you don't overwrite code
|
||||
#define CIRCUITPY_INTERNAL_NVM_SIZE 0
|
||||
|
||||
#define BOARD_FLASH_SIZE (8 * 1024 * 1024)
|
||||
|
||||
#define DEFAULT_I2C_BUS_SCL (&pin_GPIO_AD_B1_00)
|
||||
#define DEFAULT_I2C_BUS_SDA (&pin_GPIO_AD_B1_01)
|
||||
|
||||
#define DEFAULT_UART_BUS_RX (&pin_GPIO_AD_B1_07)
|
||||
#define DEFAULT_UART_BUS_TX (&pin_GPIO_AD_B1_06)
|
||||
@ -0,0 +1,8 @@
|
||||
USB_VID = 0x16C0
|
||||
USB_PID = 0x8888
|
||||
USB_PRODUCT = "iMX RT 1060 EVK"
|
||||
USB_MANUFACTURER = "NXP"
|
||||
|
||||
CHIP_VARIANT = MIMXRT1062DVJ6A
|
||||
CHIP_FAMILY = MIMXRT1062
|
||||
FLASH = IS25WP064A
|
||||
@ -0,0 +1,128 @@
|
||||
#include "shared-bindings/board/__init__.h"
|
||||
|
||||
#include "boards/board.h"
|
||||
|
||||
STATIC const mp_rom_map_elem_t board_global_dict_table[] = {
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO_AD_B0_09) }, // Connected to audio codec
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO_AD_B0_10) }, // Connected to audio codec
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO_AD_B0_03) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO_AD_B0_02) }, // Connected to audio codec
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
|
||||
|
||||
// i2c sensor is on I2C1_SCL/SDA
|
||||
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO_AD_B1_01) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_A5), MP_ROM_PTR(&pin_GPIO_AD_B1_00) },
|
||||
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_USER_LED), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
|
||||
|
||||
// Camera Sensor Interface
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_VSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_06) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PWDN), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_HSYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_07) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D9), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_05) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D8), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D7), MP_ROM_PTR(&pin_GPIO_AD_B1_10) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_PIXCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_04) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D6), MP_ROM_PTR(&pin_GPIO_AD_B1_11) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D2), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D5), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D3), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_CSI_D4), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
|
||||
|
||||
// SD Card
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CLK), MP_ROM_PTR(&pin_GPIO_SD_B0_01) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_SW), MP_ROM_PTR(&pin_GPIO_B1_12) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_CMD), MP_ROM_PTR(&pin_GPIO_SD_B0_00) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D0), MP_ROM_PTR(&pin_GPIO_SD_B0_02) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D1), MP_ROM_PTR(&pin_GPIO_SD_B0_03) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D2), MP_ROM_PTR(&pin_GPIO_SD_B0_04) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_D3), MP_ROM_PTR(&pin_GPIO_SD_B0_05) },
|
||||
{ MP_OBJ_NEW_QSTR(MP_QSTR_SD_PWREN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
|
||||
|
||||
// LCD Interface
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_BACKLIGHT), MP_ROM_PTR(&pin_GPIO_B1_15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_ENABLE), MP_ROM_PTR(&pin_GPIO_B0_01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_VSYNC), MP_ROM_PTR(&pin_GPIO_B0_03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_HSYNC), MP_ROM_PTR(&pin_GPIO_B0_02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_CLK), MP_ROM_PTR(&pin_GPIO_B0_00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D0), MP_ROM_PTR(&pin_GPIO_B0_04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D1), MP_ROM_PTR(&pin_GPIO_B0_05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D2), MP_ROM_PTR(&pin_GPIO_B0_06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D3), MP_ROM_PTR(&pin_GPIO_B0_07) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D4), MP_ROM_PTR(&pin_GPIO_B0_08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D5), MP_ROM_PTR(&pin_GPIO_B0_09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D6), MP_ROM_PTR(&pin_GPIO_B0_10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D7), MP_ROM_PTR(&pin_GPIO_B0_11) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D8), MP_ROM_PTR(&pin_GPIO_B0_12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D9), MP_ROM_PTR(&pin_GPIO_B0_13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D10), MP_ROM_PTR(&pin_GPIO_B0_14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D11), MP_ROM_PTR(&pin_GPIO_B0_15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D12), MP_ROM_PTR(&pin_GPIO_B1_00) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D13), MP_ROM_PTR(&pin_GPIO_B1_01) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D14), MP_ROM_PTR(&pin_GPIO_B1_02) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_D15), MP_ROM_PTR(&pin_GPIO_B1_03) },
|
||||
|
||||
// Touch Interface
|
||||
{ MP_ROM_QSTR(MP_QSTR_LCD_TOUCH_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_11) },
|
||||
|
||||
// Audio Interface
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_INT), MP_ROM_PTR(&pin_GPIO_AD_B1_08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_SYNC), MP_ROM_PTR(&pin_GPIO_AD_B1_15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_BCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_RXD), MP_ROM_PTR(&pin_GPIO_AD_B1_12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_TXD), MP_ROM_PTR(&pin_GPIO_AD_B1_13) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_AUDIO_MCLK), MP_ROM_PTR(&pin_GPIO_AD_B1_09) },
|
||||
|
||||
// SPDIF
|
||||
{ MP_ROM_QSTR(MP_QSTR_SPDIF_IN), MP_ROM_PTR(&pin_GPIO_AD_B1_03) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_SPDIF_OUT), MP_ROM_PTR(&pin_GPIO_AD_B1_02) },
|
||||
|
||||
// Ethernet
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDIO), MP_ROM_PTR(&pin_GPIO_EMC_41) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_MDC), MP_ROM_PTR(&pin_GPIO_EMC_40) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD0), MP_ROM_PTR(&pin_GPIO_B1_04) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXD1), MP_ROM_PTR(&pin_GPIO_B1_05) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CRS_DV), MP_ROM_PTR(&pin_GPIO_B1_06) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD0), MP_ROM_PTR(&pin_GPIO_B1_07) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXD1), MP_ROM_PTR(&pin_GPIO_B1_08) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_TXEN), MP_ROM_PTR(&pin_GPIO_B1_09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_INT), MP_ROM_PTR(&pin_GPIO_AD_B0_10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RST), MP_ROM_PTR(&pin_GPIO_AD_B0_09) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_CLK), MP_ROM_PTR(&pin_GPIO_B1_10) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_ETHERNET_RXER), MP_ROM_PTR(&pin_GPIO_B1_11) },
|
||||
|
||||
// Freelink UART
|
||||
{ MP_ROM_QSTR(MP_QSTR_FREELINK_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_12) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_FREELINK_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_13) },
|
||||
|
||||
// CAN
|
||||
{ MP_ROM_QSTR(MP_QSTR_CAN_TX), MP_ROM_PTR(&pin_GPIO_AD_B0_14) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_CAN_RX), MP_ROM_PTR(&pin_GPIO_AD_B0_15) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_CAN_STBY), MP_ROM_PTR(&pin_GPIO_AD_B0_05) },
|
||||
|
||||
{ MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj) },
|
||||
{ MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj) },
|
||||
};
|
||||
MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table);
|
||||
@ -1,106 +0,0 @@
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
_minimum_stack_size = 64K;
|
||||
_minimum_heap_size = 0;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 8M
|
||||
FLASH_BOOTLOADER (rx) : ORIGIN = 0x60000000, LENGTH = 48K
|
||||
FLASH_ISR (rx) : ORIGIN = 0x6000C000, LENGTH = 1K
|
||||
FLASH_TEXT (rx) : ORIGIN = 0x6000C400, LENGTH = 975K
|
||||
FLASH_FATFS (r) : ORIGIN = 0x60100000, LENGTH = 7M
|
||||
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 32K
|
||||
OCRAM (rwx) : ORIGIN = 0x20200000, LENGTH = 64K
|
||||
}
|
||||
|
||||
_estack = ORIGIN(OCRAM) + LENGTH(OCRAM);
|
||||
_bootloader_dbl_tap = ORIGIN(RAM) + LENGTH(RAM) - 4;
|
||||
|
||||
__fatfs_flash_start_addr = ORIGIN(FLASH_FATFS);
|
||||
__fatfs_flash_length = LENGTH(FLASH_FATFS);
|
||||
|
||||