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Base support for nrf51 and nrf52 base without depending on SDK. SoftDevice usage optional.

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crypto-aes
Glenn Ruben Bakke 6 years ago
parent 4f7b5eab7f
commit 70956ea969
66 changed files with 28080 additions and 0 deletions
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167
nrf5/Makefile
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# Select the board to build for: if not given on the command line,
# then default to pca10040.
BOARD ?= pca10040
ifeq ($(wildcard boards/$(BOARD)/.),)
$(error Invalid BOARD specified)
endif
# If SoftDevice is selected, try to use that one.
SD ?= none
SD_LOWER = $(shell echo $(SD) | tr '[:upper:]' '[:lower:]')
# TODO: Verify that it is a valid target.
ifeq ($(SD), none)
# If the build directory is not given, make it reflect the board name.
BUILD ?= build-$(BOARD)
include ../py/mkenv.mk
include boards/$(BOARD)/mpconfigboard.mk
else
# If the build directory is not given, make it reflect the board name.
BUILD ?= build-$(BOARD)-$(SD_LOWER)
include ../py/mkenv.mk
include boards/$(BOARD)/mpconfigboard_$(SD_LOWER).mk
endif
# qstr definitions (must come before including py.mk)
QSTR_DEFS = qstrdefsport.h
# include py core make definitions
include ../py/py.mk
CROSS_COMPILE = arm-none-eabi-
MCU_VARIANT_LOWER = $(shell echo $(MCU_VARIANT) | tr '[:upper:]' '[:lower:]')
INC = -I.
INC += -I..
INC += -I$(BUILD)
INC += -I./device
INC += -I./../lib/cmsis/inc
INC += -I./device
INC += -I./device/$(MCU_VARIANT_LOWER)
INC += -I./hal
INC += -I./hal/$(MCU_VARIANT_LOWER)
INC += -I./drivers
INC += -I../lib/mp-readline
NRF_DEFINES = -D$(MCU_VARIANT)
NRF_DEFINES += -DCONFIG_GPIO_AS_PINRESET
CFLAGS_CORTEX_M = -mthumb -mabi=aapcs -fsingle-precision-constant -Wdouble-promotion
CFLAGS_MCU_m4 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard
CFLAGS_MCU_m0 = $(CFLAGS_CORTEX_M) --short-enums -mtune=cortex-m0 -mcpu=cortex-m0 -mfloat-abi=soft -fno-builtin
CFLAGS = $(CFLAGS_MCU_$(MCU_SERIES))
CFLAGS += $(INC) -Wall -Werror -ansi -std=gnu99 -nostdlib $(COPT) $(NRF_DEFINES)
CFLAGS += -Iboards/$(BOARD)
LDFLAGS = $(CFLAGS)
LDFLAGS += -Xlinker -Map=$(@:.elf=.map)
LDFLAGS += -mthumb -mabi=aapcs -T $(LD_FILE)
LDFLAGS += -mcpu=cortex-m0
#Debugging/Optimization
ifeq ($(DEBUG), 1)
CFLAGS += -O0 -ggdb
LDFLAGS += -O0
else
CFLAGS += -Os -DNDEBUG
LDFLAGS += -Os
endif
LIBS =
SRC_LIB = $(addprefix lib/,\
libc/string0.c \
mp-readline/readline.c \
utils/pyexec.c \
utils/pyhelp.c \
)
SRC_C = \
main.c \
device/$(MCU_VARIANT_LOWER)/system_$(MCU_VARIANT_LOWER).c \
modpyb.c \
led.c \
mphalport.c \
uart.c \
help.c \
gccollect.c \
ifeq ($(NRF_SOFTDEVICE),NRF_S1XX_SOFTDEVICE)
SRC_C += \
hal/hal_uarte.c \
softdevice/modble.c \
softdevice/softdevice.c
CFLAGS += -I./softdevice
CFLAGS += -I./softdevice/s1xx/headers
CFLAGS += -I./softdevice/s1xx/headers/nrf52
CFLAGS += -DBLUETOOTH_SD=100
CFLAGS += -DBLUETOOTH_SD_DEBUG=1
else ifeq ($(NRF_SOFTDEVICE),NRF_S132_SOFTDEVICE)
SRC_C += \
hal/hal_uarte.c \
softdevice/modble.c \
softdevice/softdevice.c
CFLAGS += -I./softdevice
CFLAGS += -I./softdevice/s132/headers
CFLAGS += -I./softdevice/s132/headers/nrf52
CFLAGS += -DBLUETOOTH_SD=132
CFLAGS += -DBLUETOOTH_SD_DEBUG=1
else ifeq ($(NRF_SOFTDEVICE),NRF_S110_SOFTDEVICE)
SRC_C += \
hal/hal_uart.c \
softdevice/modble.c \
softdevice/softdevice.c
CFLAGS += -I./softdevice
CFLAGS += -I./softdevice/s110/headers
CFLAGS += -DBLUETOOTH_SD=110
CFLAGS += -DBLUETOOTH_SD_DEBUG=1
else ifeq ($(NRF_SOFTDEVICE),NRF_S130_SOFTDEVICE)
SRC_C += \
hal/hal_uart.c \
softdevice/modble.c \
softdevice/softdevice.c
CFLAGS += -I./softdevice
CFLAGS += -I./softdevice/s130/headers
CFLAGS += -DBLUETOOTH_SD=130
CFLAGS += -DBLUETOOTH_SD_DEBUG=1
else
SRC_C += \
hal/hal_uart.c
endif
SRC_S = \
device/$(MCU_VARIANT_LOWER)/startup_$(MCU_VARIANT_LOWER).s \
OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o))
OBJ += $(addprefix $(BUILD)/, $(SRC_LIB:.c=.o))
.phony: all flash
all: $(BUILD)/firmware.elf binary hex
flash: $(BUILD)/firmware.elf
nrfjprog --program $(BUILD)/firmware.hex --sectorerase -f $(MCU_VARIANT_LOWER)
nrfjprog --pinreset -f $(MCU_VARIANT_LOWER)
$(BUILD)/firmware.elf: $(OBJ)
$(ECHO) "LINK $@"
$(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
$(Q)$(SIZE) $@
SRC_QSTR += $(SRC_C) $(SRC_MOD) $(SRC_LIB)
include ../py/mkrules.mk
include mkrules.mk

103
nrf5/boards/common.ld
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/* define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH_ISR
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
/* *(.glue_7) */ /* glue arm to thumb code */
/* *(.glue_7t) */ /* glue thumb to arm code */
. = ALIGN(4);
_etext = .; /* define a global symbol at end of code */
} >FLASH_TEXT
/*
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
*/
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
_ram_start = .; /* create a global symbol at ram start for garbage collector */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
} >RAM AT> FLASH_TEXT
/* Uninitialized data section */
.bss :
{
. = ALIGN(4);
_sbss = .; /* define a global symbol at bss start; used by startup code */
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
} >RAM
/* this is to define the start of the heap, and make sure we have a minimum size */
.heap :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
_heap_start = .; /* define a global symbol at heap start */
. = . + _minimum_heap_size;
} >RAM
/* this just checks there is enough RAM for the stack */
.stack :
{
. = ALIGN(4);
. = . + _minimum_stack_size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/*
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
*/
.ARM.attributes 0 : { *(.ARM.attributes) }
}

28
nrf5/boards/nrf51822_aa.ld
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/*
GNU linker script for NRF52 blank w/ no SoftDevice
*/
/* Specify the memory areas */
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x000400 /* sector 0, 1 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03FC00 /* 255 KiB */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x004000 /* 16 KiB */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 10K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20001000; /* tunable */
INCLUDE "boards/common.ld"

28
nrf5/boards/nrf51822_aa_s110.ld
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/*
GNU linker script for NRF51822 AA w/ S110 8.0.0 SoftDevice
*/
/* Specify the memory areas */
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 175 KiB */
RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x002000 /* 9.89 KiB */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 4K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20003000; /* tunable */
INCLUDE "boards/common.ld"

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nrf5/boards/nrf51822_ac.ld
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/*
GNU linker script for NRF52 blank w/ no SoftDevice
*/
/* Specify the memory areas */
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x000400 /* sector 0, 1 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x00000400, LENGTH = 0x03F000 /* 255 KiB */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x008000 /* 32 KiB */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 10K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20001000; /* tunable */
INCLUDE "boards/common.ld"

28
nrf5/boards/nrf51822_ac_s110.ld
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/*
GNU linker script for NRF51822 AC w/ S110 8.0.0 SoftDevice
*/
/* Specify the memory areas */
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
FLASH_ISR (rx) : ORIGIN = 0x00018000, LENGTH = 0x000400 /* sector 0, 1 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x00018400, LENGTH = 0x027c00 /* 175 KiB */
RAM (xrw) : ORIGIN = 0x20002000, LENGTH = 0x006000 /* 9.89 KiB */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 4K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20003000; /* tunable */
INCLUDE "boards/common.ld"

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nrf5/boards/nrf51822_ac_s120.ld
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/*
GNU linker script for NRF51822 AC w/ S120 2.1.0 SoftDevice
*/
/* Specify the memory areas */
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
FLASH_ISR (rx) : ORIGIN = 0x0001D000, LENGTH = 0x000400 /* sector 0, 1 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x0001D400, LENGTH = 0x027c00 /* 139 KiB */
RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x005800 /* 22 KiB */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 4K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20003000; /* tunable */
INCLUDE "boards/common.ld"

28
nrf5/boards/nrf51822_ac_s130.ld
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/*
GNU linker script for NRF51822 AC w/ S130 2.0.0 SoftDevice
*/
/* Specify the memory areas */
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x040000 /* entire flash, 256 KiB */
FLASH_ISR (rx) : ORIGIN = 0x0001b000, LENGTH = 0x000400 /* sector 0, 1 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x0001b400, LENGTH = 0x024c00 /* 147 KiB */
RAM (xrw) : ORIGIN = 0x20001870, LENGTH = 0x002970 /* 9.89 KiB */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 6K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20002000; /* tunable */
INCLUDE "boards/common.ld"

27
nrf5/boards/nrf52832_aa.ld
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/*
GNU linker script for NRF52 blank w/ no SoftDevice
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 256 KiB */
FLASH_ISR (rx) : ORIGIN = 0x00000000, LENGTH = 0x001000 /* sector 0, 4 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x00001000, LENGTH = 0x07F000 /* 508 KiB */
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x010000 /* 64 KiB */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20005000; /* tunable */
INCLUDE "boards/common.ld"

27
nrf5/boards/nrf52832_aa_s132.ld
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/*
GNU linker script for NRF52 w/ s132 3.0.0 SoftDevice
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x080000 /* entire flash, 512 KiB */
FLASH_ISR (rx) : ORIGIN = 0x0001f000, LENGTH = 0x001000 /* sector 0, 4 KiB */
FLASH_TEXT (rx) : ORIGIN = 0x00020000, LENGTH = 0x060000 /* 396 KiB */
RAM (xrw) : ORIGIN = 0x200039c0, LENGTH = 0x0c640 /* 57.89 KiB, give 8KiB headroom for softdevice */
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 2K;
_minimum_heap_size = 16K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20005000; /* tunable */
INCLUDE "boards/common.ld"

129
nrf5/boards/nrf52832_aa_s1xx.ld
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/*
GNU linker script for NRF52 w/ s1xx prototype3 softdevice (IPv6)
*/
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x0001F000, LENGTH = 0x61000
FLASH_ISR (rx) : ORIGIN = 0x0001F000, LENGTH = 0x00400
FLASH_TEXT (rx) : ORIGIN = 0x0001F400, LENGTH = 0x60c00
RAM (xrw) : ORIGIN = 0x20002800, LENGTH = 0x0D800
}
/* produce a link error if there is not this amount of RAM for these sections */
_minimum_stack_size = 6K;
_minimum_heap_size = 16K;
/* top end of the stack */
/*_stack_end = ORIGIN(RAM) + LENGTH(RAM);*/
_estack = ORIGIN(RAM) + LENGTH(RAM);
/* RAM extents for the garbage collector */
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
_heap_end = 0x20005000; /* tunable */
/* define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH_ISR
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
/* *(.glue_7) */ /* glue arm to thumb code */
/* *(.glue_7t) */ /* glue thumb to arm code */
. = ALIGN(4);
_etext = .; /* define a global symbol at end of code */
} >FLASH_TEXT
/*
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
.ARM :
{
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
*/
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
_ram_start = .; /* create a global symbol at ram start for garbage collector */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
} >RAM AT> FLASH_TEXT
/* Uninitialized data section */
.bss :
{
. = ALIGN(4);
_sbss = .; /* define a global symbol at bss start; used by startup code */
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end; used by startup code and GC */
} >RAM
/* this is to define the start of the heap, and make sure we have a minimum size */
.heap :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
_heap_start = .; /* define a global symbol at heap start */
. = . + _minimum_heap_size;
} >RAM
/* this just checks there is enough RAM for the stack */
.stack :
{
. = ALIGN(4);
. = . + _minimum_stack_size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/*
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
*/
.ARM.attributes 0 : { *(.ARM.attributes) }
}

60
nrf5/boards/pca10000/mpconfigboard.h
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/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define PCA10000
#define MICROPY_HW_BOARD_NAME "PCA10000"
#define MICROPY_HW_MCU_NAME "NRF51822"
#define MICROPY_PY_SYS_PLATFORM "nrf51-dongle"
#define MICROPY_HW_HAS_SWITCH (0)
#define MICROPY_HW_HAS_FLASH (0)
#define MICROPY_HW_HAS_SDCARD (0)
#define MICROPY_HW_HAS_MMA7660 (0)
#define MICROPY_HW_HAS_LIS3DSH (0)
#define MICROPY_HW_HAS_LCD (0)
#define MICROPY_HW_ENABLE_RNG (0)
#define MICROPY_HW_ENABLE_RTC (0)
#define MICROPY_HW_ENABLE_TIMER (0)
#define MICROPY_HW_ENABLE_SERVO (0)
#define MICROPY_HW_ENABLE_DAC (0)
#define MICROPY_HW_ENABLE_CAN (0)
#define MICROPY_HW_LED_TRICOLOR (1)
#define MICROPY_HW_LED_PULLUP (1)
#define MICROPY_HW_LED_RED (21) // RED
#define MICROPY_HW_LED_GREEN (22) // GREEN
#define MICROPY_HW_LED_BLUE (23) // BLUE
// UART config
#define MICROPY_HW_UART1_RX (11)
#define MICROPY_HW_UART1_TX (9)
#define MICROPY_HW_UART1_CTS (10)
#define MICROPY_HW_UART1_RTS (8)
#define MICROPY_HW_UART1_HWFC (0)
#define HELP_TEXT_BOARD_LED "1,2,3"

3
nrf5/boards/pca10000/mpconfigboard.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_aa.ld

4
nrf5/boards/pca10000/mpconfigboard_s110.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_aa_s110.ld
NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE

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nrf5/boards/pca10001/mpconfigboard.h
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/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define PCA10001
#define MICROPY_HW_BOARD_NAME "PCA10001"
#define MICROPY_HW_MCU_NAME "NRF51822"
#define MICROPY_PY_SYS_PLATFORM "nrf51-DK"
#define MICROPY_HW_HAS_SWITCH (0)
#define MICROPY_HW_HAS_FLASH (0)
#define MICROPY_HW_HAS_SDCARD (0)
#define MICROPY_HW_HAS_MMA7660 (0)
#define MICROPY_HW_HAS_LIS3DSH (0)
#define MICROPY_HW_HAS_LCD (0)
#define MICROPY_HW_ENABLE_RNG (0)
#define MICROPY_HW_ENABLE_RTC (0)
#define MICROPY_HW_ENABLE_TIMER (0)
#define MICROPY_HW_ENABLE_SERVO (0)
#define MICROPY_HW_ENABLE_DAC (0)
#define MICROPY_HW_ENABLE_CAN (0)
#define MICROPY_HW_LED_COUNT (2)
#define MICROPY_HW_LED_PULLUP (0)
#define MICROPY_HW_LED1 (18) // LED1
#define MICROPY_HW_LED2 (19) // LED2
// UART config
#define MICROPY_HW_UART1_RX (11)
#define MICROPY_HW_UART1_TX (9)
#define MICROPY_HW_UART1_CTS (10)
#define MICROPY_HW_UART1_RTS (8)
#define MICROPY_HW_UART1_HWFC (1)
#define HELP_TEXT_BOARD_LED "1,2"

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nrf5/boards/pca10001/mpconfigboard.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_aa.ld

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nrf5/boards/pca10028/mpconfigboard.h
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/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define PCA10028
#define MICROPY_HW_BOARD_NAME "PCA10028"
#define MICROPY_HW_MCU_NAME "NRF51822"
#define MICROPY_PY_SYS_PLATFORM "nrf51-DK"
#define MICROPY_HW_HAS_SWITCH (0)
#define MICROPY_HW_HAS_FLASH (0)
#define MICROPY_HW_HAS_SDCARD (0)
#define MICROPY_HW_HAS_MMA7660 (0)
#define MICROPY_HW_HAS_LIS3DSH (0)
#define MICROPY_HW_HAS_LCD (0)
#define MICROPY_HW_ENABLE_RNG (0)
#define MICROPY_HW_ENABLE_RTC (0)
#define MICROPY_HW_ENABLE_TIMER (0)
#define MICROPY_HW_ENABLE_SERVO (0)
#define MICROPY_HW_ENABLE_DAC (0)
#define MICROPY_HW_ENABLE_CAN (0)
#define MICROPY_HW_LED_PULLUP (1)
#define MICROPY_HW_LED1 (21) // LED1
#define MICROPY_HW_LED2 (22) // LED2
#define MICROPY_HW_LED3 (23) // LED3
#define MICROPY_HW_LED4 (24) // LED4
// UART config
#define MICROPY_HW_UART1_RX (11)
#define MICROPY_HW_UART1_TX (9)
#define MICROPY_HW_UART1_CTS (10)
#define MICROPY_HW_UART1_RTS (8)
#define MICROPY_HW_UART1_HWFC (0)
#define HELP_TEXT_BOARD_LED "1,2,3,4"

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nrf5/boards/pca10028/mpconfigboard.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac.ld

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nrf5/boards/pca10028/mpconfigboard_s110.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac_s110.ld
NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE

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nrf5/boards/pca10028/mpconfigboard_s120.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac_s120.ld
NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE

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nrf5/boards/pca10028/mpconfigboard_s130.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac_s130.ld
NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE

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nrf5/boards/pca10031/mpconfigboard.h
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/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define PCA10031
#define MICROPY_HW_BOARD_NAME "PCA10031"
#define MICROPY_HW_MCU_NAME "NRF51822"
#define MICROPY_PY_SYS_PLATFORM "nrf51-dongle"
#define MICROPY_HW_HAS_SWITCH (0)
#define MICROPY_HW_HAS_FLASH (0)
#define MICROPY_HW_HAS_SDCARD (0)
#define MICROPY_HW_HAS_MMA7660 (0)
#define MICROPY_HW_HAS_LIS3DSH (0)
#define MICROPY_HW_HAS_LCD (0)
#define MICROPY_HW_ENABLE_RNG (0)
#define MICROPY_HW_ENABLE_RTC (0)
#define MICROPY_HW_ENABLE_TIMER (0)
#define MICROPY_HW_ENABLE_SERVO (0)
#define MICROPY_HW_ENABLE_DAC (0)
#define MICROPY_HW_ENABLE_CAN (0)
#define MICROPY_HW_LED_TRICOLOR (1)
#define MICROPY_HW_LED_PULLUP (1)
#define MICROPY_HW_LED_RED (21) // RED
#define MICROPY_HW_LED_GREEN (22) // GREEN
#define MICROPY_HW_LED_BLUE (23) // BLUE
// UART config
#define MICROPY_HW_UART1_RX (11)
#define MICROPY_HW_UART1_TX (9)
#define MICROPY_HW_UART1_CTS (10)
#define MICROPY_HW_UART1_RTS (8)
#define MICROPY_HW_UART1_HWFC (0)
#define HELP_TEXT_BOARD_LED "1,2,3"

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nrf5/boards/pca10031/mpconfigboard.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac.ld

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nrf5/boards/pca10031/mpconfigboard_s110.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac_s110.ld
NRF_SOFTDEVICE = NRF_S110_SOFTDEVICE

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nrf5/boards/pca10031/mpconfigboard_s120.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac_s120.ld
NRF_SOFTDEVICE = NRF_S120_SOFTDEVICE

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nrf5/boards/pca10031/mpconfigboard_s130.mk
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MCU_SERIES = m0
MCU_VARIANT = NRF51
LD_FILE = boards/nrf51822_ac_s130.ld
NRF_SOFTDEVICE = NRF_S130_SOFTDEVICE

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nrf5/boards/pca10040/mpconfigboard.h
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/*
* This file is part of the Micro Python project, http://micropython.org/
*
* The MIT License (MIT)
*
* Copyright (c) 2016 Glenn Ruben Bakke
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define PCA10040
#define MICROPY_HW_BOARD_NAME "PCA10040"
#define MICROPY_HW_MCU_NAME "NRF52832"
#define MICROPY_PY_SYS_PLATFORM "nrf52-DK"
#define MICROPY_HW_HAS_SWITCH (0)
#define MICROPY_HW_HAS_FLASH (0)
#define MICROPY_HW_HAS_SDCARD (0)
#define MICROPY_HW_HAS_MMA7660 (0)
#define MICROPY_HW_HAS_LIS3DSH (0)
#define MICROPY_HW_HAS_LCD (0)
#define MICROPY_HW_ENABLE_RNG (0)
#define MICROPY_HW_ENABLE_RTC (0)
#define MICROPY_HW_ENABLE_TIMER (0)
#define MICROPY_HW_ENABLE_SERVO (0)
#define MICROPY_HW_ENABLE_DAC (0)
#define MICROPY_HW_ENABLE_CAN (0)
#define MICROPY_HW_LED_PULLUP (1)
#define MICROPY_HW_LED1 (17) // LED1
#define MICROPY_HW_LED2 (18) // LED2
#define MICROPY_HW_LED3 (19) // LED3
#define MICROPY_HW_LED4 (20) // LED4
// UART config
#define MICROPY_HW_UART1_RX (8)
#define MICROPY_HW_UART1_TX (6)
#define MICROPY_HW_UART1_CTS (7)
#define MICROPY_HW_UART1_RTS (5)
#define MICROPY_HW_UART1_HWFC (1)
#define HELP_TEXT_BOARD_LED "1,2,3,4"

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nrf5/boards/pca10040/mpconfigboard.mk
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MCU_SERIES = m4
MCU_VARIANT = NRF52
LD_FILE = boards/nrf52832_aa.ld

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nrf5/boards/pca10040/mpconfigboard_s132.mk
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MCU_SERIES = m4
MCU_VARIANT = NRF52
LD_FILE = boards/nrf52832_aa_s132.ld
NRF_SOFTDEVICE = NRF_S132_SOFTDEVICE

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nrf5/boards/pca10040/mpconfigboard_s1xx.mk
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MCU_SERIES = m4
MCU_VARIANT = NRF52
LD_FILE = boards/nrf52832_aa_s1xx.ld
NRF_SOFTDEVICE = NRF_S1XX_SOFTDEVICE

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nrf5/device/compiler_abstraction.h
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/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _COMPILER_ABSTRACTION_H
#define _COMPILER_ABSTRACTION_H
/*lint ++flb "Enter library region" */
#if defined ( __CC_ARM )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#define GET_SP() __current_sp()
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define STRING_PRAGMA(x) _Pragma(#x)
#define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#define GET_SP() __get_SP()
#elif defined ( __GNUC__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __attribute__((aligned(n)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#define GET_SP() gcc_current_sp()
static inline unsigned int gcc_current_sp(void)
{
register unsigned sp __ASM("sp");
return sp;
}
#elif defined ( __TASKING__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#endif
/* Not defined for TASKING. */
#ifndef __PACKED
#define __PACKED
#endif
#define GET_SP() __get_MSP()
#endif
/*lint --flb "Leave library region" */
#endif

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nrf5/device/nrf.h
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/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF_H
#define NRF_H
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 9
#define MDK_MICRO_VERSION 0
#if defined(_WIN32)
/* Do not include nrf51 specific files when building for PC host */
#elif defined(__unix)
/* Do not include nrf51 specific files when building for PC host */
#elif defined(__APPLE__)
/* Do not include nrf51 specific files when building for PC host */
#else
/* Family selection for family includes. */
#if defined (NRF51)
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "nrf51_deprecated.h"
#elif defined (NRF52)
#include "nrf52.h"
#include "nrf52_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_name_change.h"
#else
#error "Device family must be defined. See nrf.h."
#endif /* NRF51, NRF52 */
#include "compiler_abstraction.h"
#endif /* _WIN32 || __unix || __APPLE__ */
#endif /* NRF_H */

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nrf5/device/nrf51/nrf51_deprecated.h
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/* Copyright (c) 2016, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF51_DEPRECATED_H
#define NRF51_DEPRECATED_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and
* nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
*/
/* NVMC */
/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
#define ERASEPROTECTEDPAGE ERASEPCR0
/* LPCOMP */
/* The interrupt ISR was renamed. Adding old name to the macros. */
#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler
#define LPCOMP_COMP_IRQn LPCOMP_IRQn
/* Corrected typo in RESULT register. */
#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below
/* MPU */
/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos
#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk
#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1
#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0
/* POWER */
/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM3_Pos (19UL)
#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos)
#define POWER_RAMON_OFFRAM3_RAM3Off (0UL)
#define POWER_RAMON_OFFRAM3_RAM3On (1UL)
/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_OFFRAM2_Pos (18UL)
#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos)
#define POWER_RAMON_OFFRAM2_RAM2Off (0UL)
#define POWER_RAMON_OFFRAM2_RAM2On (1UL)
/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM3_Pos (3UL)
#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos)
#define POWER_RAMON_ONRAM3_RAM3Off (0UL)
#define POWER_RAMON_ONRAM3_RAM3On (1UL)
/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
#define POWER_RAMON_ONRAM2_Pos (2UL)
#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos)
#define POWER_RAMON_ONRAM2_RAM2Off (0UL)
#define POWER_RAMON_ONRAM2_RAM2On (1UL)
/* RADIO */
/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm
/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos
#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk
#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include
#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip
/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos
#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk
#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled
#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled
/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos
#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk
#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled
#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled
/* FICR */
/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
#define SIZERAMBLOCK0 SIZERAMBLOCKS
#define SIZERAMBLOCK1 SIZERAMBLOCKS
#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
#define DEVICEID0 DEVICEID[0]
#define DEVICEID1 DEVICEID[1]
/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
#define ER0 ER[0]
#define ER1 ER[1]
#define ER2 ER[2]
#define ER3 ER[3]
/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
#define IR0 IR[0]
#define IR1 IR[1]
#define IR2 IR[2]
#define IR3 IR[3]
/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
#define DEVICEADDR0 DEVICEADDR[0]
#define DEVICEADDR1 DEVICEADDR[1]
/* PPI */
/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
#define TASKS_CHG0EN TASKS_CHG[0].EN
#define TASKS_CHG0DIS TASKS_CHG[0].DIS
#define TASKS_CHG1EN TASKS_CHG[1].EN
#define TASKS_CHG1DIS TASKS_CHG[1].DIS
#define TASKS_CHG2EN TASKS_CHG[2].EN
#define TASKS_CHG2DIS TASKS_CHG[2].DIS
#define TASKS_CHG3EN TASKS_CHG[3].EN
#define TASKS_CHG3DIS TASKS_CHG[3].DIS
/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
#define CH0_EEP CH[0].EEP
#define CH0_TEP CH[0].TEP
#define CH1_EEP CH[1].EEP
#define CH1_TEP CH[1].TEP
#define CH2_EEP CH[2].EEP
#define CH2_TEP CH[2].TEP
#define CH3_EEP CH[3].EEP
#define CH3_TEP CH[3].TEP
#define CH4_EEP CH[4].EEP
#define CH4_TEP CH[4].TEP
#define CH5_EEP CH[5].EEP
#define CH5_TEP CH[5].TEP
#define CH6_EEP CH[6].EEP
#define CH6_TEP CH[6].TEP
#define CH7_EEP CH[7].EEP
#define CH7_TEP CH[7].TEP
#define CH8_EEP CH[8].EEP
#define CH8_TEP CH[8].TEP
#define CH9_EEP CH[9].EEP
#define CH9_TEP CH[9].TEP
#define CH10_EEP CH[10].EEP
#define CH10_TEP CH[10].TEP
#define CH11_EEP CH[11].EEP
#define CH11_TEP CH[11].TEP
#define CH12_EEP CH[12].EEP
#define CH12_TEP CH[12].TEP
#define CH13_EEP CH[13].EEP
#define CH13_TEP CH[13].TEP
#define CH14_EEP CH[14].EEP
#define CH14_TEP CH[14].TEP
#define CH15_EEP CH[15].EEP
#define CH15_TEP CH[15].TEP
/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
#define CHG0 CHG[0]
#define CHG1 CHG[1]
#define CHG2 CHG[2]
#define CHG3 CHG[3]
/* All bitfield macros for the CHGx registers therefore changed name. */
#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded
#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included
#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos
#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk
#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded
#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included
#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos
#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk
#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded
#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included
#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos
#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk
#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded
#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included
#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos
#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk
#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded
#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included
#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos
#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk
#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded
#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included
#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos
#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk
#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded
#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included
#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos
#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk
#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded
#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included
#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos
#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk
#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded
#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included
#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos
#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk
#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded
#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included
#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos
#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk
#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded
#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included
#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos
#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk
#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded
#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included
#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos
#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk
#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded
#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included
#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos
#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk
#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded
#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included
#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos
#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk
#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded
#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included
#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos
#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk
#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded
#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included
#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos
#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk
#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded
#