samd51 peripheral clocks were defined as 12MHz, but were really 120MHz

crypto-aes
Dan Halbert 5 years ago committed by Scott Shawcroft
parent 1d6bf8e04a
commit 6f662e9bbc

@ -41,7 +41,7 @@
* \brief ADC0's Clock frequency
*/
#ifndef CONF_GCLK_ADC0_FREQUENCY
#define CONF_GCLK_ADC0_FREQUENCY 12000000
#define CONF_GCLK_ADC0_FREQUENCY 120000000
#endif
// <y> DAC Clock Source
@ -81,7 +81,7 @@
* \brief DAC's Clock frequency
*/
#ifndef CONF_GCLK_DAC_FREQUENCY
#define CONF_GCLK_DAC_FREQUENCY 12000000
#define CONF_GCLK_DAC_FREQUENCY 120000000
#endif
// <y> EVSYS Channel 0 Clock Source
@ -122,7 +122,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 1 Clock Source
@ -163,7 +163,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 2 Clock Source
@ -204,7 +204,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 3 Clock Source
@ -245,7 +245,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 4 Clock Source
@ -286,7 +286,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 5 Clock Source
@ -327,7 +327,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 6 Clock Source
@ -368,7 +368,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 7 Clock Source
@ -409,7 +409,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 8 Clock Source
@ -450,7 +450,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 9 Clock Source
@ -491,7 +491,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 10 Clock Source
@ -532,7 +532,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0
#endif
// <y> EVSYS Channel 11 Clock Source
@ -573,7 +573,7 @@
*/
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000.0
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0
#endif
/**
@ -581,7 +581,7 @@
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 12000000
#define CONF_CPU_FREQUENCY 120000000
#endif
// <y> RTC Clock Source
@ -877,7 +877,7 @@
* \brief TC0's Clock frequency
*/
#ifndef CONF_GCLK_TC0_FREQUENCY
#define CONF_GCLK_TC0_FREQUENCY 12000000
#define CONF_GCLK_TC0_FREQUENCY 120000000
#endif
// <y> USB Clock Source

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