Also, fixed pin mappings for rev B Metro M4: swap PA12 and PA13 on SPI 2x3 header swap A3 and A5 Comment out all frozen modules in CPX again to make room while waiting for SPI flash.crypto-aes
Dan Halbert
5 years ago
parent
9564f7b90e
commit
312444bbd2
@ -1 +1 @@
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Subproject commit 7ffa51e117eb6d6b6679febfc77e50d03731b467
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Subproject commit 72f76894ba08c9de2ec3ae231fb71daaf3eafb1e
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File diff suppressed because it is too large
Load Diff
@ -1,113 +1,926 @@
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// Derived from: Auto-generated config file peripheral_clk_config.h
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// Boilerplate removed.
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/* Auto-generated config file peripheral_clk_config.h */
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#ifndef PERIPHERAL_CLK_CONFIG_H
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#define PERIPHERAL_CLK_CONFIG_H
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// ADC
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// <<< Use Configuration Wizard in Context Menu >>>
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// <y> ADC Clock Source
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// <id> adc_gclk_selection
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for ADC.
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#ifndef CONF_GCLK_ADC0_SRC
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#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_ADC0_FREQUENCY 120000000
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#endif
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/**
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* \def CONF_GCLK_ADC0_FREQUENCY
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* \brief ADC0's Clock frequency
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*/
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#ifndef CONF_GCLK_ADC0_FREQUENCY
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#define CONF_GCLK_ADC0_FREQUENCY 12000000
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#endif
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// <y> DAC Clock Source
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// DAC
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <id> dac_gclk_selection
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// <i> Select the clock source for DAC.
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#ifndef CONF_GCLK_DAC_SRC
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#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_DAC_FREQUENCY 120000000
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#endif
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/**
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* \def CONF_GCLK_DAC_FREQUENCY
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* \brief DAC's Clock frequency
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*/
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#ifndef CONF_GCLK_DAC_FREQUENCY
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#define CONF_GCLK_DAC_FREQUENCY 12000000
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#endif
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// <y> EVSYS Channel 0 Clock Source
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// <id> evsys_clk_selection_0
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// EVSYS
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 0.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 1 Clock Source
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// <id> evsys_clk_selection_1
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 1.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 2 Clock Source
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// <id> evsys_clk_selection_2
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 2.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 3 Clock Source
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// <id> evsys_clk_selection_3
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 3.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 4 Clock Source
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// <id> evsys_clk_selection_4
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 4.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 5 Clock Source
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// <id> evsys_clk_selection_5
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 5.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 6 Clock Source
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// <id> evsys_clk_selection_6
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 6.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 7 Clock Source
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// <id> evsys_clk_selection_7
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
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// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
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// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
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// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
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// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
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// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
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// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
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// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
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// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
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// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
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// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
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// <i> Select the clock source for channel 7.
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#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC
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#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
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#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0
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#endif
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/**
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* \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
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* \brief EVSYS's Clock frequency
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*/
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#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY
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#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000.0
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#endif
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// <y> EVSYS Channel 8 Clock Source
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// <id> evsys_clk_selection_8
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// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
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||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 8.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000.0
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 9 Clock Source
|
||||
// <id> evsys_clk_selection_9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 9.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000.0
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 10 Clock Source
|
||||
// <id> evsys_clk_selection_10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 10.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000.0
|
||||
#endif
|
||||
|
||||
// <y> EVSYS Channel 11 Clock Source
|
||||
// <id> evsys_clk_selection_11
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
|
||||
|
||||
// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
|
||||
|
||||
// <i> Select the clock source for channel 11.
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
|
||||
* \brief EVSYS's Clock frequency
|
||||
*/
|
||||
|
||||
// CPU: 120 MHz
|
||||
#define CONF_CPU_FREQUENCY 120000000
|
||||
#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY
|
||||
#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000.0
|
||||
#endif
|
||||
|
||||
// RTC
|
||||
/**
|
||||
* \def CONF_CPU_FREQUENCY
|
||||
* \brief CPU's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_CPU_FREQUENCY
|
||||
#define CONF_CPU_FREQUENCY 12000000
|
||||
#endif
|
||||
|
||||
// <y> RTC Clock Source
|
||||
// <id> rtc_clk_selection
|
||||
// <RTC_CLOCK_SOURCE"> RTC source
|
||||
// <i> Select the clock source for RTC.
|
||||
#ifndef CONF_GCLK_RTC_SRC
|
||||
#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \def CONF_GCLK_RTC_FREQUENCY
|
||||
* \brief RTC's Clock frequency
|
||||
*/
|
||||
#ifndef CONF_GCLK_RTC_FREQUENCY
|
||||