Add core files and use same toolchain as stmhal

crypto-aes
Dave Hylands 9 years ago
parent 4d9dd26818
commit 04f5ae1d1c

@ -6,14 +6,7 @@ QSTR_DEFS = qstrdefsport.h
# include py core make definitions
include ../py/py.mk
ifeq ($(ARDUINO),)
$(error Please define ARDUINO (where TeensyDuino is installed))
endif
TOOLS_PATH = $(ARDUINO)/hardware/tools
COMPILER_PATH = $(TOOLS_PATH)/arm-none-eabi/bin
CORE_PATH = $(ARDUINO)/hardware/teensy/cores/teensy3
CROSS_COMPILE = $(COMPILER_PATH)/arm-none-eabi-
CROSS_COMPILE = arm-none-eabi-
CFLAGS_TEENSY = -DF_CPU=96000000 -DUSB_SERIAL -D__MK20DX256__
CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mcpu=cortex-m4 -fsingle-precision-constant -Wdouble-promotion $(CFLAGS_TEENSY)
@ -22,13 +15,26 @@ INC = -I.
INC += -I$(PY_SRC)
INC += -I../stmhal
INC += -I$(BUILD)
INC += -I$(CORE_PATH)
INC += -Icore
CFLAGS = $(INC) -Wall -ansi -std=gnu99 -nostdlib $(CFLAGS_CORTEX_M4)
LDFLAGS = -nostdlib -T mk20dx256.ld
LIBS = -L $(COMPILER_PATH)/../arm-none-eabi/lib/thumb2 -lm
LIBS += -L $(COMPILER_PATH)/../arm-none-eabi/lib/thumb2 -lc
LIBS += -L $(COMPILER_PATH)/../lib/gcc/arm-none-eabi/4.7.2/thumb2 -lgcc
LIBGCC_FILE_NAME = $(shell $(CC) -print-libgcc-file-name)
LIBM_FILE_NAME = $(shell $(CC) -print-file-name=libm.a)
LIBC_FILE_NAME = $(shell $(CC) -print-file-name=libc.a)
#$(info %%%%% LIBGCC_FILE_NAME = $(LIBGCC_FILE_NAME))
#$(info %%%%% LIBM_FILE_NAME = $(LIBM_FILE_NAME))
#$(info %%%%% LIBC_FILE_NAME = $(LIBC_FILE_NAME))
#$(info %%%%% dirname LIBGCC_FILE_NAME = $(dir $(LIBGCC_FILE_NAME)))
#$(info %%%%% dirname LIBM_FILE_NAME = $(dir $(LIBM_FILE_NAME)))
#$(info %%%%% dirname LIBC_FILE_NAME = $(dir $(LIBC_FILE_NAME)))
LIBS = -L $(dir $(LIBM_FILE_NAME)) -lm
LIBS += -L $(dir $(LIBC_FILE_NAME)) -lc
LIBS += -L $(dir $(LIBGCC_FILE_NAME)) -lgcc
#Debugging/Optimization
ifdef DEBUG
@ -67,7 +73,7 @@ STM_SRC_S = $(addprefix stmhal/,\
gchelper.s \
)
SRC_TEENSY = \
SRC_TEENSY = $(addprefix core/,\
mk20dx128.c \
pins_teensy.c \
analog.c \
@ -76,6 +82,7 @@ SRC_TEENSY = \
usb_mem.c \
usb_serial.c \
yield.c \
)
OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(STM_SRC_C:.c=.o) $(STM_SRC_S:.s=.o) $(SRC_TEENSY:.c=.o))
OBJ += $(BUILD)/pins_gen.o
@ -83,6 +90,18 @@ OBJ += $(BUILD)/pins_gen.o
all: hex
hex: $(BUILD)/micropython-mz.hex
ifeq ($(ARDUINO),)
post_compile: $(BUILD)/micropython-mz.hex
$(ECHO) "Please define ARDUINO (where TeensyDuino is installed)"
exit 1
reboot:
$(ECHO) "Please define ARDUINO (where TeensyDuino is installed)"
exit 1
else
TOOLS_PATH = $(ARDUINO)/hardware/tools
post_compile: $(BUILD)/micropython-mz.hex
$(ECHO) "Preparing $@ for upload"
$(Q)$(TOOLS_PATH)/teensy_post_compile -file="$(basename $(<F))" -path="$(<D)" -tools="$(TOOLS_PATH)"
@ -90,8 +109,10 @@ post_compile: $(BUILD)/micropython-mz.hex
reboot:
$(ECHO) "REBOOT"
-$(Q)$(TOOLS_PATH)/teensy_reboot
endif
upload: post_compile reboot
.PHONY: deploy
deploy: post_compile reboot
$(BUILD)/micropython.elf: $(OBJ)
$(ECHO) "LINK $@"
@ -110,9 +131,6 @@ $(BUILD)/%.hex: $(BUILD)/%.elf
$(ECHO) "HEX $<"
$(Q)$(OBJCOPY) -O ihex -R .eeprom "$<" "$@"
$(BUILD)/%.o: $(CORE_PATH)/%.c
$(call compile_c)
MAKE_PINS = make-pins.py
BOARD_PINS = teensy-pins.csv
AF_FILE = mk20dx256-af.csv

@ -0,0 +1,3 @@
//#include "WProgram.h"
#include "core_pins.h"
#include "pins_arduino.h"

@ -0,0 +1,227 @@
/* Teensyduino Core Library
* http://www.pjrc.com/teensy/
* Copyright (c) 2013 PJRC.COM, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef HardwareSerial_h
#define HardwareSerial_h
#include "mk20dx128.h"
#include <inttypes.h>
// uncomment to enable 9 bit formats
//#define SERIAL_9BIT_SUPPORT
#define SERIAL_7E1 0x02
#define SERIAL_7O1 0x03
#define SERIAL_8N1 0x00
#define SERIAL_8N2 0x04
#define SERIAL_8E1 0x06
#define SERIAL_8O1 0x07
#define SERIAL_7E1_RXINV 0x12
#define SERIAL_7O1_RXINV 0x13
#define SERIAL_8N1_RXINV 0x10
#define SERIAL_8N2_RXINV 0x14
#define SERIAL_8E1_RXINV 0x16
#define SERIAL_8O1_RXINV 0x17
#define SERIAL_7E1_TXINV 0x22
#define SERIAL_7O1_TXINV 0x23
#define SERIAL_8N1_TXINV 0x20
#define SERIAL_8N2_TXINV 0x24
#define SERIAL_8E1_TXINV 0x26
#define SERIAL_8O1_TXINV 0x27
#define SERIAL_7E1_RXINV_TXINV 0x32
#define SERIAL_7O1_RXINV_TXINV 0x33
#define SERIAL_8N1_RXINV_TXINV 0x30
#define SERIAL_8N2_RXINV_TXINV 0x34
#define SERIAL_8E1_RXINV_TXINV 0x36
#define SERIAL_8O1_RXINV_TXINV 0x37
#ifdef SERIAL_9BIT_SUPPORT
#define SERIAL_9N1 0x84
#define SERIAL_9E1 0x8E
#define SERIAL_9O1 0x8F
#define SERIAL_9N1_RXINV 0x94
#define SERIAL_9E1_RXINV 0x9E
#define SERIAL_9O1_RXINV 0x9F
#define SERIAL_9N1_TXINV 0xA4
#define SERIAL_9E1_TXINV 0xAE
#define SERIAL_9O1_TXINV 0xAF
#define SERIAL_9N1_RXINV_TXINV 0xB4
#define SERIAL_9E1_RXINV_TXINV 0xBE
#define SERIAL_9O1_RXINV_TXINV 0xBF
#endif
// bit0: parity, 0=even, 1=odd
// bit1: parity, 0=disable, 1=enable
// bit2: mode, 1=9bit, 0=8bit
// bit3: mode10: 1=10bit, 0=8bit
// bit4: rxinv, 0=normal, 1=inverted
// bit5: txinv, 0=normal, 1=inverted
// bit6: unused
// bit7: actual data goes into 9th bit
#define BAUD2DIV(baud) (((F_CPU * 2) + ((baud) >> 1)) / (baud))
#define BAUD2DIV3(baud) (((F_BUS * 2) + ((baud) >> 1)) / (baud))
// C language implementation
//
#ifdef __cplusplus
extern "C" {
#endif
void serial_begin(uint32_t divisor);
void serial_format(uint32_t format);
void serial_end(void);
void serial_set_transmit_pin(uint8_t pin);
void serial_putchar(uint32_t c);
void serial_write(const void *buf, unsigned int count);
void serial_flush(void);
int serial_available(void);
int serial_getchar(void);
int serial_peek(void);
void serial_clear(void);
void serial_print(const char *p);
void serial_phex(uint32_t n);
void serial_phex16(uint32_t n);
void serial_phex32(uint32_t n);
void serial2_begin(uint32_t divisor);
void serial2_format(uint32_t format);
void serial2_end(void);
void serial2_putchar(uint32_t c);
void serial2_write(const void *buf, unsigned int count);
void serial2_flush(void);
int serial2_available(void);
int serial2_getchar(void);
int serial2_peek(void);
void serial2_clear(void);
void serial3_begin(uint32_t divisor);
void serial3_format(uint32_t format);
void serial3_end(void);
void serial3_putchar(uint32_t c);
void serial3_write(const void *buf, unsigned int count);
void serial3_flush(void);
int serial3_available(void);
int serial3_getchar(void);
int serial3_peek(void);
void serial3_clear(void);
#ifdef __cplusplus
}
#endif
// C++ interface
//
#ifdef __cplusplus
#include "Stream.h"
class HardwareSerial : public Stream
{
public:
virtual void begin(uint32_t baud) { serial_begin(BAUD2DIV(baud)); }
virtual void begin(uint32_t baud, uint32_t format) {
serial_begin(BAUD2DIV(baud));
serial_format(format); }
virtual void end(void) { serial_end(); }
virtual void transmitterEnable(uint8_t pin) { serial_set_transmit_pin(pin); }
virtual int available(void) { return serial_available(); }
virtual int peek(void) { return serial_peek(); }
virtual int read(void) { return serial_getchar(); }
virtual void flush(void) { serial_flush(); }
virtual void clear(void) { serial_clear(); }
virtual size_t write(uint8_t c) { serial_putchar(c); return 1; }
virtual size_t write(unsigned long n) { return write((uint8_t)n); }
virtual size_t write(long n) { return write((uint8_t)n); }
virtual size_t write(unsigned int n) { return write((uint8_t)n); }
virtual size_t write(int n) { return write((uint8_t)n); }
virtual size_t write(const uint8_t *buffer, size_t size)
{ serial_write(buffer, size); return size; }
virtual size_t write(const char *str) { size_t len = strlen(str);
serial_write((const uint8_t *)str, len);
return len; }
virtual size_t write9bit(uint32_t c) { serial_putchar(c); return 1; }
};
extern HardwareSerial Serial1;
class HardwareSerial2 : public HardwareSerial
{
public:
virtual void begin(uint32_t baud) { serial2_begin(BAUD2DIV(baud)); }
virtual void begin(uint32_t baud, uint32_t format) {
serial2_begin(BAUD2DIV(baud));
serial2_format(format); }
virtual void end(void) { serial2_end(); }
virtual int available(void) { return serial2_available(); }
virtual int peek(void) { return serial2_peek(); }
virtual int read(void) { return serial2_getchar(); }
virtual void flush(void) { serial2_flush(); }
virtual void clear(void) { serial2_clear(); }
virtual size_t write(uint8_t c) { serial2_putchar(c); return 1; }
virtual size_t write(unsigned long n) { return write((uint8_t)n); }
virtual size_t write(long n) { return write((uint8_t)n); }
virtual size_t write(unsigned int n) { return write((uint8_t)n); }
virtual size_t write(int n) { return write((uint8_t)n); }
virtual size_t write(const uint8_t *buffer, size_t size)
{ serial2_write(buffer, size); return size; }
virtual size_t write(const char *str) { size_t len = strlen(str);
serial2_write((const uint8_t *)str, len);
return len; }
virtual size_t write9bit(uint32_t c) { serial2_putchar(c); return 1; }
};
extern HardwareSerial2 Serial2;
class HardwareSerial3 : public HardwareSerial
{
public:
virtual void begin(uint32_t baud) { serial3_begin(BAUD2DIV3(baud)); }
virtual void begin(uint32_t baud, uint32_t format) {
serial3_begin(BAUD2DIV3(baud));
serial3_format(format); }
virtual void end(void) { serial3_end(); }
virtual int available(void) { return serial3_available(); }
virtual int peek(void) { return serial3_peek(); }
virtual int read(void) { return serial3_getchar(); }
virtual void flush(void) { serial3_flush(); }
virtual void clear(void) { serial3_clear(); }
virtual size_t write(uint8_t c) { serial3_putchar(c); return 1; }
virtual size_t write(unsigned long n) { return write((uint8_t)n); }
virtual size_t write(long n) { return write((uint8_t)n); }
virtual size_t write(unsigned int n) { return write((uint8_t)n); }
virtual size_t write(int n) { return write((uint8_t)n); }
virtual size_t write(const uint8_t *buffer, size_t size)
{ serial3_write(buffer, size); return size; }
virtual size_t write(const char *str) { size_t len = strlen(str);
serial3_write((const uint8_t *)str, len);
return len; }
virtual size_t write9bit(uint32_t c) { serial3_putchar(c); return 1; }
};
extern HardwareSerial3 Serial3;
#endif
#endif

@ -0,0 +1,463 @@
/* Teensyduino Core Library
* http://www.pjrc.com/teensy/
* Copyright (c) 2013 PJRC.COM, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include "core_pins.h"
//#include "HardwareSerial.h"
static uint8_t calibrating;
static uint8_t analog_right_shift = 0;
static uint8_t analog_config_bits = 10;
static uint8_t analog_num_average = 4;
static uint8_t analog_reference_internal = 0;
// the alternate clock is connected to OSCERCLK (16 MHz).
// datasheet says ADC clock should be 2 to 12 MHz for 16 bit mode
// datasheet says ADC clock should be 1 to 18 MHz for 8-12 bit mode
#if F_BUS == 60000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7.5 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 15 MHz
#elif F_BUS == 56000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(2) + ADC_CFG1_ADICLK(1) // 7 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 14 MHz
#elif F_BUS == 48000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 12 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 24 MHz
#elif F_BUS == 40000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 10 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 20 MHz
#elif F_BUS == 36000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(1) // 9 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(1) // 18 MHz
#elif F_BUS == 24000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(1) + ADC_CFG1_ADICLK(0) // 12 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 24 MHz
#elif F_BUS == 16000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 16 MHz
#elif F_BUS == 8000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 8 MHz
#elif F_BUS == 4000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 4 MHz
#elif F_BUS == 2000000
#define ADC_CFG1_16BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
#define ADC_CFG1_12BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
#define ADC_CFG1_10BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
#define ADC_CFG1_8BIT ADC_CFG1_ADIV(0) + ADC_CFG1_ADICLK(0) // 2 MHz
#else
#error "F_BUS must be 60, 56, 48, 40, 36, 24, 4 or 2 MHz"
#endif
void analog_init(void)
{
uint32_t num;
VREF_TRM = 0x60;
VREF_SC = 0xE1; // enable 1.2 volt ref
if (analog_config_bits == 8) {
ADC0_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
#if defined(__MK20DX256__)
ADC1_CFG1 = ADC_CFG1_8BIT + ADC_CFG1_MODE(0);
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
#endif
} else if (analog_config_bits == 10) {
ADC0_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
#if defined(__MK20DX256__)
ADC1_CFG1 = ADC_CFG1_10BIT + ADC_CFG1_MODE(2) + ADC_CFG1_ADLSMP;
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(3);
#endif
} else if (analog_config_bits == 12) {
ADC0_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
#if defined(__MK20DX256__)
ADC1_CFG1 = ADC_CFG1_12BIT + ADC_CFG1_MODE(1) + ADC_CFG1_ADLSMP;
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
#endif
} else {
ADC0_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
ADC0_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
#if defined(__MK20DX256__)
ADC1_CFG1 = ADC_CFG1_16BIT + ADC_CFG1_MODE(3) + ADC_CFG1_ADLSMP;
ADC1_CFG2 = ADC_CFG2_MUXSEL + ADC_CFG2_ADLSTS(2);
#endif
}
if (analog_reference_internal) {
ADC0_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
#if defined(__MK20DX256__)
ADC1_SC2 = ADC_SC2_REFSEL(1); // 1.2V ref
#endif
} else {
ADC0_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
#if defined(__MK20DX256__)
ADC1_SC2 = ADC_SC2_REFSEL(0); // vcc/ext ref
#endif
}
num = analog_num_average;
if (num <= 1) {
ADC0_SC3 = ADC_SC3_CAL; // begin cal
#if defined(__MK20DX256__)
ADC1_SC3 = ADC_SC3_CAL; // begin cal
#endif
} else if (num <= 4) {
ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
#if defined(__MK20DX256__)
ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(0);
#endif
} else if (num <= 8) {
ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
#if defined(__MK20DX256__)
ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(1);
#endif
} else if (num <= 16) {
ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
#if defined(__MK20DX256__)
ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(2);
#endif
} else {
ADC0_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
#if defined(__MK20DX256__)
ADC1_SC3 = ADC_SC3_CAL + ADC_SC3_AVGE + ADC_SC3_AVGS(3);
#endif
}
calibrating = 1;
}
static void wait_for_cal(void)
{
uint16_t sum;
//serial_print("wait_for_cal\n");
#if defined(__MK20DX128__)
while (ADC0_SC3 & ADC_SC3_CAL) {
// wait
}
#elif defined(__MK20DX256__)
while ((ADC0_SC3 & ADC_SC3_CAL) || (ADC1_SC3 & ADC_SC3_CAL)) {
// wait
}
#endif
__disable_irq();
if (calibrating) {
//serial_print("\n");
sum = ADC0_CLPS + ADC0_CLP4 + ADC0_CLP3 + ADC0_CLP2 + ADC0_CLP1 + ADC0_CLP0;
sum = (sum / 2) | 0x8000;
ADC0_PG = sum;
//serial_print("ADC0_PG = ");
//serial_phex16(sum);
//serial_print("\n");
sum = ADC0_CLMS + ADC0_CLM4 + ADC0_CLM3 + ADC0_CLM2 + ADC0_CLM1 + ADC0_CLM0;
sum = (sum / 2) | 0x8000;
ADC0_MG = sum;
//serial_print("ADC0_MG = ");
//serial_phex16(sum);
//serial_print("\n");
#if defined(__MK20DX256__)
sum = ADC1_CLPS + ADC1_CLP4 + ADC1_CLP3 + ADC1_CLP2 + ADC1_CLP1 + ADC1_CLP0;
sum = (sum / 2) | 0x8000;
ADC1_PG = sum;
sum = ADC1_CLMS + ADC1_CLM4 + ADC1_CLM3 + ADC1_CLM2 + ADC1_CLM1 + ADC1_CLM0;
sum = (sum / 2) | 0x8000;
ADC1_MG = sum;
#endif
calibrating = 0;
}
__enable_irq();
}
// ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC.
// VREFH/VREFL - connected as the primary reference option
// 1.2 V VREF_OUT - connected as the VALT reference option
#define DEFAULT 0
#define INTERNAL 2
#define INTERNAL1V2 2
#define INTERNAL1V1 2
#define EXTERNAL 0
void analogReference(uint8_t type)
{
if (type) {
// internal reference requested
if (!analog_reference_internal) {
analog_reference_internal = 1;
if (calibrating) {
ADC0_SC3 = 0; // cancel cal
#if defined(__MK20DX256__)
ADC1_SC3 = 0; // cancel cal
#endif
}
analog_init();
}
} else {
// vcc or external reference requested
if (analog_reference_internal) {
analog_reference_internal = 0;
if (calibrating) {
ADC0_SC3 = 0; // cancel cal
#if defined(__MK20DX256__)
ADC1_SC3 = 0; // cancel cal
#endif
}
analog_init();
}
}
}
void analogReadRes(unsigned int bits)
{
unsigned int config;
if (bits >= 13) {
if (bits > 16) bits = 16;
config = 16;
} else if (bits >= 11) {
config = 12;
} else if (bits >= 9) {
config = 10;
} else {
config = 8;
}
analog_right_shift = config - bits;
if (config != analog_config_bits) {
analog_config_bits = config;
if (calibrating) ADC0_SC3 = 0; // cancel cal
analog_init();
}
}
void analogReadAveraging(unsigned int num)
{
if (calibrating) wait_for_cal();
if (num <= 1) {
num = 0;
ADC0_SC3 = 0;
} else if (num <= 4) {
num = 4;
ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(0);
} else if (num <= 8) {
num = 8;
ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(1);
} else if (num <= 16) {
num = 16;
ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(2);
} else {
num = 32;
ADC0_SC3 = ADC_SC3_AVGE + ADC_SC3_AVGS(3);
}
analog_num_average = num;
}
// The SC1A register is used for both software and hardware trigger modes of operation.
#if defined(__MK20DX128__)
static const uint8_t channel2sc1a[] = {
5, 14, 8, 9, 13, 12, 6, 7, 15, 4,
0, 19, 3, 21, 26, 22, 23
};
#elif defined(__MK20DX256__)
static const uint8_t channel2sc1a[] = {
5, 14, 8, 9, 13, 12, 6, 7, 15, 4,
0, 19, 3, 19+128, 26, 18+128, 23,
5+192, 5+128, 4+128, 6+128, 7+128, 4+192
// A15 26 E1 ADC1_SE5a 5+64
// A16 27 C9 ADC1_SE5b 5
// A17 28 C8 ADC1_SE4b 4
// A18 29 C10 ADC1_SE6b 6
// A19 30 C11 ADC1_SE7b 7
// A20 31 E0 ADC1_SE4a 4+64
};
#endif
// TODO: perhaps this should store the NVIC priority, so it works recursively?
static volatile uint8_t analogReadBusyADC0 = 0;
#if defined(__MK20DX256__)
static volatile uint8_t analogReadBusyADC1 = 0;
#endif
int analogRead(uint8_t pin)
{
int result;
uint8_t index, channel;
//serial_phex(pin);
//serial_print(" ");
if (pin <= 13) {
index = pin; // 0-13 refer to A0-A13
} else if (pin <= 23) {
index = pin - 14; // 14-23 are A0-A9
#if defined(__MK20DX256__)
} else if (pin >= 26 && pin <= 31) {
index = pin - 9; // 26-31 are A15-A20
#endif
} else if (pin >= 34 && pin <= 40) {
index = pin - 24; // 34-37 are A10-A13, 38 is temp sensor,
// 39 is vref, 40 is unused (A14 on Teensy 3.1)
} else {
return 0; // all others are invalid
}
//serial_phex(index);
//serial_print(" ");
channel = channel2sc1a[index];
//serial_phex(channel);
//serial_print(" ");
//serial_print("analogRead");
//return 0;
if (calibrating) wait_for_cal();
//pin = 5; // PTD1/SE5b, pin 14, analog 0
#if defined(__MK20DX256__)
if (channel & 0x80) goto beginADC1;
#endif
__disable_irq();
startADC0:
//serial_print("startADC0\n");
ADC0_SC1A = channel;
analogReadBusyADC0 = 1;
__enable_irq();
while (1) {
__disable_irq();
if ((ADC0_SC1A & ADC_SC1_COCO)) {
result = ADC0_RA;
analogReadBusyADC0 = 0;
__enable_irq();
result >>= analog_right_shift;
return result;
}
// detect if analogRead was used from an interrupt
// if so, our analogRead got canceled, so it must
// be restarted.
if (!analogReadBusyADC0) goto startADC0;
__enable_irq();
yield();
}
#if defined(__MK20DX256__)
beginADC1:
__disable_irq();
startADC1:
//serial_print("startADC0\n");
// ADC1_CFG2[MUXSEL] bit selects between ADCx_SEn channels a and b.
if (channel & 0x40) {
ADC1_CFG2 &= ~ADC_CFG2_MUXSEL;
} else {
ADC1_CFG2 |= ADC_CFG2_MUXSEL;
}
ADC1_SC1A = channel & 0x3F;
analogReadBusyADC1 = 1;
__enable_irq();
while (1) {
__disable_irq();
if ((ADC1_SC1A & ADC_SC1_COCO)) {
result = ADC1_RA;
analogReadBusyADC1 = 0;
__enable_irq();
result >>= analog_right_shift;
return result;
}
// detect if analogRead was used from an interrupt
// if so, our analogRead got canceled, so it must
// be restarted.
if (!analogReadBusyADC1) goto startADC1;
__enable_irq();
yield();
}
#endif
}
void analogWriteDAC0(int val)
{
#if defined(__MK20DX256__)
SIM_SCGC2 |= SIM_SCGC2_DAC0;
if (analog_reference_internal) {
DAC0_C0 = DAC_C0_DACEN; // 1.2V ref is DACREF_1
} else {
DAC0_C0 = DAC_C0_DACEN | DAC_C0_DACRFS; // 3.3V VDDA is DACREF_2
}
if (val < 0) val = 0; // TODO: saturate instruction?
else if (val > 4095) val = 4095;
*(int16_t *)&(DAC0_DAT0L) = val;
#endif
}

@ -0,0 +1,107 @@
/* Teensyduino Core Library
* http://www.pjrc.com/teensy/
* Copyright (c) 2013 PJRC.COM, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _avr_functions_h_
#define _avr_functions_h_
#include <inttypes.h>
#ifdef __cplusplus
extern "C" {
#endif
void eeprom_initialize(void);
uint8_t eeprom_read_byte(const uint8_t *addr) __attribute__ ((pure));
uint16_t eeprom_read_word(const uint16_t *addr) __attribute__ ((pure));
uint32_t eeprom_read_dword(const uint32_t *addr) __attribute__ ((pure));
void eeprom_read_block(void *buf, const void *addr, uint32_t len);
void eeprom_write_byte(uint8_t *addr, uint8_t value);
void eeprom_write_word(uint16_t *addr, uint16_t value);
void eeprom_write_dword(uint32_t *addr, uint32_t value);
void eeprom_write_block(const void *buf, void *addr, uint32_t len);
int eeprom_is_ready(void);
#define eeprom_busy_wait() do {} while (!eeprom_is_ready())
static inline float eeprom_read_float(const float *addr) __attribute__((pure, always_inline, unused));
static inline float eeprom_read_float(const float *addr)
{
union {float f; uint32_t u32;} u;
u.u32 = eeprom_read_dword((const uint32_t *)addr);
return u.f;
}
static inline void eeprom_write_float(float *addr, float value) __attribute__((always_inline, unused));
static inline void eeprom_write_float(float *addr, float value)
{
union {float f; uint32_t u32;} u;
u.f = value;
eeprom_write_dword((uint32_t *)addr, u.u32);
}
static inline void eeprom_update_byte(uint8_t *addr, uint8_t value) __attribute__((always_inline, unused));
static inline void eeprom_update_byte(uint8_t *addr, uint8_t value)
{
eeprom_write_byte(addr, value);
}
static inline void eeprom_update_word(uint16_t *addr, uint16_t value) __attribute__((always_inline, unused));
static inline void eeprom_update_word(uint16_t *addr, uint16_t value)
{
eeprom_write_word(addr, value);
}
static inline void eeprom_update_dword(uint32_t *addr, uint32_t value) __attribute__((always_inline, unused));
static inline void eeprom_update_dword(uint32_t *addr, uint32_t value)
{
eeprom_write_dword(addr, value);
}
static inline void eeprom_update_float(float *addr, float value) __attribute__((always_inline, unused));
static inline void eeprom_update_float(float *addr, float value)
{
union {float f; uint32_t u32;} u;
u.f = value;
eeprom_write_dword((uint32_t *)addr, u.u32);
}
static inline void eeprom_update_block(const void *buf, void *addr, uint32_t len) __attribute__((always_inline, unused));
static inline void eeprom_update_block(const void *buf, void *addr, uint32_t len)
{
eeprom_write_block(buf, addr, len);
}
char * ultoa(unsigned long val, char *buf, int radix);
char * ltoa(long val, char *buf, int radix);
static inline char * utoa(unsigned int val, char *buf, int radix) __attribute__((always_inline, unused));
static inline char * utoa(unsigned int val, char *buf, int radix) { return ultoa(val, buf, radix); }
static inline char * itoa(int val, char *buf, int radix) __attribute__((always_inline, unused));
static inline char * itoa(int val, char *buf, int radix) { return ltoa(val, buf, radix); }
char * dtostrf(float val, int width, unsigned int precision, char *buf);
#ifdef __cplusplus
}
#endif
#endif

@ -0,0 +1,841 @@
/* Teensyduino Core Library
* http://www.pjrc.com/teensy/
* Copyright (c) 2013 PJRC.COM, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _core_pins_h_
#define _core_pins_h_
#include "mk20dx128.h"
#include "pins_arduino.h"
#define HIGH 1
#define LOW 0
#define INPUT 0
#define OUTPUT 1
#define INPUT_PULLUP 2
#define LSBFIRST 0
#define MSBFIRST 1
#define _BV(n) (1<<(n))
#define CHANGE 4
#define FALLING 2
#define RISING 3
// Pin Arduino
// 0 B16 RXD
// 1 B17 TXD
// 2 D0
// 3 A12 FTM1_CH0
// 4 A13 FTM1_CH1
// 5 D7 FTM0_CH7 OC0B/T1
// 6 D4 FTM0_CH4 OC0A
// 7 D2
// 8 D3 ICP1
// 9 C3 FTM0_CH2 OC1A
// 10 C4 FTM0_CH3 SS/OC1B
// 11 C6 MOSI/OC2A
// 12 C7 MISO
// 13 C5 SCK
// 14 D1
// 15 C0
// 16 B0 (FTM1_CH0)
// 17 B1 (FTM1_CH1)
// 18 B3 SDA
// 19 B2 SCL
// 20 D5 FTM0_CH5
// 21 D6 FTM0_CH6
// 22 C1 FTM0_CH0
// 23 C2 FTM0_CH1
// 24 A5 (FTM0_CH2)
// 25 B19
// 26 E1
// 27 C9
// 28 C8
// 29 C10
// 30 C11
// 31 E0
// 32 B18
// 33 A4 (FTM0_CH1)
// (34) analog only
// (35) analog only
// (36) analog only
// (37) analog only
// not available to user:
// A0 FTM0_CH5 SWD Clock
// A1 FTM0_CH6 USB ID
// A2 FTM0_CH7 SWD Trace
// A3 FTM0_CH0 SWD Data
#define CORE_NUM_TOTAL_PINS 34
#define CORE_NUM_DIGITAL 34
#define CORE_NUM_INTERRUPT 34
#if defined(__MK20DX128__)
#define CORE_NUM_ANALOG 14
#define CORE_NUM_PWM 10
#elif defined(__MK20DX256__)
#define CORE_NUM_ANALOG 21
#define CORE_NUM_PWM 12
#endif
#define CORE_PIN0_BIT 16
#define CORE_PIN1_BIT 17
#define CORE_PIN2_BIT 0
#define CORE_PIN3_BIT 12
#define CORE_PIN4_BIT 13
#define CORE_PIN5_BIT 7
#define CORE_PIN6_BIT 4
#define CORE_PIN7_BIT 2
#define CORE_PIN8_BIT 3
#define CORE_PIN9_BIT 3
#define CORE_PIN10_BIT 4
#define CORE_PIN11_BIT 6
#define CORE_PIN12_BIT 7
#define CORE_PIN13_BIT 5
#define CORE_PIN14_BIT 1
#define CORE_PIN15_BIT 0
#define CORE_PIN16_BIT 0
#define CORE_PIN17_BIT 1
#define CORE_PIN18_BIT 3
#define CORE_PIN19_BIT 2
#define CORE_PIN20_BIT 5
#define CORE_PIN21_BIT 6
#define CORE_PIN22_BIT 1
#define CORE_PIN23_BIT 2
#define CORE_PIN24_BIT 5
#define CORE_PIN25_BIT 19
#define CORE_PIN26_BIT 1
#define CORE_PIN27_BIT 9
#define CORE_PIN28_BIT 8
#define CORE_PIN29_BIT 10
#define CORE_PIN30_BIT 11
#define CORE_PIN31_BIT 0
#define CORE_PIN32_BIT 18
#define CORE_PIN33_BIT 4
#define CORE_PIN0_BITMASK (1<<(CORE_PIN0_BIT))
#define CORE_PIN1_BITMASK (1<<(CORE_PIN1_BIT))
#define CORE_PIN2_BITMASK (1<<(CORE_PIN2_BIT))
#define CORE_PIN3_BITMASK (1<<(CORE_PIN3_BIT))
#define CORE_PIN4_BITMASK (1<<(CORE_PIN4_BIT))
#define CORE_PIN5_BITMASK (1<<(CORE_PIN5_BIT))
#define CORE_PIN6_BITMASK (1<<(CORE_PIN6_BIT))
#define CORE_PIN7_BITMASK (1<<(CORE_PIN7_BIT))
#define CORE_PIN8_BITMASK (1<<(CORE_PIN8_BIT))
#define CORE_PIN9_BITMASK (1<<(CORE_PIN9_BIT))
#define CORE_PIN10_BITMASK (1<<(CORE_PIN10_BIT))
#define CORE_PIN11_BITMASK (1<<(CORE_PIN11_BIT))
#define CORE_PIN12_BITMASK (1<<(CORE_PIN12_BIT))
#define CORE_PIN13_BITMASK (1<<(CORE_PIN13_BIT))
#define CORE_PIN14_BITMASK (1<<(CORE_PIN14_BIT))
#define CORE_PIN15_BITMASK (1<<(CORE_PIN15_BIT))
#define CORE_PIN16_BITMASK (1<<(CORE_PIN16_BIT))
#define CORE_PIN17_BITMASK (1<<(CORE_PIN17_BIT))
#define CORE_PIN18_BITMASK (1<<(CORE_PIN18_BIT))
#define CORE_PIN19_BITMASK (1<<(CORE_PIN19_BIT))
#define CORE_PIN20_BITMASK (1<<(CORE_PIN20_BIT))
#define CORE_PIN21_BITMASK (1<<(CORE_PIN21_BIT))
#define CORE_PIN22_BITMASK (1<<(CORE_PIN22_BIT))
#define CORE_PIN23_BITMASK (1<<(CORE_PIN23_BIT))
#define CORE_PIN24_BITMASK (1<<(CORE_PIN24_BIT))
#define CORE_PIN25_BITMASK (1<<(CORE_PIN25_BIT))
#define CORE_PIN26_BITMASK (1<<(CORE_PIN26_BIT))
#define CORE_PIN27_BITMASK (1<<(CORE_PIN27_BIT))
#define CORE_PIN28_BITMASK (1<<(CORE_PIN28_BIT))
#define CORE_PIN29_BITMASK (1<<(CORE_PIN29_BIT))
#define CORE_PIN30_BITMASK (1<<(CORE_PIN30_BIT))
#define CORE_PIN31_BITMASK (1<<(CORE_PIN31_BIT))
#define CORE_PIN32_BITMASK (1<<(CORE_PIN32_BIT))
#define CORE_PIN33_BITMASK (1<<(CORE_PIN33_BIT))
#define CORE_PIN0_PORTREG GPIOB_PDOR
#define CORE_PIN1_PORTREG GPIOB_PDOR
#define CORE_PIN2_PORTREG GPIOD_PDOR
#define CORE_PIN3_PORTREG GPIOA_PDOR
#define CORE_PIN4_PORTREG GPIOA_PDOR
#define CORE_PIN5_PORTREG GPIOD_PDOR
#define CORE_PIN6_PORTREG GPIOD_PDOR
#define CORE_PIN7_PORTREG GPIOD_PDOR
#define CORE_PIN8_PORTREG GPIOD_PDOR
#define CORE_PIN9_PORTREG GPIOC_PDOR
#define CORE_PIN10_PORTREG GPIOC_PDOR
#define CORE_PIN11_PORTREG GPIOC_PDOR
#define CORE_PIN12_PORTREG GPIOC_PDOR
#define CORE_PIN13_PORTREG GPIOC_PDOR
#define CORE_PIN14_PORTREG GPIOD_PDOR
#define CORE_PIN15_PORTREG GPIOC_PDOR
#define CORE_PIN16_PORTREG GPIOB_PDOR
#define CORE_PIN17_PORTREG GPIOB_PDOR
#define CORE_PIN18_PORTREG GPIOB_PDOR
#define CORE_PIN19_PORTREG GPIOB_PDOR
#define CORE_PIN20_PORTREG GPIOD_PDOR
#define CORE_PIN21_PORTREG GPIOD_PDOR
#define CORE_PIN22_PORTREG GPIOC_PDOR
#define CORE_PIN23_PORTREG GPIOC_PDOR
#define CORE_PIN24_PORTREG GPIOA_PDOR
#define CORE_PIN25_PORTREG GPIOB_PDOR
#define CORE_PIN26_PORTREG GPIOE_PDOR
#define CORE_PIN27_PORTREG GPIOC_PDOR
#define CORE_PIN28_PORTREG GPIOC_PDOR
#define CORE_PIN29_PORTREG GPIOC_PDOR
#define CORE_PIN30_PORTREG GPIOC_PDOR
#define CORE_PIN31_PORTREG GPIOE_PDOR
#define CORE_PIN32_PORTREG GPIOB_PDOR
#define CORE_PIN33_PORTREG GPIOA_PDOR
#define CORE_PIN0_PORTSET GPIOB_PSOR
#define CORE_PIN1_PORTSET GPIOB_PSOR
#define CORE_PIN2_PORTSET GPIOD_PSOR
#define CORE_PIN3_PORTSET GPIOA_PSOR
#define CORE_PIN4_PORTSET GPIOA_PSOR
#define CORE_PIN5_PORTSET GPIOD_PSOR
#define CORE_PIN6_PORTSET GPIOD_PSOR
#define CORE_PIN7_PORTSET GPIOD_PSOR
#define CORE_PIN8_PORTSET GPIOD_PSOR
#define CORE_PIN9_PORTSET GPIOC_PSOR
#define CORE_PIN10_PORTSET GPIOC_PSOR
#define CORE_PIN11_PORTSET GPIOC_PSOR
#define CORE_PIN12_PORTSET GPIOC_PSOR
#define CORE_PIN13_PORTSET GPIOC_PSOR
#define CORE_PIN14_PORTSET GPIOD_PSOR
#define CORE_PIN15_PORTSET GPIOC_PSOR
#define CORE_PIN16_PORTSET GPIOB_PSOR
#define CORE_PIN17_PORTSET GPIOB_PSOR
#define CORE_PIN18_PORTSET GPIOB_PSOR
#define CORE_PIN19_PORTSET GPIOB_PSOR
#define CORE_PIN20_PORTSET GPIOD_PSOR
#define CORE_PIN21_PORTSET GPIOD_PSOR
#define CORE_PIN22_PORTSET GPIOC_PSOR
#define CORE_PIN23_PORTSET GPIOC_PSOR
#define CORE_PIN24_PORTSET GPIOA_PSOR
#define CORE_PIN25_PORTSET GPIOB_PSOR
#define CORE_PIN26_PORTSET GPIOE_PSOR
#define CORE_PIN27_PORTSET GPIOC_PSOR
#define CORE_PIN28_PORTSET GPIOC_PSOR
#define CORE_PIN29_PORTSET GPIOC_PSOR
#define CORE_PIN30_PORTSET GPIOC_PSOR
#define CORE_PIN31_PORTSET GPIOE_PSOR
#define CORE_PIN32_PORTSET GPIOB_PSOR
#define CORE_PIN33_PORTSET GPIOA_PSOR
#define CORE_PIN0_PORTCLEAR GPIOB_PCOR
#define CORE_PIN1_PORTCLEAR GPIOB_PCOR
#define CORE_PIN2_PORTCLEAR GPIOD_PCOR
#define CORE_PIN3_PORTCLEAR GPIOA_PCOR
#define CORE_PIN4_PORTCLEAR GPIOA_PCOR
#define CORE_PIN5_PORTCLEAR GPIOD_PCOR
#define CORE_PIN6_PORTCLEAR GPIOD_PCOR
#define CORE_PIN7_PORTCLEAR GPIOD_PCOR
#define CORE_PIN8_PORTCLEAR GPIOD_PCOR
#define CORE_PIN9_PORTCLEAR GPIOC_PCOR
#define CORE_PIN10_PORTCLEAR GPIOC_PCOR
#define CORE_PIN11_PORTCLEAR GPIOC_PCOR
#define CORE_PIN12_PORTCLEAR GPIOC_PCOR
#define CORE_PIN13_PORTCLEAR GPIOC_PCOR
#define CORE_PIN14_PORTCLEAR GPIOD_PCOR
#define CORE_PIN15_PORTCLEAR GPIOC_PCOR
#define CORE_PIN16_PORTCLEAR GPIOB_PCOR
#define CORE_PIN17_PORTCLEAR GPIOB_PCOR
#define CORE_PIN18_PORTCLEAR GPIOB_PCOR
#define CORE_PIN19_PORTCLEAR GPIOB_PCOR
#define CORE_PIN20_PORTCLEAR GPIOD_PCOR
#define CORE_PIN21_PORTCLEAR GPIOD_PCOR
#define CORE_PIN22_PORTCLEAR GPIOC_PCOR
#define CORE_PIN23_PORTCLEAR GPIOC_PCOR
#define CORE_PIN24_PORTCLEAR GPIOA_PCOR
#define CORE_PIN25_PORTCLEAR GPIOB_PCOR
#define CORE_PIN26_PORTCLEAR GPIOE_PCOR
#define CORE_PIN27_PORTCLEAR GPIOC_PCOR
#define CORE_PIN28_PORTCLEAR GPIOC_PCOR
#define CORE_PIN29_PORTCLEAR GPIOC_PCOR
#define CORE_PIN30_PORTCLEAR GPIOC_PCOR
#define CORE_PIN31_PORTCLEAR GPIOE_PCOR
#define CORE_PIN32_PORTCLEAR GPIOB_PCOR
#define CORE_PIN33_PORTCLEAR GPIOA_PCOR
#define CORE_PIN0_DDRREG GPIOB_PDDR
#define CORE_PIN1_DDRREG GPIOB_PDDR
#define CORE_PIN2_DDRREG GPIOD_PDDR
#define CORE_PIN3_DDRREG GPIOA_PDDR
#define CORE_PIN4_DDRREG GPIOA_PDDR
#define CORE_PIN5_DDRREG GPIOD_PDDR
#define CORE_PIN6_DDRREG GPIOD_PDDR
#define CORE_PIN7_DDRREG GPIOD_PDDR
#define CORE_PIN8_DDRREG GPIOD_PDDR
#define CORE_PIN9_DDRREG GPIOC_PDDR
#define CORE_PIN10_DDRREG GPIOC_PDDR
#define CORE_PIN11_DDRREG GPIOC_PDDR
#define CORE_PIN12_DDRREG GPIOC_PDDR
#define CORE_PIN13_DDRREG GPIOC_PDDR
#define CORE_PIN14_DDRREG GPIOD_PDDR
#define CORE_PIN15_DDRREG GPIOC_PDDR
#define CORE_PIN16_DDRREG GPIOB_PDDR
#define CORE_PIN17_DDRREG GPIOB_PDDR
#define CORE_PIN18_DDRREG GPIOB_PDDR
#define CORE_PIN19_DDRREG GPIOB_PDDR
#define CORE_PIN20_DDRREG GPIOD_PDDR
#define CORE_PIN21_DDRREG GPIOD_PDDR
#define CORE_PIN22_DDRREG GPIOC_PDDR
#define CORE_PIN23_DDRREG GPIOC_PDDR
#define CORE_PIN24_DDRREG GPIOA_PDDR
#define CORE_PIN25_DDRREG GPIOB_PDDR
#define CORE_PIN26_DDRREG GPIOE_PDDR
#define CORE_PIN27_DDRREG GPIOC_PDDR
#define CORE_PIN28_DDRREG GPIOC_PDDR
#define CORE_PIN29_DDRREG GPIOC_PDDR
#define CORE_PIN30_DDRREG GPIOC_PDDR
#define CORE_PIN31_DDRREG GPIOE_PDDR
#define CORE_PIN32_DDRREG GPIOB_PDDR
#define CORE_PIN33_DDRREG GPIOA_PDDR
#define CORE_PIN0_PINREG GPIOB_PDIR
#define CORE_PIN1_PINREG GPIOB_PDIR
#define CORE_PIN2_PINREG GPIOD_PDIR
#define CORE_PIN3_PINREG GPIOA_PDIR
#define CORE_PIN4_PINREG GPIOA_PDIR
#define CORE_PIN5_PINREG GPIOD_PDIR
#define CORE_PIN6_PINREG GPIOD_PDIR
#define CORE_PIN7_PINREG GPIOD_PDIR
#define CORE_PIN8_PINREG GPIOD_PDIR
#define CORE_PIN9_PINREG GPIOC_PDIR
#define CORE_PIN10_PINREG GPIOC_PDIR
#define CORE_PIN11_PINREG GPIOC_PDIR
#define CORE_PIN12_PINREG GPIOC_PDIR
#define CORE_PIN13_PINREG GPIOC_PDIR
#define CORE_PIN14_PINREG GPIOD_PDIR
#define CORE_PIN15_PINREG GPIOC_PDIR
#define CORE_PIN16_PINREG GPIOB_PDIR
#define CORE_PIN17_PINREG GPIOB_PDIR
#define CORE_PIN18_PINREG GPIOB_PDIR
#define CORE_PIN19_PINREG GPIOB_PDIR
#define CORE_PIN20_PINREG GPIOD_PDIR
#define CORE_PIN21_PINREG GPIOD_PDIR
#define CORE_PIN22_PINREG GPIOC_PDIR
#define CORE_PIN23_PINREG GPIOC_PDIR
#define CORE_PIN24_PINREG GPIOA_PDIR
#define CORE_PIN25_PINREG GPIOB_PDIR
#define CORE_PIN26_PINREG GPIOE_PDIR
#define CORE_PIN27_PINREG GPIOC_PDIR
#define CORE_PIN28_PINREG GPIOC_PDIR
#define CORE_PIN29_PINREG GPIOC_PDIR
#define CORE_PIN30_PINREG GPIOC_PDIR
#define CORE_PIN31_PINREG GPIOE_PDIR
#define CORE_PIN32_PINREG GPIOB_PDIR
#define CORE_PIN33_PINREG GPIOA_PDIR
#define CORE_PIN0_CONFIG PORTB_PCR16
#define CORE_PIN1_CONFIG PORTB_PCR17
#define CORE_PIN2_CONFIG PORTD_PCR0
#define CORE_PIN3_CONFIG PORTA_PCR12
#define CORE_PIN4_CONFIG PORTA_PCR13
#define CORE_PIN5_CONFIG PORTD_PCR7
#define CORE_PIN6_CONFIG PORTD_PCR4
#define CORE_PIN7_CONFIG PORTD_PCR2
#define CORE_PIN8_CONFIG PORTD_PCR3
#define CORE_PIN9_CONFIG PORTC_PCR3
#define CORE_PIN10_CONFIG PORTC_PCR4
#define CORE_PIN11_CONFIG PORTC_PCR6
#define CORE_PIN12_CONFIG PORTC_PCR7
#define CORE_PIN13_CONFIG PORTC_PCR5
#define CORE_PIN14_CONFIG PORTD_PCR1
#define CORE_PIN15_CONFIG PORTC_PCR0
#define CORE_PIN16_CONFIG PORTB_PCR0
#define CORE_PIN17_CONFIG PORTB_PCR1
#define CORE_PIN18_CONFIG PORTB_PCR3
#define CORE_PIN19_CONFIG PORTB_PCR2
#define CORE_PIN20_CONFIG PORTD_PCR5
#define CORE_PIN21_CONFIG PORTD_PCR6
#define CORE_PIN22_CONFIG PORTC_PCR1
#define CORE_PIN23_CONFIG PORTC_PCR2
#define CORE_PIN24_CONFIG PORTA_PCR5
#define CORE_PIN25_CONFIG PORTB_PCR19
#define CORE_PIN26_CONFIG PORTE_PCR1
#define CORE_PIN27_CONFIG PORTC_PCR9
#define CORE_PIN28_CONFIG PORTC_PCR8
#define CORE_PIN29_CONFIG PORTC_PCR10
#define CORE_PIN30_CONFIG PORTC_PCR11
#define CORE_PIN31_CONFIG PORTE_PCR0
#define CORE_PIN32_CONFIG PORTB_PCR18
#define CORE_PIN33_CONFIG PORTA_PCR4
#define CORE_ADC0_PIN 14
#define CORE_ADC1_PIN 15
#define CORE_ADC2_PIN 16
#define CORE_ADC3_PIN 17
#define CORE_ADC4_PIN 18
#define CORE_ADC5_PIN 19
#define CORE_ADC6_PIN 20
#define CORE_ADC7_PIN 21
#define CORE_ADC8_PIN 22
#define CORE_ADC9_PIN 23
#define CORE_ADC10_PIN 34
#define CORE_ADC11_PIN 35
#define CORE_ADC12_PIN 36
#define CORE_ADC13_PIN 37
#define CORE_RXD0_PIN 0
#define CORE_TXD0_PIN 1
#define CORE_RXD1_PIN 9
#define CORE_TXD1_PIN 10
#define CORE_RXD2_PIN 7
#define CORE_TXD2_PIN 8
#define CORE_INT0_PIN 0
#define CORE_INT1_PIN 1
#define CORE_INT2_PIN 2
#define CORE_INT3_PIN 3
#define CORE_INT4_PIN 4
#define CORE_INT5_PIN 5
#define CORE_INT6_PIN 6
#define CORE_INT7_PIN 7
#define CORE_INT8_PIN 8
#define CORE_INT9_PIN 9
#define CORE_INT10_PIN 10
#define CORE_INT11_PIN 11
#define CORE_INT12_PIN 12
#define CORE_INT13_PIN 13
#define CORE_INT14_PIN 14
#define CORE_INT15_PIN 15
#define CORE_INT16_PIN 16
#define CORE_INT17_PIN 17
#define CORE_INT18_PIN 18
#define CORE_INT19_PIN 19
#define CORE_INT20_PIN 20
#define CORE_INT21_PIN 21
#define CORE_INT22_PIN 22
#define CORE_INT23_PIN 23
#define CORE_INT24_PIN 24
#define CORE_INT25_PIN 25
#define CORE_INT26_PIN 26
#define CORE_INT27_PIN 27
#define CORE_INT28_PIN 28
#define CORE_INT29_PIN 29
#define CORE_INT30_PIN 30
#define CORE_INT31_PIN 31
#define CORE_INT32_PIN 32
#define CORE_INT33_PIN 33
#define CORE_INT_EVERY_PIN 1
#ifdef __cplusplus
extern "C" {
#endif
void digitalWrite(uint8_t pin, uint8_t val);
static inline void digitalWriteFast(uint8_t pin, uint8_t val) __attribute__((always_inline, unused));
static inline void digitalWriteFast(uint8_t pin, uint8_t val)
{
if (__builtin_constant_p(pin)) {
if (val) {
if (pin == 0) {
CORE_PIN0_PORTSET = CORE_PIN0_BITMASK;
} else if (pin == 1) {
CORE_PIN1_PORTSET = CORE_PIN1_BITMASK;
} else if (pin == 2) {
CORE_PIN2_PORTSET = CORE_PIN2_BITMASK;
} else if (pin == 3) {
CORE_PIN3_PORTSET = CORE_PIN3_BITMASK;
} else if (pin == 4) {
CORE_PIN4_PORTSET = CORE_PIN4_BITMASK;
} else if (pin == 5) {
CORE_PIN5_PORTSET = CORE_PIN5_BITMASK;
} else if (pin == 6) {
CORE_PIN6_PORTSET = CORE_PIN6_BITMASK;
} else if (pin == 7) {
CORE_PIN7_PORTSET = CORE_PIN7_BITMASK;
} else if (pin == 8) {
CORE_PIN8_PORTSET = CORE_PIN8_BITMASK;
} else if (pin == 9) {
CORE_PIN9_PORTSET = CORE_PIN9_BITMASK;
} else if (pin == 10) {
CORE_PIN10_PORTSET = CORE_PIN10_BITMASK;
} else if (pin == 11) {
CORE_PIN11_PORTSET = CORE_PIN11_BITMASK;
} else if (pin == 12) {
CORE_PIN12_PORTSET = CORE_PIN12_BITMASK;
} else if (pin == 13) {
CORE_PIN13_PORTSET = CORE_PIN13_BITMASK;
} else if (pin == 14) {
CORE_PIN14_PORTSET = CORE_PIN14_BITMASK;
} else if (pin == 15) {
CORE_PIN15_PORTSET = CORE_PIN15_BITMASK;
} else if (pin == 16) {
CORE_PIN16_PORTSET = CORE_PIN16_BITMASK;
} else if (pin == 17) {
CORE_PIN17_PORTSET = CORE_PIN17_BITMASK;
} else if (pin == 18) {
CORE_PIN18_PORTSET = CORE_PIN18_BITMASK;
} else if (pin == 19) {
CORE_PIN19_PORTSET = CORE_PIN19_BITMASK;
} else if (pin == 20) {
CORE_PIN20_PORTSET = CORE_PIN20_BITMASK;
} else if (pin == 21) {
CORE_PIN21_PORTSET = CORE_PIN21_BITMASK;
} else if (pin == 22) {
CORE_PIN22_PORTSET = CORE_PIN22_BITMASK;
} else if (pin == 23) {
CORE_PIN23_PORTSET = CORE_PIN23_BITMASK;
} else if (pin == 24) {
CORE_PIN24_PORTSET = CORE_PIN24_BITMASK;
} else if (pin == 25) {
CORE_PIN25_PORTSET = CORE_PIN25_BITMASK;
} else if (pin == 26) {
CORE_PIN26_PORTSET = CORE_PIN26_BITMASK;
} else if (pin == 27) {
CORE_PIN27_PORTSET = CORE_PIN27_BITMASK;
} else if (pin == 28) {
CORE_PIN28_PORTSET = CORE_PIN28_BITMASK;
} else if (pin == 29) {
CORE_PIN29_PORTSET = CORE_PIN29_BITMASK;
} else if (pin == 30) {
CORE_PIN30_PORTSET = CORE_PIN30_BITMASK;
} else if (pin == 31) {
CORE_PIN31_PORTSET = CORE_PIN31_BITMASK;
} else if (pin == 32) {
CORE_PIN32_PORTSET = CORE_PIN32_BITMASK;
} else if (pin == 33) {
CORE_PIN33_PORTSET = CORE_PIN33_BITMASK;
}
} else {
if (pin == 0) {
CORE_PIN0_PORTCLEAR = CORE_PIN0_BITMASK;
} else if (pin == 1) {
CORE_PIN1_PORTCLEAR = CORE_PIN1_BITMASK;
} else if (pin == 2) {
CORE_PIN2_PORTCLEAR = CORE_PIN2_BITMASK;
} else if (pin == 3) {
CORE_PIN3_PORTCLEAR = CORE_PIN3_BITMASK;
} else if (pin == 4) {
CORE_PIN4_PORTCLEAR = CORE_PIN4_BITMASK;
} else if (pin == 5) {
CORE_PIN5_PORTCLEAR = CORE_PIN5_BITMASK;
} else if (pin == 6) {
CORE_PIN6_PORTCLEAR = CORE_PIN6_BITMASK;
} else if (pin == 7) {
CORE_PIN7_PORTCLEAR = CORE_PIN7_BITMASK;
} else if (pin == 8) {
CORE_PIN8_PORTCLEAR = CORE_PIN8_BITMASK;
} else if (pin == 9) {
CORE_PIN9_PORTCLEAR = CORE_PIN9_BITMASK;
} else if (pin == 10) {
CORE_PIN10_PORTCLEAR = CORE_PIN10_BITMASK;
} else if (pin == 11) {
CORE_PIN11_PORTCLEAR = CORE_PIN11_BITMASK;
} else if (pin == 12) {
CORE_PIN12_PORTCLEAR = CORE_PIN12_BITMASK;
} else if (pin == 13) {
CORE_PIN13_PORTCLEAR = CORE_PIN13_BITMASK;
} else if (pin == 14) {
CORE_PIN14_PORTCLEAR = CORE_PIN14_BITMASK;
} else if (pin == 15) {
CORE_PIN15_PORTCLEAR = CORE_PIN15_BITMASK;
} else if (pin == 16) {
CORE_PIN16_PORTCLEAR = CORE_PIN16_BITMASK;
} else if (pin == 17) {
CORE_PIN17_PORTCLEAR = CORE_PIN17_BITMASK;
} else if (pin == 18) {
CORE_PIN18_PORTCLEAR = CORE_PIN18_BITMASK;
} else if (pin == 19) {
CORE_PIN19_PORTCLEAR = CORE_PIN19_BITMASK;
} else if (pin == 20) {
CORE_PIN20_PORTCLEAR = CORE_PIN20_BITMASK;
} else if (pin == 21) {
CORE_PIN21_PORTCLEAR = CORE_PIN21_BITMASK;
} else if (pin == 22) {
CORE_PIN22_PORTCLEAR = CORE_PIN22_BITMASK;
} else if (pin == 23) {
CORE_PIN23_PORTCLEAR = CORE_PIN23_BITMASK;
} else if (pin == 24) {
CORE_PIN24_PORTCLEAR = CORE_PIN24_BITMASK;
} else if (pin == 25) {
CORE_PIN25_PORTCLEAR = CORE_PIN25_BITMASK;
} else if (pin == 26) {
CORE_PIN26_PORTCLEAR = CORE_PIN26_BITMASK;
} else if (pin == 27) {
CORE_PIN27_PORTCLEAR = CORE_PIN27_BITMASK;
} else if (pin == 28) {
CORE_PIN28_PORTCLEAR = CORE_PIN28_BITMASK;
} else if (pin == 29) {
CORE_PIN29_PORTCLEAR = CORE_PIN29_BITMASK;
} else if (pin == 30) {
CORE_PIN30_PORTCLEAR = CORE_PIN30_BITMASK;
} else if (pin == 31) {
CORE_PIN31_PORTCLEAR = CORE_PIN31_BITMASK;
} else if (pin == 32) {
CORE_PIN32_PORTCLEAR = CORE_PIN32_BITMASK;
} else if (pin == 33) {
CORE_PIN33_PORTCLEAR = CORE_PIN33_BITMASK;
}
}
} else {
if (val) {
*portSetRegister(pin) = 1;
} else {
*portClearRegister(pin) = 1;
}
}
}
uint8_t digitalRead(uint8_t pin);
static inline uint8_t digitalReadFast