starting to fill in talk
Signed-off-by: Sean Cross <sean@xobs.io>
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index.html
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index.html
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<section>
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<section>
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<h3>Outline</h3>
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<h3>Outline</h3>
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<ol>
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<ol>
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<li>What is an FPGA?</li>
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<li>What is Fomu?</li>
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<li>What is this PCB?</li>
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<li>
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<ul>
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<li>Modifications made</li>
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<li>Differences to final PCB</li>
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</ul>
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</li>
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<li>Levels of Fomu</li>
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<li>
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<ol>
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<li>Python / Interpreted</li>
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<li>RISC-V</li>
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<li>Verilog / FPGA</li>
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</ol>
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</li>
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<li>Fomu Firmware Layout</li>
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<li>Fomu Firmware Layout</li>
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<li>
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<li>
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<ol>
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<ol>
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<li>Blinkenlights</li>
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<li>Blinkenlights</li>
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</ol>
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</ol>
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</section>
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</section>
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<section>
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<h2>Workshop Outline</h2>
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<ol>
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<li>What is Fomu, and what is an FPGA?</li>
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<li>What can I do with Fomu?</li>
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<li>What makes Fomu special?</li>
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</ol>
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</section>
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<section>
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<section>
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<h2>What is an FPGA?</h2>
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<p>
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An FPGA is like a hardware emulator. It can change itself so that it can take on the characteristics of any other digital logic.
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</p>
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<p>
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FPGAs are measured in resources called LUTs or LCs.
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</p>
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</section>
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<section>
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<h2>What is Fomu?</h2>
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<p>
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Fomu is an FPGA that fits in your USB port. It has foru buttons, 2 MB of SPI flash, an RGB LED, and an ICE40UP5K with 5280 LCs. It also has 128 kB of dedicated RAM, not counting the block RAM.
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Unlike many other PCBs, Fomu does not have a separate USB controller chip. This means that any projects that want to use the USB port must include a USB softcore.
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</p>
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</section>
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<section>
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<h2>What is this PCB?</h2>
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<p>
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This is Fomu EVT1. This is the original stretch prototype of Fomu. The schematics are the same, but much has changed:
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* Name changed from Tomu-FPGA to Fomu
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* Package changed from SG48 to WLCSP32
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Additionally, some patches were needed to get this PCB working:
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* SO-8 for SPI flash was too small
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* Crystal footprint was upside-down
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These are yours to take home with you!
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Differences between EVT1 and EVT3:
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* Silkscreen on Raspberry Pi header
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* Populate Raspberry Pi header
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* Add PMOD pins to touchpads
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* Swap PMODa pins for I3C
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</p>
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</section>
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<section>
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<h2>Levels of Fomu</h2>
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<p>
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Fomu aims to be accessable on three levels:
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<ol>
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<li>Python / Interpreted</li>
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<li>RISC-V</li>
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<li>Verilog / FPGA</li>
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</ol>
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</p>
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</section>
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</section>
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</div>
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</div>
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</div> <!-- class="reveal" -->
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</div> <!-- class="reveal" -->
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<!-- End of main presentation -->
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<!-- End of main presentation -->
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