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Signed-off-by: Sean Cross <sean@xobs.io>
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Sean Cross
2019-06-16 10:48:01 -07:00
parent 81fe77c179
commit e1424c4534
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<section>
<h3>Outline</h3>
<ol>
<li>What is an FPGA?</li>
<li>What is Fomu?</li>
<li>What is this PCB?</li>
<li>
<ul>
<li>Modifications made</li>
<li>Differences to final PCB</li>
</ul>
</li>
<li>Levels of Fomu</li>
<li>
<ol>
<li>Python / Interpreted</li>
<li>RISC-V</li>
<li>Verilog / FPGA</li>
</ol>
</li>
<li>Fomu Firmware Layout</li>
<li>
<ol>
@@ -135,6 +118,68 @@
<li>Blinkenlights</li>
</ol>
</section>
<section>
<h2>Workshop Outline</h2>
<ol>
<li>What is Fomu, and what is an FPGA?</li>
<li>What can I do with Fomu?</li>
<li>What makes Fomu special?</li>
</ol>
</section>
<section>
<section>
<h2>What is an FPGA?</h2>
<p>
An FPGA is like a hardware emulator. It can change itself so that it can take on the characteristics of any other digital logic.
</p>
<p>
FPGAs are measured in resources called LUTs or LCs.
</p>
</section>
<section>
<h2>What is Fomu?</h2>
<p>
Fomu is an FPGA that fits in your USB port. It has foru buttons, 2 MB of SPI flash, an RGB LED, and an ICE40UP5K with 5280 LCs. It also has 128 kB of dedicated RAM, not counting the block RAM.
Unlike many other PCBs, Fomu does not have a separate USB controller chip. This means that any projects that want to use the USB port must include a USB softcore.
</p>
</section>
<section>
<h2>What is this PCB?</h2>
<p>
This is Fomu EVT1. This is the original stretch prototype of Fomu. The schematics are the same, but much has changed:
* Name changed from Tomu-FPGA to Fomu
* Package changed from SG48 to WLCSP32
Additionally, some patches were needed to get this PCB working:
* SO-8 for SPI flash was too small
* Crystal footprint was upside-down
These are yours to take home with you!
Differences between EVT1 and EVT3:
* Silkscreen on Raspberry Pi header
* Populate Raspberry Pi header
* Add PMOD pins to touchpads
* Swap PMODa pins for I3C
</p>
</section>
<section>
<h2>Levels of Fomu</h2>
<p>
Fomu aims to be accessable on three levels:
<ol>
<li>Python / Interpreted</li>
<li>RISC-V</li>
<li>Verilog / FPGA</li>
</ol>
</p>
</section>
</section>
</div>
</div> <!-- class="reveal" -->
<!-- End of main presentation -->