From ddee9849ca98a357ce7b067d4e649408e4090fca Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Wed, 19 Jun 2019 19:36:17 -0700 Subject: [PATCH] feature-complete-ish Signed-off-by: Sean Cross --- css/theme/teardown19.css | 308 +++++++++++++++++++++++++++++++++++++ img/under-construction.gif | Bin 0 -> 17726 bytes index.html | 305 ++++++++++++++++++++++++++++++++---- 3 files changed, 584 insertions(+), 29 deletions(-) create mode 100644 css/theme/teardown19.css create mode 100644 img/under-construction.gif diff --git a/css/theme/teardown19.css b/css/theme/teardown19.css new file mode 100644 index 0000000..c55f3fe --- /dev/null +++ b/css/theme/teardown19.css @@ -0,0 +1,308 @@ +/** + * League theme for reveal.js. + * + * This was the default theme pre-3.0.0. + * + * Copyright (C) 2011-2012 Hakim El Hattab, http://hakim.se + */ +@import url(../../lib/font/league-gothic/league-gothic.css); +@import url(https://fonts.googleapis.com/css?family=Lato:400,700,400italic,700italic); +/********************************************* + * GLOBAL STYLES + *********************************************/ +body { + background: #1c1e20; + background: -moz-radial-gradient(center, circle cover, #555a5f 0%, #1c1e20 100%); + background: -webkit-gradient(radial, center center, 0px, center center, 100%, color-stop(0%, #555a5f), color-stop(100%, #1c1e20)); + background: -webkit-radial-gradient(center, circle cover, #555a5f 0%, #1c1e20 100%); + background: -o-radial-gradient(center, circle cover, #555a5f 0%, #1c1e20 100%); + background: -ms-radial-gradient(center, circle cover, #555a5f 0%, #1c1e20 100%); + background: radial-gradient(center, circle cover, #555a5f 0%, #1c1e20 100%); + background-color: #2b2b2b; } + +.reveal .footer { + position: absolute; + bottom: 1em; + right: 2em; + text-align: right; + font-size: 0.5em; + width: 100%; + height: 96px; + /*background-image: url("lca2019-logo.svg");*/ + background-repeat: no-repeat; + display: flex; + justify-content: flex-end; + align-items: flex-end; + z-index: 1; +} + +.reveal .footer .url { + position: absolute; + padding-bottom: 30px; +} + +.reveal .footer .theme { + padding-right: 80px; +} + +.reveal .footer .hashtag { + padding-right: 80px; +} + +.reveal { + font-family: "Lato", sans-serif; + font-size: 40px; + font-weight: normal; + color: #eee; } + +::selection { + color: #fff; + background: #FF5E99; + text-shadow: none; } + +::-moz-selection { + color: #fff; + background: #FF5E99; + text-shadow: none; } + +.reveal .slides section, +.reveal .slides section > section { + line-height: 1.3; + font-weight: inherit; } + +/********************************************* + * HEADERS + *********************************************/ +.reveal h1, +.reveal h2, +.reveal h3, +.reveal h4, +.reveal h5, +.reveal h6 { + margin: 0 0 20px 0; + color: #eee; + font-family: "League Gothic", Impact, sans-serif; + font-weight: normal; + line-height: 1.2; + letter-spacing: normal; + text-transform: uppercase; + text-shadow: 0px 0px 6px rgba(0, 0, 0, 0.2); + word-wrap: break-word; } + +.reveal h1 { + font-size: 3.77em; } + +.reveal h2 { + font-size: 2.11em; } + +.reveal h3 { + font-size: 1.55em; } + +.reveal h4 { + font-size: 1em; } + +.reveal h1 { + text-shadow: 0 1px 0 #ccc, 0 2px 0 #c9c9c9, 0 3px 0 #bbb, 0 4px 0 #b9b9b9, 0 5px 0 #aaa, 0 6px 1px rgba(0, 0, 0, 0.1), 0 0 5px rgba(0, 0, 0, 0.1), 0 1px 3px rgba(0, 0, 0, 0.3), 0 3px 5px rgba(0, 0, 0, 0.2), 0 5px 10px rgba(0, 0, 0, 0.25), 0 20px 20px rgba(0, 0, 0, 0.15); } + +/********************************************* + * OTHER + *********************************************/ +.reveal p { + margin: 20px 0; + line-height: 1.3; } + +/* Ensure certain elements are never larger than the slide itself */ +.reveal img, +.reveal video, +.reveal iframe { + max-width: 95%; + max-height: 95%; } + +.reveal strong, +.reveal b { + font-weight: bold; } + +.reveal em { + font-style: italic; } + +.reveal ol, +.reveal dl, +.reveal ul { + display: inline-block; + text-align: left; + margin: 0 0 0 1em; } + +.reveal ol { + list-style-type: decimal; } + +.reveal ul { + list-style-type: disc; } + +.reveal ul ul { + list-style-type: square; } + +.reveal ul ul ul { + list-style-type: circle; } + +.reveal ul ul, +.reveal ul ol, +.reveal ol ol, +.reveal ol ul { + display: block; + margin-left: 40px; } + +.reveal dt { + font-weight: bold; } + +.reveal dd { + margin-left: 40px; } + +.reveal blockquote { + display: block; + position: relative; + width: 70%; + margin: 20px auto; + padding: 5px; + font-style: italic; + background: rgba(255, 255, 255, 0.05); + box-shadow: 0px 0px 2px rgba(0, 0, 0, 0.2); } + +.reveal blockquote p:first-child, +.reveal blockquote p:last-child { + display: inline-block; } + +.reveal q { + font-style: italic; } + +.reveal pre { + display: block; + position: relative; + width: 90%; + margin: 20px auto; + text-align: left; + font-size: 0.55em; + font-family: monospace; + line-height: 1.2em; + word-wrap: break-word; + box-shadow: 0px 0px 6px rgba(0, 0, 0, 0.3); } + +.reveal code { + font-family: monospace; + text-transform: none; } + +.reveal pre code { + display: block; + padding: 5px; + overflow: auto; + max-height: 400px; + word-wrap: normal; } + +.reveal table { + margin: auto; + border-collapse: collapse; + border-spacing: 0; } + +.reveal table th { + font-weight: bold; } + +.reveal table th, +.reveal table td { + text-align: left; + padding: 0.2em 0.5em 0.2em 0.5em; + border-bottom: 1px solid; } + +.reveal table th[align="center"], +.reveal table td[align="center"] { + text-align: center; } + +.reveal table th[align="right"], +.reveal table td[align="right"] { + text-align: right; } + +.reveal table tbody tr:last-child th, +.reveal table tbody tr:last-child td { + border-bottom: none; } + +.reveal sup { + vertical-align: super; + font-size: smaller; } + +.reveal sub { + vertical-align: sub; + font-size: smaller; } + +.reveal small { + display: inline-block; + font-size: 0.6em; + line-height: 1.2em; + vertical-align: top; } + +.reveal small * { + vertical-align: top; } + +/********************************************* + * LINKS + *********************************************/ +.reveal a { + color: #13DAEC; + text-decoration: none; + -webkit-transition: color .15s ease; + -moz-transition: color .15s ease; + transition: color .15s ease; } + +.reveal a:hover { + color: #71e9f4; + text-shadow: none; + border: none; } + +.reveal .roll span:after { + color: #fff; + background: #0d99a5; } + +/********************************************* + * IMAGES + *********************************************/ +.reveal section img { + margin: 15px 0px; + background: rgba(255, 255, 255, 0.12); + border: 4px solid #eee; + box-shadow: 0 0 10px rgba(0, 0, 0, 0.15); } + +.reveal section img.plain { + border: 0; + box-shadow: none; } + +.reveal a img { + -webkit-transition: all .15s linear; + -moz-transition: all .15s linear; + transition: all .15s linear; } + +.reveal a:hover img { + background: rgba(255, 255, 255, 0.2); + border-color: #13DAEC; + box-shadow: 0 0 20px rgba(0, 0, 0, 0.55); } + +/********************************************* + * NAVIGATION CONTROLS + *********************************************/ +.reveal .controls { + color: #13DAEC; } + +/********************************************* + * PROGRESS BAR + *********************************************/ +.reveal .progress { + background: rgba(0, 0, 0, 0.2); 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zCfY5j&!9CI8pyJSBLmR_Ot$iQ)0y5LXBcMje*!}Uy!#QuQ>B%q$65^n7^K*=V$&Mj zv~G4{&0v7A`+e$g(omE@=+8b3LpT_Q%=3{RCl}rrI>}#Wg+sKo809oXE`1Q zvGk=6Vi1_X1S1$B391)j4jZTv&wK83$_@bN!4SI8M-g>Q#Nq5`9|YRhe)cxRK@M-1 z10VRnh(g%?5ugBt4J@~Hu6KPc12_OHj&TgJpF$2<$U+mEAcuCR{ppa$1k}q;`BGTE z6ua03E%rVqzoS$o5g0t-!#;~bNaFOAr@89MPWIGC{S>7*MdmYa3}e`UHl7!1MG`=Z zW;BEF#|VbyPeJ_HtKRjkk9zETf%#ovzV^l##tVL(dsR{-0=@^jP#A>*QG(Ba z4730MoKS{zSchR~30^1=tZ)#k001DkhHNMh%&>&3P>8EQ3x|k^w6KVac!ZAsNDRmj ziIE71Sk#9DA%#XLi7&W=oG1;?@C?o1iO(>FC0GzrNQvm9hNd_TQV4;hXn&+gg>9G+ zfPjkjbc(Qeinut7ws>T_*o)PNi@ykr#8`~Rc#O!HjLNu-%-D?1_>9mPjnX)c)L4zy zc#YVYjoP@4+}MrY_>JHgj^a3uS-xkMcN=^jMGfc#rs) zkNUWe{Me8F_>TY?kODc71X+*(Qk|H^hBw3Osd6FoZk}A29EZLGS`I0ahlQKDzG+C22d6PJgnUgxXlRVjz zKKYYC8I(dfltfvSMtPJ-nUqSoluX%_PWhBj8I@8wl~h@kR(X|JnUz|(m0a1CUip<^ z8J1!>mSkC$W_gxqnU-p~mTcLUZuypQ8JBW7mvmW|c6pb0nU{LGmwefme)*Sx8JL1O kn1orFhIyEXnV5>Xn2gz&j`^678JUtfnUq - + @@ -106,9 +106,9 @@

Fomu aims to be accessable on three levels:

    -
  1. Python / Interpreted
  2. -
  3. RISC-V
  4. -
  5. Verilog / FPGA
  6. +
  7. Python / Interpreter
  8. +
  9. RISC-V / C
  10. +
  11. FPGA / HDL

@@ -118,8 +118,7 @@
  1. What do I need to get started?
  2. What is an FPGA, and what is Fomu?
  3. -
  4. What makes Fomu special?
  5. -
  6. What can I do with Fomu?
  7. +
  8. Working with Fomu using Python, RISC-V, and HDL
@@ -150,7 +149,127 @@ FPGAs are measured in resources called LUTs or LCs.

--> - + + +
+

What is an FPGA?

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
0123456789101112131415
IO00000000011111111
IO10000111100001111
IO20011001100110011
IO30101010101010101
O????????????????
+

What is an FPGA?

@@ -177,6 +296,7 @@
  • 2x I2C and 2x SPI
  • 8 16-bit DSP units
  • Warmboot capability
  • +
  • Open toolchain
  • @@ -184,7 +304,7 @@

    What is Fomu?

    • ICE40UP5K
    • -
    • 2MB flash memory
    • +
    • 2MB QSPI flash memory
    • Four edge-plated pads
    • ESD protection
    • USB implemented in HDL
    • @@ -198,6 +318,11 @@
      +

      Fomu Block Design Diagram

      + Fomu block diagram +
      + +

      What is this PCB?

      Fomu EVT1

      Fomu EVT1

      @@ -234,11 +359,6 @@
    -
    -

    Fomu Block Design Diagram

    - Fomu block diagram -
    -

    Fomu SPI Flash Layout

    Fomu memory layout @@ -255,10 +375,23 @@

    Working with Fomu

    -
    +
    + +
    +

    FAT Bootloader

    +
      +
    • Presents itself as a USB disk
    • +
    • Drag and drop files to program
    • +
    • Multiple interpreter support
    • +
    +
    + +
    +
    +

    "fail safe" bootloader

    - Using dfu + Device Firmware Update - DFU

    Updating Fomu

    @@ -301,7 +434,7 @@ $ dfu-util -D new-image.dfu # Load new program

    Connecting via serial

    screen /dev/cu.usbserial*
    screen /dev/ttyACM*
    -
    Teraterm
    +
    Tera Term
    MicroPython v1.10-296-g0a5a77a on 2019-06-18; fomu with vexriscv
     >>>
    @@ -322,18 +455,21 @@ $ dfu-util -D new-image.dfu # Load new program
    >>> rgb.write_raw(0b0001, 255)
     >>> rgb.write_raw(0b1010, 14)
     >>> rgb.write_raw(0b1011, 1)
    ->>> 
    -
    +>>>

    Future Work

    - CircuitPython, etc. +
      +
    • CircuitPython
    • +
    • eLua
    • +
    • Espurino?
    • +
    -

    RISC-V code

    +

    RISC-V

    @@ -346,17 +482,33 @@ $ dfu-util -D new-image.dfu # Load new program Wishbone bridge
    +
    +

    CPU is Optional

    +
      +
    • Multiple CPUs available
    • +
    • +
        +
      • VexRiscv
      • +
      • picorv32
      • +
      • lm32
      • +
      • ...
      • +
      +
    • +
    • Also works just fine with no CPU
    • +
    +
    +

    CSR Access

    -
    #define CSR_VERSION_MAJOR_ADDR 0xe0007000L
    +					
    #define CSR_VERSION_MAJOR_ADDR 0xe0007000
     #define CSR_VERSION_MAJOR_SIZE 1
    -#define CSR_VERSION_MINOR_ADDR 0xe0007004L
    +#define CSR_VERSION_MINOR_ADDR 0xe0007004
     #define CSR_VERSION_MINOR_SIZE 1
    -#define CSR_VERSION_REVISION_ADDR 0xe0007008L
    +#define CSR_VERSION_REVISION_ADDR 0xe0007008
     #define CSR_VERSION_REVISION_SIZE 1
    -#define CSR_VERSION_GITREV_ADDR 0xe000700cL
    +#define CSR_VERSION_GITREV_ADDR 0xe000700c
     #define CSR_VERSION_GITREV_SIZE 4
    -#define CSR_VERSION_GITEXTRA_ADDR 0xe000701cL
    +#define CSR_VERSION_GITEXTRA_ADDR 0xe000701c
     #define CSR_VERSION_GITEXTRA_SIZE 2
     
    Excerpt from csr.h @@ -383,7 +535,35 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff

    Writing RISC-V Code

    +
    $ make
    +  CC       ./src/main.c        main.o
    +  CC       ./src/rgb.c rgb.o
    +  CC       ./src/time.c        time.o
    +  AS       ./src/crt0-vexriscv.S       crt0-vexriscv.o
    +  LD       riscv-blink.elf
    +  OBJCOPY  riscv-blink.bin
    +  IHEX     riscv-blink.ihex
    +$ 
    + +
    +

    Modifying RISC-V Code

    +
    --- a/riscv-blink/src/main.c
    ++++ b/riscv-blink/src/main.c
    +@@ -38,6 +38,7 @@ void isr(void) {
    + void main(void) {
    +     rgb_init();
    +     irq_setie(0);
    ++    rgb_write((100000/64000)-1, LEDDBR);
    +     int i = 0;
    +     while (1) {
    +         i++;
    +
    + +
    +

    Other RISC-V Programs

    + riscv-usb-cdcacm: echo characters back after adding 1 +
    @@ -392,18 +572,85 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff
    -

    Yosys and NextPNR

    +

    Yosys and NextPNR

    +
      +
    • Timing Driven!
    • +
    +
    Max frequency for clock 'clk12':   24.63 MHz (PASS at 12.00 MHz)
    +Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
    +Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)
    -

    Blinking an LED

    +

    Blinking an LED

    +
    $ make FOMU_REV=evt
    +...
    +20 warnings, 0 errors
    + PACK     blink.bin
    +Built 'blink' for Fomu evt1
    +$ dfu-util -D blink.bin
    -

    LiteX and MiGen

    +

    LiteX and MiGen

    +
      +
    1. Define hardware in Python
    2. +
    3. Evaluate Python to produce netlist
    4. +
    5. Synthesize netlist to FPGA
    6. +
    -
    +
    +

    lxbuildenv.py

    +
      +
    1. Python environment using native interpreter
    2. +
    3. Very stable, good for hardware projects
    4. +
    5. Should work with system Python
    6. +
    7. Runs on Linux, Windows, Raspberry Pi
    8. +
    +
    + +
    +

    Why do we need a CPU?

    + LiteX Design +
    + +
    +

    What if we remove the CPU?

    +
      +
    • Workshop project has no CPU
    • +
    • DummyUsb module automatically enumerates
    • +
    • Wishbone Debug Bridge still accessible
    • +
    +
    + +
    +

    Build Workshop Module

    +
    $ python3 workshop.py --placer heap
    +...
    +5 warnings, 0 errors
    +$ 
    +
    + +
    +

    Load onto Fomu

    +
    $ dfu-util -D build/gateware/top.bin
    +Download      [=========================] 100%    104090 bytes
    +Download done.
    +$ 
    +
    + +
    +

    Write a value to RAM

    +
    $ wishbone-tool --pid 0x5bf0 0x10000000
    +Value at 10000000: 0baf801e
    +$ wishbone-tool --pid 0x5bf0 0x10000000 0x12345678
    +$ wishbone-tool --pid 0x5bf0 0x10000000
    +Value at 10000000: 12345678
    +$ 
    +
    + +

    VexRiscv