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minor rewording of riscv-section

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Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross 2019-06-22 17:46:19 -07:00
parent 86f806f80b
commit 700a9b86d2
1 changed files with 16 additions and 4 deletions
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@ -129,9 +129,7 @@
<li>DFU utilities</li>
<li>Serial console</li>
<li>RISC-V toolchain</li>
<li>Synthesis</li>
<li>Place-and-Route</li>
<li>Packer</li>
<li>FPGA Toolchain</li>
<li>Python 3</li>
</ol>
</section>
@ -454,6 +452,17 @@ $ dfu-util -D new-image.dfu # Load new program</code></pre>
</code></pre>
</section>
<section>
<h2>Memory-Mapped Registers</h2>
<pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000
#define CSR_VERSION_MINOR_ADDR 0xe0007004
#define CSR_VERSION_REVISION_ADDR 0xe0007008</code></pre>
<pre class="fragment"><code class="python">>>> import machine
>>> machine.mem32[0xe0007000]
1
>>></code></pre>
</section>
<section>
<h2>RGB LEDD reference</h2>
<img data-src="img/ice40-ledd.png" alt="ICE40 LEDD registers">
@ -549,6 +558,9 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff</code></pre>
OBJCOPY riscv-blink.bin
IHEX riscv-blink.ihex
$ </code></pre>
<p>
From <code>riscv-blink</code> directory in <code>teardown2019-workshop</code>
</p>
</section>
<section>