minor rewording of riscv-section

Signed-off-by: Sean Cross <sean@xobs.io>

index.html

@@ -129,9 +129,7 @@
 						<li>DFU utilities</li>
 						<li>Serial console</li>
 						<li>RISC-V toolchain</li>
-						<li>Synthesis</li>
-						<li>Place-and-Route</li>
-						<li>Packer</li>
+						<li>FPGA Toolchain</li>
 						<li>Python 3</li>
 					</ol>
 				</section>
@@ -452,7 +450,18 @@ $ dfu-util -D new-image.dfu    # Load new program</code></pre>
 							>>> rgb.mode("error")
 							>>> 
 					</code></pre>
-				</section>
+                </section>
+
+                <section>
+                    <h2>Memory-Mapped Registers</h2>
+                    <pre><code class="cpp">#define CSR_VERSION_MAJOR_ADDR 0xe0007000
+#define CSR_VERSION_MINOR_ADDR 0xe0007004
+#define CSR_VERSION_REVISION_ADDR 0xe0007008</code></pre>
+                    <pre class="fragment"><code class="python">>>> import machine
+>>> machine.mem32[0xe0007000]
+1
+>>></code></pre>
+                </section>
 
 				<section>
 					<h2>RGB LEDD reference</h2>
@@ -549,6 +558,9 @@ $ wishbone-tool --pid 0x5bf0 0xe0006800 0xff</code></pre>
   OBJCOPY  riscv-blink.bin
   IHEX     riscv-blink.ihex
 $ </code></pre>
+                    <p>
+                        From <code>riscv-blink</code> directory in <code>teardown2019-workshop</code>
+                    </p>
 				</section>
 
 				<section>