commit 67423523a9462e052847f004984e2bc76c6f631a Author: Sean Cross Date: Tue Nov 26 07:43:05 2019 +0800 initial commit Signed-off-by: Sean Cross diff --git a/betrusted-soc b/betrusted-soc new file mode 100644 index 0000000..354564d Binary files /dev/null and b/betrusted-soc differ diff --git a/fb.cs b/fb.cs new file mode 100644 index 0000000..69732ae --- /dev/null +++ b/fb.cs @@ -0,0 +1,94 @@ +// +// Copyright (c) 2010 - 2019 Antmicro +// +// This file is licensed under the MIT License. +// Full license text is available in 'licenses/MIT.txt'. +// + +using System; +using System.Linq; +using Antmicro.Renode.Backends.Display; +using Antmicro.Renode.Core; +using Antmicro.Renode.Core.Structure.Registers; +using Antmicro.Renode.Logging; +using Antmicro.Renode.Peripherals.Bus; +using Antmicro.Renode.Peripherals.Memory; +using Antmicro.Renode.Utilities; + +namespace Antmicro.Renode.Peripherals.Video +{ + public class fb : AutoRepaintingVideo, IDoubleWordPeripheral, IProvidesRegisterCollection, IKnownSize + { + public fb(Machine machine) : base(machine) + { + this.machine = machine; + + RegistersCollection = new DoubleWordRegisterCollection(this); + Reconfigure(336, 536, PixelFormat.RGB565, false); + for (int i = 0; i < buffer.Length; i++) buffer[i] = 0; + DoRepaint(); + DefineRegisters(); + Reset(); + } + + public void WriteDoubleWord(long address, uint value) + { + RegistersCollection.Write(address, value); + } + + public uint ReadDoubleWord(long offset) + { + return RegistersCollection.Read(offset); + } + + public override void Reset() + { + RegistersCollection.Reset(); + } + + public long Size => 0x800; + public DoubleWordRegisterCollection RegistersCollection { get; private set; } + + protected override void Repaint() + { + var newbuf = new Byte[44*Height]; + machine.SystemBus.ReadBytes(bufferAddress, newbuf.Length, newbuf, 0); + for (int y = 0; y < Height; y++) { + if (!updateDirty || updateAll || ((newbuf[y*44+0x2a] & 0x1) == 0x1)) for (int x = 0; x < Width; x++) { + if (((newbuf[((x+y*44*8))/8] >> (x%8))&1) > 0) { + buffer[2*(x+y*Width)] = 0xFF; + buffer[2*(x+y*Width)+1] = 0xFF; + } else { + buffer[2*(x+y*Width)] = 0x0; + buffer[2*(x+y*Width)+1] = 0x0; + } + } + } + } + + private void DefineRegisters() + { + Registers.COMMAND.Define(this) + .WithValueField(0, 32, writeCallback: (_, val) => + { + updateDirty = (val & 0x1) == 0x1; + updateAll = (val & 0x10) == 0x10; + DoRepaint(); + }) + ; + } + + private bool updateDirty = false; + private bool updateAll = false; + + private uint bufferAddress = 0xB0000000; + + private readonly Machine machine; + + private enum Registers + { + COMMAND = 0x0, + BUSY = 0x04 + } + } +} diff --git a/soc.svd b/soc.svd new file mode 100644 index 0000000..697bebe --- /dev/null +++ b/soc.svd @@ -0,0 +1,2883 @@ + + + + litex + SOC + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + COM + 0xF0005800 + COM + + + TX1 + Bits 8-15 of `COM_TX`. Tx data, for MOSI. + 0x0000 + 0x00 + + + tx + 7 + [7:0] + 0 + + + + + TX0 + Bits 0-7 of `COM_TX`. + 0x0004 + 0x00 + + + tx + 7 + [7:0] + 0 + + + + + RX1 + Bits 8-15 of `COM_RX`. Rx data, from MISO + 0x0008 + 0x00 + + + rx + 7 + [7:0] + 0 + + + + + RX0 + Bits 0-7 of `COM_RX`. + 0x000c + 0x00 + + + rx + 7 + [7:0] + 0 + + + + + CONTROL + 0x0010 + 0x00 + + + clrdone + 0 + [0:0] + 0 + + + + go + 1 + [1:1] + 1 + + + + intena + 2 + [2:2] + 2 + + + + + + STATUS + 0x0014 + 0x00 + + + tip + 0 + [0:0] + 0 + + + + done + 1 + [1:1] + 1 + + + + + + EV_STATUS + 0x0018 + 0x00 + + + status + 0 + [0:0] + 0 + + + + + EV_PENDING + 0x001c + 0x00 + + + pending + 0 + [0:0] + 0 + + + + + EV_ENABLE + 0x0020 + 0x00 + + + enable + 0 + [0:0] + 0 + + + + + + 0 + 0x24 + registers + + + + I2C + 0xF0006000 + I2C + + + PRESCALE1 + Bits 8-15 of `I2C_PRESCALE`. Prescaler value. Set to (module clock / (5 * I2C +freq) - 1). Example: if module clock is equal to sysclk; syclk is 100MHz; and +I2C freq is 100kHz, then prescaler is (100MHz / (5 * 100kHz) - 1) = 199. Reset +value: 0xFFFF + 0x0000 + 0x7f + + + prescale + 7 + [7:0] + 0 + + + + + PRESCALE0 + Bits 0-7 of `I2C_PRESCALE`. + 0x0004 + 0x7f + + + prescale + 7 + [7:0] + 0 + + + + + CONTROL + 0x0008 + 0x00 + + + Resvd + 5 + [5:0] + 0 + + + + IEN + 6 + [6:6] + 6 + + + + EN + 7 + [7:7] + 7 + + + + + + TXR + Next byte to transmit to slave devices. LSB indicates R/W during address phases, +`1` for reading from slaves, `0` for writing to slaves + 0x000c + 0x00 + + + txr + 7 + [7:0] + 0 + + + + + RXR + Data being read from slaved devices + 0x0010 + 0x00 + + + rxr + 7 + [7:0] + 0 + + + + + COMMAND + 0x0014 + 0x00 + + + IACK + 0 + [0:0] + 0 + + + + Resvd + 2 + [2:1] + 1 + + + + ACK + 3 + [3:3] + 3 + + + + WR + 4 + [4:4] + 4 + + + + RD + 5 + [5:5] + 5 + + + + STO + 6 + [6:6] + 6 + + + + STA + 7 + [7:7] + 7 + + + + + + STATUS + 0x0018 + 0x00 + + + IF + 0 + [0:0] + 0 + + + + TIP + 1 + [1:1] + 1 + + + + Resvd + 4 + [4:2] + 2 + + + + ArbLost + 5 + [5:5] + 5 + + + + Busy + 6 + [6:6] + 6 + + + + RxACK + 7 + [7:7] + 7 + + + + + + EV_STATUS + 0x001c + 0x00 + + + status + 0 + [0:0] + 0 + + + + + EV_PENDING + 0x0020 + 0x00 + + + pending + 0 + [0:0] + 0 + + + + + EV_ENABLE + 0x0024 + 0x00 + + + enable + 0 + [0:0] + 0 + + + + + + 0 + 0x28 + registers + + + i2c + 2 + + + + TICKTIMER + 0xF0007800 + TICKTIMER + + + CONTROL + 0x0000 + 0x00 + + + reset + 0 + [0:0] + 0 + + + + pause + 1 + [1:1] + 1 + + + + + + TIME5 + Bits 40-47 of `TICKTIMER_TIME`. Elapsed time in systicks + 0x0004 + 0x00 + + + time + 7 + [7:0] + 0 + + + + + TIME4 + Bits 32-39 of `TICKTIMER_TIME`. + 0x0008 + 0x00 + + + time + 7 + [7:0] + 0 + + + + + TIME3 + Bits 24-31 of `TICKTIMER_TIME`. + 0x000c + 0x00 + + + time + 7 + [7:0] + 0 + + + + + TIME2 + Bits 16-23 of `TICKTIMER_TIME`. + 0x0010 + 0x00 + + + time + 7 + [7:0] + 0 + + + + + TIME1 + Bits 8-15 of `TICKTIMER_TIME`. + 0x0014 + 0x00 + + + time + 7 + [7:0] + 0 + + + + + TIME0 + Bits 0-7 of `TICKTIMER_TIME`. + 0x0018 + 0x00 + + + time + 7 + [7:0] + 0 + + + + + + 0 + 0x1c + registers + + + + INFO + 0xF0004000 + INFO + + + DNA_ID7 + Bits 56-56 of `INFO_DNA_ID`. + 0x0000 + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + DNA_ID6 + Bits 48-55 of `INFO_DNA_ID`. + 0x0004 + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + DNA_ID5 + Bits 40-47 of `INFO_DNA_ID`. + 0x0008 + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + DNA_ID4 + Bits 32-39 of `INFO_DNA_ID`. + 0x000c + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + DNA_ID3 + Bits 24-31 of `INFO_DNA_ID`. + 0x0010 + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + DNA_ID2 + Bits 16-23 of `INFO_DNA_ID`. + 0x0014 + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + DNA_ID1 + Bits 8-15 of `INFO_DNA_ID`. + 0x0018 + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + DNA_ID0 + Bits 0-7 of `INFO_DNA_ID`. + 0x001c + 0x00 + + + dna_id + 7 + [7:0] + 0 + + + + + GIT_COMMIT19 + Bits 152-159 of `INFO_GIT_COMMIT`. + 0x0020 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT18 + Bits 144-151 of `INFO_GIT_COMMIT`. + 0x0024 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT17 + Bits 136-143 of `INFO_GIT_COMMIT`. + 0x0028 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT16 + Bits 128-135 of `INFO_GIT_COMMIT`. + 0x002c + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT15 + Bits 120-127 of `INFO_GIT_COMMIT`. + 0x0030 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT14 + Bits 112-119 of `INFO_GIT_COMMIT`. + 0x0034 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT13 + Bits 104-111 of `INFO_GIT_COMMIT`. + 0x0038 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT12 + Bits 96-103 of `INFO_GIT_COMMIT`. + 0x003c + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT11 + Bits 88-95 of `INFO_GIT_COMMIT`. + 0x0040 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT10 + Bits 80-87 of `INFO_GIT_COMMIT`. + 0x0044 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT9 + Bits 72-79 of `INFO_GIT_COMMIT`. + 0x0048 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT8 + Bits 64-71 of `INFO_GIT_COMMIT`. + 0x004c + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT7 + Bits 56-63 of `INFO_GIT_COMMIT`. + 0x0050 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT6 + Bits 48-55 of `INFO_GIT_COMMIT`. + 0x0054 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT5 + Bits 40-47 of `INFO_GIT_COMMIT`. + 0x0058 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT4 + Bits 32-39 of `INFO_GIT_COMMIT`. + 0x005c + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT3 + Bits 24-31 of `INFO_GIT_COMMIT`. + 0x0060 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT2 + Bits 16-23 of `INFO_GIT_COMMIT`. + 0x0064 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT1 + Bits 8-15 of `INFO_GIT_COMMIT`. + 0x0068 + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + GIT_COMMIT0 + Bits 0-7 of `INFO_GIT_COMMIT`. + 0x006c + 0x00 + + + git_commit + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM7 + Bits 56-63 of `INFO_PLATFORM_PLATFORM`. + 0x0070 + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM6 + Bits 48-55 of `INFO_PLATFORM_PLATFORM`. + 0x0074 + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM5 + Bits 40-47 of `INFO_PLATFORM_PLATFORM`. + 0x0078 + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM4 + Bits 32-39 of `INFO_PLATFORM_PLATFORM`. + 0x007c + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM3 + Bits 24-31 of `INFO_PLATFORM_PLATFORM`. + 0x0080 + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM2 + Bits 16-23 of `INFO_PLATFORM_PLATFORM`. + 0x0084 + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM1 + Bits 8-15 of `INFO_PLATFORM_PLATFORM`. + 0x0088 + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_PLATFORM0 + Bits 0-7 of `INFO_PLATFORM_PLATFORM`. + 0x008c + 0x00 + + + platform_platform + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET7 + Bits 56-63 of `INFO_PLATFORM_TARGET`. + 0x0090 + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET6 + Bits 48-55 of `INFO_PLATFORM_TARGET`. + 0x0094 + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET5 + Bits 40-47 of `INFO_PLATFORM_TARGET`. + 0x0098 + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET4 + Bits 32-39 of `INFO_PLATFORM_TARGET`. + 0x009c + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET3 + Bits 24-31 of `INFO_PLATFORM_TARGET`. + 0x00a0 + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET2 + Bits 16-23 of `INFO_PLATFORM_TARGET`. + 0x00a4 + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET1 + Bits 8-15 of `INFO_PLATFORM_TARGET`. + 0x00a8 + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + PLATFORM_TARGET0 + Bits 0-7 of `INFO_PLATFORM_TARGET`. + 0x00ac + 0x00 + + + platform_target + 7 + [7:0] + 0 + + + + + XADC_TEMPERATURE1 + Bits 8-11 of `INFO_XADC_TEMPERATURE`. + 0x00b0 + 0x00 + + + xadc_temperature + 7 + [7:0] + 0 + + + + + XADC_TEMPERATURE0 + Bits 0-7 of `INFO_XADC_TEMPERATURE`. + 0x00b4 + 0x00 + + + xadc_temperature + 7 + [7:0] + 0 + + + + + XADC_VCCINT1 + Bits 8-11 of `INFO_XADC_VCCINT`. + 0x00b8 + 0x00 + + + xadc_vccint + 7 + [7:0] + 0 + + + + + XADC_VCCINT0 + Bits 0-7 of `INFO_XADC_VCCINT`. + 0x00bc + 0x00 + + + xadc_vccint + 7 + [7:0] + 0 + + + + + XADC_VCCAUX1 + Bits 8-11 of `INFO_XADC_VCCAUX`. + 0x00c0 + 0x00 + + + xadc_vccaux + 7 + [7:0] + 0 + + + + + XADC_VCCAUX0 + Bits 0-7 of `INFO_XADC_VCCAUX`. + 0x00c4 + 0x00 + + + xadc_vccaux + 7 + [7:0] + 0 + + + + + XADC_VCCBRAM1 + Bits 8-11 of `INFO_XADC_VCCBRAM`. + 0x00c8 + 0x00 + + + xadc_vccbram + 7 + [7:0] + 0 + + + + + XADC_VCCBRAM0 + Bits 0-7 of `INFO_XADC_VCCBRAM`. + 0x00cc + 0x00 + + + xadc_vccbram + 7 + [7:0] + 0 + + + + + + 0 + 0xd0 + registers + + + + CRG + 0xF0003800 + CRG + + + MMCM_READ + 0x0000 + 0x00 + + + mmcm_read + 0 + [0:0] + 0 + + + + + MMCM_WRITE + 0x0004 + 0x00 + + + mmcm_write + 0 + [0:0] + 0 + + + + + MMCM_DRDY + 0x0008 + 0x00 + + + mmcm_drdy + 0 + [0:0] + 0 + + + + + MMCM_ADR + 0x000c + 0x00 + + + mmcm_adr + 6 + [6:0] + 0 + + + + + MMCM_DAT_W1 + Bits 8-15 of `CRG_MMCM_DAT_W`. + 0x0010 + 0x00 + + + mmcm_dat_w + 7 + [7:0] + 0 + + + + + MMCM_DAT_W0 + Bits 0-7 of `CRG_MMCM_DAT_W`. + 0x0014 + 0x00 + + + mmcm_dat_w + 7 + [7:0] + 0 + + + + + MMCM_DAT_R1 + Bits 8-15 of `CRG_MMCM_DAT_R`. + 0x0018 + 0x00 + + + mmcm_dat_r + 7 + [7:0] + 0 + + + + + MMCM_DAT_R0 + Bits 0-7 of `CRG_MMCM_DAT_R`. + 0x001c + 0x00 + + + mmcm_dat_r + 7 + [7:0] + 0 + + + + + + 0 + 0x20 + registers + + + + KEYBOARD + 0xF0009000 + KEYBOARD + + + ROW0DAT1 + Bits 8-9 of `KEYBOARD_ROW0DAT`. Column data for the given row + 0x0000 + 0x00 + + + row0dat + 7 + [7:0] + 0 + + + + + ROW0DAT0 + Bits 0-7 of `KEYBOARD_ROW0DAT`. + 0x0004 + 0x00 + + + row0dat + 7 + [7:0] + 0 + + + + + ROW1DAT1 + Bits 8-9 of `KEYBOARD_ROW1DAT`. Column data for the given row + 0x0008 + 0x00 + + + row1dat + 7 + [7:0] + 0 + + + + + ROW1DAT0 + Bits 0-7 of `KEYBOARD_ROW1DAT`. + 0x000c + 0x00 + + + row1dat + 7 + [7:0] + 0 + + + + + ROW2DAT1 + Bits 8-9 of `KEYBOARD_ROW2DAT`. Column data for the given row + 0x0010 + 0x00 + + + row2dat + 7 + [7:0] + 0 + + + + + ROW2DAT0 + Bits 0-7 of `KEYBOARD_ROW2DAT`. + 0x0014 + 0x00 + + + row2dat + 7 + [7:0] + 0 + + + + + ROW3DAT1 + Bits 8-9 of `KEYBOARD_ROW3DAT`. Column data for the given row + 0x0018 + 0x00 + + + row3dat + 7 + [7:0] + 0 + + + + + ROW3DAT0 + Bits 0-7 of `KEYBOARD_ROW3DAT`. + 0x001c + 0x00 + + + row3dat + 7 + [7:0] + 0 + + + + + ROW4DAT1 + Bits 8-9 of `KEYBOARD_ROW4DAT`. Column data for the given row + 0x0020 + 0x00 + + + row4dat + 7 + [7:0] + 0 + + + + + ROW4DAT0 + Bits 0-7 of `KEYBOARD_ROW4DAT`. + 0x0024 + 0x00 + + + row4dat + 7 + [7:0] + 0 + + + + + ROW5DAT1 + Bits 8-9 of `KEYBOARD_ROW5DAT`. Column data for the given row + 0x0028 + 0x00 + + + row5dat + 7 + [7:0] + 0 + + + + + ROW5DAT0 + Bits 0-7 of `KEYBOARD_ROW5DAT`. + 0x002c + 0x00 + + + row5dat + 7 + [7:0] + 0 + + + + + ROW6DAT1 + Bits 8-9 of `KEYBOARD_ROW6DAT`. Column data for the given row + 0x0030 + 0x00 + + + row6dat + 7 + [7:0] + 0 + + + + + ROW6DAT0 + Bits 0-7 of `KEYBOARD_ROW6DAT`. + 0x0034 + 0x00 + + + row6dat + 7 + [7:0] + 0 + + + + + ROW7DAT1 + Bits 8-9 of `KEYBOARD_ROW7DAT`. Column data for the given row + 0x0038 + 0x00 + + + row7dat + 7 + [7:0] + 0 + + + + + ROW7DAT0 + Bits 0-7 of `KEYBOARD_ROW7DAT`. + 0x003c + 0x00 + + + row7dat + 7 + [7:0] + 0 + + + + + ROW8DAT1 + Bits 8-9 of `KEYBOARD_ROW8DAT`. Column data for the given row + 0x0040 + 0x00 + + + row8dat + 7 + [7:0] + 0 + + + + + ROW8DAT0 + Bits 0-7 of `KEYBOARD_ROW8DAT`. + 0x0044 + 0x00 + + + row8dat + 7 + [7:0] + 0 + + + + + EV_STATUS + 0x0048 + 0x00 + + + status + 0 + [0:0] + 0 + + + + + EV_PENDING + 0x004c + 0x00 + + + pending + 0 + [0:0] + 0 + + + + + EV_ENABLE + 0x0050 + 0x00 + + + enable + 0 + [0:0] + 0 + + + + + ROWCHANGE1 + Bits 8-8 of `KEYBOARD_ROWCHANGE`. The rows that changed since the last scan + 0x0054 + 0x00 + + + rowchange + 7 + [7:0] + 0 + + + + + ROWCHANGE0 + Bits 0-7 of `KEYBOARD_ROWCHANGE`. + 0x0058 + 0x00 + + + rowchange + 7 + [7:0] + 0 + + + + + + 0 + 0x5c + registers + + + keyboard + 4 + + + + MESSIBLE + 0xF0007000 + MESSIBLE + + + IN + Write half of the FIFO to send data out the Messible. Writing to this register +advances the write pointer automatically. + 0x0000 + 0x00 + + + in + 7 + [7:0] + 0 + + + + + OUT + Read half of the FIFO to receive data on the Messible. Reading from this +register advances the read pointer automatically. + 0x0004 + 0x00 + + + out + 7 + [7:0] + 0 + + + + + STATUS + 0x0008 + 0x00 + + + full + 0 + [0:0] + 0 + + + + have + 1 + [1:1] + 1 + + + + + + + 0 + 0xc + registers + + + + POWER + 0xF0008000 + POWER + + + POWER + 0x0000 + 0x0a + + + audio + 0 + [0:0] + 0 + + + + self + 1 + [1:1] + 1 + + + + ec_snoop + 2 + [2:2] + 2 + + + + state + 4 + [4:3] + 3 + + + + noisebias + 5 + [5:5] + 5 + + + + noise + 7 + [7:6] + 6 + + + + + + + 0 + 0x4 + registers + + + + UART + 0xF0001800 + UART + + + RXTX + 0x0000 + 0x00 + + + rxtx + 7 + [7:0] + 0 + + + + + TXFULL + 0x0004 + 0x00 + + + txfull + 0 + [0:0] + 0 + + + + + RXEMPTY + 0x0008 + 0x00 + + + rxempty + 0 + [0:0] + 0 + + + + + EV_STATUS + 0x000c + 0x00 + + + status + 1 + [1:0] + 0 + + + + + EV_PENDING + 0x0010 + 0x00 + + + pending + 1 + [1:0] + 0 + + + + + EV_ENABLE + 0x0014 + 0x00 + + + enable + 1 + [1:0] + 0 + + + + + + 0 + 0x18 + registers + + + uart + 0 + + + + SPINOR + 0xF0008800 + SPINOR + + + CFG1 + 0x0000 + 0x00 + + + cfg1 + 7 + [7:0] + 0 + + + + + CFG2 + 0x0004 + 0x00 + + + cfg2 + 7 + [7:0] + 0 + + + + + CFG3 + 0x0008 + 0x00 + + + cfg3 + 7 + [7:0] + 0 + + + + + CFG4 + 0x000c + 0x00 + + + cfg4 + 7 + [7:0] + 0 + + + + + STAT1 + 0x0010 + 0x00 + + + stat1 + 7 + [7:0] + 0 + + + + + STAT2 + 0x0014 + 0x00 + + + stat2 + 7 + [7:0] + 0 + + + + + STAT3 + 0x0018 + 0x00 + + + stat3 + 7 + [7:0] + 0 + + + + + STAT4 + 0x001c + 0x00 + + + stat4 + 7 + [7:0] + 0 + + + + + + 0 + 0x20 + registers + + + + SRAM_EXT + 0xF0004800 + SRAM_EXT + + + CONFIG_STATUS3 + Bits 24-31 of `SRAM_EXT_CONFIG_STATUS`. + 0x0000 + 0x00 + + + mode + 7 + [7:0] + 0 + + + + + + CONFIG_STATUS2 + Bits 16-23 of `SRAM_EXT_CONFIG_STATUS`. + 0x0004 + 0x00 + + + mode + 7 + [7:0] + 0 + + + + + + CONFIG_STATUS1 + Bits 8-15 of `SRAM_EXT_CONFIG_STATUS`. + 0x0008 + 0x00 + + + mode + 7 + [7:0] + 0 + + + + + + CONFIG_STATUS0 + Bits 0-7 of `SRAM_EXT_CONFIG_STATUS`. + 0x000c + 0x00 + + + mode + 7 + [7:0] + 0 + + + + + + READ_CONFIG + 0x0010 + 0x00 + + + trigger + 0 + [0:0] + 0 + + + + + + + 0 + 0x14 + registers + + + + MEMLCD + 0xF0005000 + MEMLCD + + + COMMAND + 0x0000 + 0x00 + + + UpdateDirty + 0 + [0:0] + 0 + + + + UpdateAll + 1 + [1:1] + 1 + + + + + + BUSY + A ``1`` indicates that the block is currently updating the LCD + 0x0004 + 0x00 + + + busy + 0 + [0:0] + 0 + + + + + PRESCALER + Prescaler value. LCD clock is module (clock / (prescaler+1)). Reset value: 99, +so for a default sysclk of 100MHz this yields an LCD SCLK of 1MHz + 0x0008 + 0x63 + + + prescaler + 7 + [7:0] + 0 + + + + + EV_STATUS + 0x000c + 0x00 + + + status + 0 + [0:0] + 0 + + + + + EV_PENDING + 0x0010 + 0x00 + + + pending + 0 + [0:0] + 0 + + + + + EV_ENABLE + 0x0014 + 0x00 + + + enable + 0 + [0:0] + 0 + + + + + + 0 + 0x18 + registers + + + + BTEVENTS + 0xF0006800 + BTEVENTS + + + EV_STATUS + 0x0000 + 0x00 + + + status + 1 + [1:0] + 0 + + + + + EV_PENDING + 0x0004 + 0x00 + + + pending + 1 + [1:0] + 0 + + + + + EV_ENABLE + 0x0008 + 0x00 + + + enable + 1 + [1:0] + 0 + + + + + + 0 + 0xc + registers + + + btevents + 3 + + + + CTRL + 0xF0000000 + CTRL + + + RESET + 0x0000 + 0x00 + + + reset + 0 + [0:0] + 0 + + + + + SCRATCH3 + Bits 24-31 of `CTRL_SCRATCH`. + 0x0004 + 0x12 + + + scratch + 7 + [7:0] + 0 + + + + + SCRATCH2 + Bits 16-23 of `CTRL_SCRATCH`. + 0x0008 + 0x34 + + + scratch + 7 + [7:0] + 0 + + + + + SCRATCH1 + Bits 8-15 of `CTRL_SCRATCH`. + 0x000c + 0x56 + + + scratch + 7 + [7:0] + 0 + + + + + SCRATCH0 + Bits 0-7 of `CTRL_SCRATCH`. + 0x0010 + 0x78 + + + scratch + 7 + [7:0] + 0 + + + + + BUS_ERRORS3 + Bits 24-31 of `CTRL_BUS_ERRORS`. + 0x0014 + 0x00 + + + bus_errors + 7 + [7:0] + 0 + + + + + BUS_ERRORS2 + Bits 16-23 of `CTRL_BUS_ERRORS`. + 0x0018 + 0x00 + + + bus_errors + 7 + [7:0] + 0 + + + + + BUS_ERRORS1 + Bits 8-15 of `CTRL_BUS_ERRORS`. + 0x001c + 0x00 + + + bus_errors + 7 + [7:0] + 0 + + + + + BUS_ERRORS0 + Bits 0-7 of `CTRL_BUS_ERRORS`. + 0x0020 + 0x00 + + + bus_errors + 7 + [7:0] + 0 + + + + + + 0 + 0x24 + registers + + + + TIMER0 + 0xF0002800 + TIMER0 + + + LOAD3 + Bits 24-31 of `TIMER0_LOAD`. Load value when Timer is (re-)enabled.In One-Shot +mode, the value written to this register specify the Timer's duration in +clock cycles. + 0x0000 + 0x00 + + + load + 7 + [7:0] + 0 + + + + + LOAD2 + Bits 16-23 of `TIMER0_LOAD`. + 0x0004 + 0x00 + + + load + 7 + [7:0] + 0 + + + + + LOAD1 + Bits 8-15 of `TIMER0_LOAD`. + 0x0008 + 0x00 + + + load + 7 + [7:0] + 0 + + + + + LOAD0 + Bits 0-7 of `TIMER0_LOAD`. + 0x000c + 0x00 + + + load + 7 + [7:0] + 0 + + + + + RELOAD3 + Bits 24-31 of `TIMER0_RELOAD`. Reload value when Timer reaches 0.In Periodic +mode, the value written to this register specify the Timer's period in +clock cycles. + 0x0010 + 0x00 + + + reload + 7 + [7:0] + 0 + + + + + RELOAD2 + Bits 16-23 of `TIMER0_RELOAD`. + 0x0014 + 0x00 + + + reload + 7 + [7:0] + 0 + + + + + RELOAD1 + Bits 8-15 of `TIMER0_RELOAD`. + 0x0018 + 0x00 + + + reload + 7 + [7:0] + 0 + + + + + RELOAD0 + Bits 0-7 of `TIMER0_RELOAD`. + 0x001c + 0x00 + + + reload + 7 + [7:0] + 0 + + + + + EN + Enable of the Timer.Set if to 1 to enable/start the Timer and 0 to disable the +Timer + 0x0020 + 0x00 + + + en + 0 + [0:0] + 0 + + + + + UPDATE_VALUE + Update of the current countdown value.A write to this register latches the +current countdown value to `value` register. + 0x0024 + 0x00 + + + update_value + 0 + [0:0] + 0 + + + + + VALUE3 + Bits 24-31 of `TIMER0_VALUE`. Latched countdown value + 0x0028 + 0x00 + + + value + 7 + [7:0] + 0 + + + + + VALUE2 + Bits 16-23 of `TIMER0_VALUE`. + 0x002c + 0x00 + + + value + 7 + [7:0] + 0 + + + + + VALUE1 + Bits 8-15 of `TIMER0_VALUE`. + 0x0030 + 0x00 + + + value + 7 + [7:0] + 0 + + + + + VALUE0 + Bits 0-7 of `TIMER0_VALUE`. + 0x0034 + 0x00 + + + value + 7 + [7:0] + 0 + + + + + EV_STATUS + 0x0038 + 0x00 + + + status + 0 + [0:0] + 0 + + + + + EV_PENDING + 0x003c + 0x00 + + + pending + 0 + [0:0] + 0 + + + + + EV_ENABLE + 0x0040 + 0x00 + + + enable + 0 + [0:0] + 0 + + + + + + 0 + 0x44 + registers + + + timer0 + 1 + + + + REBOOT + 0xF0003000 + REBOOT + + + CTRL + 0x0000 + 0x00 + + + ctrl + 7 + [7:0] + 0 + + + + + ADDR3 + Bits 24-31 of `REBOOT_ADDR`. + 0x0004 + 0x20 + + + addr + 7 + [7:0] + 0 + + + + + ADDR2 + Bits 16-23 of `REBOOT_ADDR`. + 0x0008 + 0x50 + + + addr + 7 + [7:0] + 0 + + + + + ADDR1 + Bits 8-15 of `REBOOT_ADDR`. + 0x000c + 0x00 + + + addr + 7 + [7:0] + 0 + + + + + ADDR0 + Bits 0-7 of `REBOOT_ADDR`. + 0x0010 + 0x00 + + + addr + 7 + [7:0] + 0 + + + + + + 0 + 0x14 + registers + + + + UART_PHY + 0xF0001000 + UART_PHY + + + TUNING_WORD3 + Bits 24-31 of `UART_PHY_TUNING_WORD`. + 0x0000 + 0x00 + + + tuning_word + 7 + [7:0] + 0 + + + + + TUNING_WORD2 + Bits 16-23 of `UART_PHY_TUNING_WORD`. + 0x0004 + 0x4b + + + tuning_word + 7 + [7:0] + 0 + + + + + TUNING_WORD1 + Bits 8-15 of `UART_PHY_TUNING_WORD`. + 0x0008 + 0x7f + + + tuning_word + 7 + [7:0] + 0 + + + + + TUNING_WORD0 + Bits 0-7 of `UART_PHY_TUNING_WORD`. + 0x000c + 0x5a + + + tuning_word + 7 + [7:0] + 0 + + + + + + 0 + 0x10 + registers + + + + IDENTIFIER_MEM + 0xF0002000 + IDENTIFIER_MEM + + + IDENTIFIER_MEM + 8 x 28-bit memory + 0x0000 + 0x00 + + + identifier_mem + 7 + [7:0] + 0 + + + + + + 0 + 0x4 + registers + + + + diff --git a/test.repl b/test.repl new file mode 100644 index 0000000..7cd2e3c --- /dev/null +++ b/test.repl @@ -0,0 +1,17 @@ +cpu: CPU.VexRiscv @ sysbus + cpuType: "rv32gc" + +mem: Memory.MappedMemory @ sysbus 0x20500000 + size: 0x10000 + +mem2: Memory.MappedMemory @ sysbus 0x00001000 + size: 0x40000 + +mem3: Memory.MappedMemory @ sysbus 0x40000000 + size: 0x10000000 + +fbmem: Memory.MappedMemory @ sysbus 0xB0000000 + size: 0x6000 + +fb: Video.fb @ sysbus 0xF0005000 + diff --git a/test.resc b/test.resc new file mode 100644 index 0000000..c702548 --- /dev/null +++ b/test.resc @@ -0,0 +1,7 @@ +mach create +i @fb.cs +using sysbus +machine LoadPlatformDescription "test.repl" +sysbus ApplySVD @soc.svd +sysbus LoadELF @betrusted-soc +showAnalyzer sysbus.fb